Read decision circuit and data read method

Abstract

Embodiments of the present application disclose a read decision circuit and a data reading method. A reference selection module in the read decision circuit is configured to receive a high reference voltage, a low reference voltage and a signal voltage, and output a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage and the signal voltage; a signal processing module is configured to receive the first signal voltage and the second signal voltage, and output a first full-swing voltage signal and a second full-swing voltage signal based on the first signal voltage and the second signal voltage; a pre-amplification module is configured to output a first amplified signal and a second amplified signal based on the first full-swing voltage signal and the second full-swing voltage signal; a zero adjustment module is configured to superimpose an offset voltage on the first amplified signal and the second amplified signal to obtain a first comparison signal and a second comparison signal; and a signal comparison module is configured to obtain a data reading result based on the first comparison signal and the second comparison signal.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a read decision circuit and a data reading method. Background Technology

[0002] With the widespread use of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly. As an important component of the memory read module, the read decision circuit has a significant impact on the reliability of memory data read.

[0003] Typical non-volatile memory cell structures include Figure 1 As shown, it consists of a non-volatile memory device and a transistor. The resistance state of the non-volatile memory device is variable, denoted as the high-resistance state resistance R. H and low resistance R L A typical non-volatile reference cell consists of a resistor with a known resistance or multiple non-volatile memory cells connected in series and parallel. Its purpose is to obtain a resistance value of R. ref (R ref =(R H +R L The reference resistance value is 1 / 2). The main function of the read decision circuit is to compare and amplify the small signals on the bit line and the reference bit line, thereby realizing the memory data read operation. With the miniaturization of semiconductor memory linewidth, the misalignment of modules within the semiconductor memory will seriously affect the sensing resolution of the read decision circuit. At the same time, the traditional sensing method for memory data read also seriously affects the sensing resolution of the memory read module.

[0004] Typical non-volatile memory data retrieval methods include Figure 2 As shown, the same current or voltage is applied to the non-volatile memory device and the reference cell, and the voltage or current signals output by the corresponding non-volatile memory device and the reference cell are detected. Then, the read decision circuit compares the bit line BL and the reference bit line BL. Ref Signal magnitude, outputting data information stored in non-volatile storage devices;

[0005] Currently, data stored in non-volatile storage devices is easily affected by offset voltage when being read. Summary of the Invention

[0006] The embodiments of this application provide a read decision circuit and a data reading method, which aim to improve the sensing resolution, reduce the impact of offset voltage on memory data reading, and improve the reliability of non-volatile memory data reading.

[0007] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0008] According to one aspect of the embodiments of this application, a read decision circuit is provided, the read decision circuit comprising: a reference selection module, a signal processing module, a pre-amplification module, a zero-adjustment module, and a signal comparison module; wherein, the reference selection module is configured to receive a high reference voltage, a low reference voltage, and a signal voltage, and output a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage, and the signal voltage; the signal processing module is configured to receive the first signal voltage and the second signal voltage, and output a first full-margin voltage signal and a second full-margin voltage signal based on the first signal voltage and the second signal voltage; the pre-amplification module is configured to output a first amplified signal and a second amplified signal based on the first full-margin voltage signal and the second full-margin voltage signal; the zero-adjustment module is configured to superimpose an offset voltage onto the first amplified signal and the second amplified signal to obtain a first comparison signal and a second comparison signal; the signal comparison module is configured to obtain a data read result based on the first comparison signal and the second comparison signal.

[0009] In some examples, the read decision circuit further includes: a bias module; the bias module is connected to the signal processing module and is used to provide a first common-mode voltage to the signal processing module; the bias module is connected to the zero-adjustment module and is used to provide a second common-mode voltage to the zero-adjustment module; the bias module is connected to the signal comparison module and is used to provide an enable voltage to the signal comparison module.

[0010] In some examples, the reference selection module includes: a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; a first port of the first selection switch is connected to the high reference voltage, and a second port of the first selection switch is connected to the second port of the second selection switch, for selecting and transmitting the high reference voltage; a first port of the second selection switch is connected to the signal voltage, and a second port of the second selection switch is connected to the second port of the first selection switch, for selecting and transmitting the signal voltage; a first port of the third selection switch is connected to the signal voltage, and a second port of the third selection switch is connected to the second port of the fourth selection switch, for selecting and transmitting the signal voltage; a first port of the fourth selection switch is connected to the low reference voltage, and a second port of the fourth selection switch is connected to the second port of the third selection switch, for selecting and transmitting the low reference voltage.

[0011] In some examples, the signal processing module includes: a first coupling capacitor, a second coupling capacitor, a first bias switch, and a second bias switch; a first port of the first coupling capacitor is connected to the second ports of the first selection switch and the second selection switch, and a second port of the first coupling capacitor is connected to the second port of the first bias switch and the pre-amplification module; the first coupling capacitor is used to store the input offset voltage and process the first signal voltage to output the first full-margin voltage signal; a first port of the second coupling capacitor is connected to the second ports of the third selection switch and the fourth selection switch, and a second port of the second coupling capacitor is connected to the second port of the second bias switch and the pre-amplification module; the second coupling capacitor is used to store the input offset voltage and process the second signal voltage to output the second full-margin voltage signal; a first port of the first bias switch is connected to the bias module, and a second port of the first bias switch is connected to the pre-amplification module and the second port of the first coupling capacitor, for providing a first common-mode voltage to the pre-amplification module; a first port of the second bias switch is connected to the bias module, and a second port of the second bias switch is connected to the pre-amplification module and the second port of the second coupling capacitor, for providing a first common-mode voltage to the pre-amplification module.

[0012] In some examples, the pre-amplification module includes: a first input port, a second input port, a first output port, and a second output port; the first input port is connected to the second port of the first coupling capacitor and the first bias switch, and is used to receive a first full-margin voltage signal output by the first coupling capacitor and a first common-mode voltage transmitted by the first bias switch; the second input port is connected to the second port of the second coupling capacitor and the second bias switch, and is used to receive a second full-margin voltage signal output by the second coupling capacitor and a first common-mode voltage transmitted by the second bias switch; the first output port is connected to the zero-adjustment module, and is used to output the first amplified signal based on the first full-margin voltage signal; the second output port is connected to the zero-adjustment module, and is used to output the second amplified signal based on the second full-margin voltage signal.

[0013] In some examples, the zeroing module includes: a third coupling capacitor, a fourth coupling capacitor, a third bias switch, and a fourth bias switch; the first port of the third coupling capacitor is connected to the first output port, and the second port of the third coupling capacitor is connected to the second port of the third bias switch and the signal comparison module, for superimposing the offset voltage onto the first amplified signal and the first comparison signal; the first port of the fourth coupling capacitor is connected to the second output port, and the second port of the fourth coupling capacitor is connected to the second port of the fourth bias switch and the signal comparison module, for superimposing the offset voltage onto the second amplified signal and the second comparison signal; the first port of the third bias switch is connected to the bias module, and the second port of the third bias switch is connected to the second port of the third coupling capacitor and the first port of the signal comparison module, for providing a second common-mode voltage to the signal comparison module; the first port of the fourth bias switch is connected to the bias module, and the second port of the fourth bias switch is connected to the second port of the fourth coupling capacitor and the second port of the signal comparison module, for providing a second common-mode voltage to the signal comparison module.

[0014] In some examples, the signal comparison module includes: a third input port, a fourth input port, and an output port; the third input port is connected to the third coupling capacitor of the zero-adjustment module and the second port of the third bias switch, and is used to receive the first comparison signal and the second common-mode signal output by the zero-adjustment module; the fourth input port is connected to the fourth coupling capacitor of the zero-adjustment module and the second port of the fourth bias switch, and is used to receive the second comparison signal and the second common-mode signal output by the zero-adjustment module; the output port of the signal comparison module compares the first comparison signal and the second comparison signal, and outputs the comparison result as the data reading result.

[0015] According to one aspect of the embodiments of this application, a data reading method is provided, the data reading method comprising:

[0016] It receives a high reference voltage, a low reference voltage, and a signal voltage, and outputs a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage, and the signal voltage;

[0017] Receive the first signal voltage and the second signal voltage, and output a first full margin voltage signal and a second full margin voltage signal based on the first signal voltage and the second signal voltage;

[0018] Based on the first full-margin voltage signal and the second full-margin voltage signal, output a first amplified signal and a second amplified signal;

[0019] The offset voltage is superimposed on the first amplified signal and the second amplified signal to obtain the first comparison signal and the second comparison signal;

[0020] The data reading result is obtained based on the first comparison signal and the second comparison signal.

[0021] In the technical solution provided by the embodiments of this application, a read decision circuit is provided, comprising: a reference selection module, a signal processing module, a pre-amplification module, a zero-adjustment module, and a signal comparison module; wherein, the reference selection module is used to receive a high reference voltage, a low reference voltage, and a signal voltage, and output a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage, and the signal voltage; the signal processing module is used to receive the first signal voltage and the second signal voltage, and output a first full-margin voltage signal and a second full-margin voltage signal based on the first signal voltage and the second signal voltage; the pre-amplification module is used to output a first amplified signal and a second amplified signal based on the first full-margin voltage signal and the second full-margin voltage signal; the zero-adjustment module is used to superimpose the offset voltage onto the first amplified signal and the second amplified signal to obtain a first comparison signal and a second comparison signal; the signal comparison module is used to obtain a data reading result based on the first comparison signal and the second comparison signal. The read decision circuit improves the sensing resolution and reduces the impact of offset voltage on memory data reading, thereby improving the reliability of non-volatile memory data reading.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating a typical non-volatile memory cell structure, as shown in an exemplary embodiment of this application.

[0024] Figure 2 This is a schematic diagram illustrating a typical non-volatile memory data reading method in an exemplary embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the basic structure of a read decision circuit shown in an exemplary embodiment of this application;

[0026] Figure 4 This is an exemplary embodiment of the present application illustrating a high reference bit line voltage, a bit line voltage, and a low reference bit line voltage generation schematic diagram;

[0027] Figure 5 This is a schematic diagram of the basic structure of another read decision circuit shown in an exemplary embodiment of this application;

[0028] Explanation of reference numerals in the attached figures:

[0029] 101-Read decision circuit; 1011-Reference selection module; 1012-Signal processing module; 1013-Pre-amplification module; 1014-Zeroing module; 1015-Signal comparison module; 1016-Bias module; V REF_H - High reference voltage; V REF_L -Low reference voltage; V Data -Signal voltage; V A - First signal voltage; V B -Second signal voltage; V X - First full margin voltage signal; V Y - Second full margin voltage signal; S A - First amplified signal; S B -Second amplified signal; S X - First comparison signal; S Y - Second comparison signal; S1 - First selection switch; S2 - Second selection switch; S3 - Third selection switch; S4 - Fourth selection switch; C1 - First coupling capacitor; C2 - Second coupling capacitor; S5 - First bias switch; S6 - Second bias switch; S7 - Third bias switch; S8 - Fourth bias switch; C3 - Third coupling capacitor; C4 - Second coupling capacitor. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0031] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0032] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0033] It should also be noted that "multiple" as mentioned in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0034] like Figure 3 As shown, Figure 3 This application illustrates a read decision circuit 101 according to an embodiment of the present application. The read decision circuit 101 includes: a reference selection module 1011, a signal processing module 1012, a pre-amplification module 1013, a zeroing module 1014, and a signal comparison module 1015; wherein, the reference selection module 1011 is used to receive a high reference voltage V. REF_H Low reference voltage V REF_L and signal voltage V Data And based on the high reference voltage V REF_H The low reference voltage V REF_L and the signal voltage V Data Output first signal voltage V A Second signal voltage V B The signal processing module 1012 is used to receive the first signal voltage V. A and the second signal voltage V B And based on the first signal voltage V A and the second signal voltage V B Output first full margin voltage signal V X Second full margin voltage signal V Y The pre-amplification module 1013 is used to amplify the voltage signal V based on the first full margin voltage signal. X Second full margin voltage signal V Y Output the first amplified signal S A Second amplified signal S B The zero-adjustment module 1014 is used to superimpose the offset voltage onto the first amplified signal S. A and the second amplified signal S B The first comparison signal S is obtained. X Second comparison signal S Y The signal comparison module 1015 is used to compare the first comparison signal S. X and the second comparison signal S Y The data reading results are obtained.

[0035] It is understandable, such as Figure 4 As shown, Figure 4 The figure shows the high reference voltage V. REF_H Low reference voltage VREF_L and signal voltage V Data The diagram illustrates the generation of the high reference bit line voltage, which is generated by a non-volatile memory device in a high-impedance state. This high reference bit line voltage is denoted as the high reference voltage V. REF_H (V RH The low reference bit line voltage is generated by a non-volatile memory device in a low-resistance state, and the low reference bit line reference voltage is denoted as the low reference voltage V. REF_L (V RL Bit line voltage is generated by the data cells of non-volatile memory, and is denoted as signal voltage V. Data When a non-volatile memory data cell is in a high-impedance state, then V Data =V RH When the non-volatile memory data cell is in a low-impedance state, then V Data =V RL V G_load V is the gate control signal for the load transistor. G_clamp V is the gate control signal for the clamping transistor. G_sel This is the gate control signal for the bit-line transistor.

[0036] The read decision circuit 101 comprises a reference selection module 1011, a signal processing module 1012, a pre-amplification module 1013, a zeroing module 1014, and a signal comparison module 1015. The reference selection module 1011 is used to receive and select the high reference voltage V. REF_H Signal voltage V Data and low reference voltage V REF_L Signal, and output the first signal voltage V A Second signal voltage V B The signal processing module 1012 is used to control the first signal voltage V output by the reference selection module 1011. A The second signal voltage VB is output and the first full margin voltage signal V is stored. X Second full margin voltage signal V Y Meanwhile, the bias pre-amplification module 1013 is in the linear operating region; the pre-amplification module 1013 is used to receive and amplify the first full-margin voltage signal V. X Second full margin voltage signal V Y Simultaneously, the offset voltage of the signal comparison module 1015 is reduced, and the first amplified signal S is output. A Second amplified signal S B The zero-adjustment module 1014 is used to ensure that the bias signal comparison module 1015 is in the linear operating region, and simultaneously superimposes the offset voltages of the storage pre-amplification module 1013 and the signal comparison module 1015 onto the first amplified signal S at the signal output. A Second amplified signal S BAbove, the first comparison signal S outputs an approximately zero offset voltage signal. X Second comparison signal S Y This eliminates the impact of offset voltage on the data signal voltage V during data reading. Data The effect; the signal comparison module 1015 is used to receive and compare the first comparison signal S X Second comparison signal S Y It also amplifies the output data reading results.

[0037] In some examples, the read decision circuit 101 further includes: a bias module 1016; the bias module 1016 is connected to the signal processing module 1012 and is used to provide a first common-mode voltage to the signal processing module 1012; the bias module 1016 is connected to the zero-adjustment module 1014 and is used to provide a second common-mode voltage to the zero-adjustment module 1014; the bias module 1016 is connected to the signal comparison module 1015 and is used to provide an enable voltage to the signal comparison module 1015.

[0038] The bias module 1016 is used to provide a common-mode voltage to the signal processing module 1012 and the zero-adjustment module 1014, so that the signal processing module 1012 and the zero-adjustment module 1014 are in the linear operating region, and at the same time control the signal processing module 1012 and the zero-adjustment module 1014 to store the offset voltage of the pre-amplification module 1013 and the signal comparison module 1015.

[0039] In some examples, such as the attached Figure 5 As shown, this embodiment provides a read decision circuit 101, which includes: a bias module 1016, a reference selection module 1011, a signal processing module 1012, a pre-amplification module 1013, a zero-adjustment module 1014, and a signal comparison module 1015. The bias module 1016 provides a common-mode voltage VCM to the signal processing module 1012 and the zero-adjustment module 1014, ensuring that the signal processing module 1012 and the zero-adjustment module 1014 are in the linear operating region. Simultaneously, it controls the signal processing module 1012 and the zero-adjustment module 1014 to store the offset voltage of the pre-amplification module 1013 and the signal comparison module 1015. The reference selection module 1011 is used to receive and select a high reference voltage VCM. REF_H Signal voltage V Data and low reference voltage V REF_L The signal processing module 1012 consists of a first coupling capacitor C1, a second coupling capacitor C2, a first bias switch S5, and a second bias switch S6. It is used to control the reference selection module 1011 and store the first full margin voltage signal V. X Second full margin voltage signal V Y Meanwhile, the bias pre-amplification module 1013 is in the linear operating region; the pre-amplification module 1013 receives and amplifies the signal V.X and V Y Simultaneously, the offset voltage of the signal comparison module 1015 is reduced; the zeroing module 1014 is composed of a third bias switch S7, a fourth bias switch S8, a third coupling capacitor C3, and a fourth coupling capacitor C4. The bias signal comparison module 1015 is in the linear operating region, and the offset voltages of the storage pre-amplification module 1013 and the signal comparison module 1015 are superimposed on the first fully amplified signal S. A Second amplified signal S B Above, the first comparison signal S outputs an approximately zero offset voltage signal. X Second comparison signal S Y This eliminates the impact of offset voltage on the data signal voltage V during data reading. Data The impact; the signal comparison module 1015 receives and compares signal S X and S Y It also amplifies the output data reading results.

[0040] In some examples, such as Figure 5 As shown, the reference selection module 1011 includes: a first selection switch S1, a second selection switch S2, a third selection switch S3, and a fourth selection switch S4; the first port of the first selection switch S1 is connected to the high reference voltage V. REF_H The connection is made such that the second port of the first selection switch S1 is connected to the second port of the second selection switch S2, for selecting and transmitting the high reference voltage V. REF_H The first port of the second selection switch S2 is connected to the signal voltage V. Data The second port of the second selection switch S2 is connected to the second port of the first selection switch S1 for selecting and transmitting the signal voltage V. Data The first port of the third selection switch S3 receives the signal voltage V. Data The second port of the third selection switch S3 is connected to the second port of the fourth selection switch S4 for selecting and transmitting the signal voltage V. Data The first port of the fourth selection switch S4 is connected to the low reference voltage V. REF_L The second port of the fourth selection switch S4 is connected to the second port of the third selection switch S3 for selecting and transmitting the low reference voltage V. REF_L .

[0041] The reference selection module 1011 includes a first selection switch S1, a second selection switch S2, a third selection switch S3, and a fourth selection switch S4; the first port of the first selection switch S1 receives a high reference voltage V. REF_HIts second port is connected to the second port of the second selection switch S2, and is used to select and transmit the high reference voltage V signal. REF_H The first port of the second selection switch S2 receives the signal voltage V. Data Its second port is connected to the second port of the first selection switch S1, and is used to select and transmit the signal voltage V. Data The first port of the third selection switch S3 receives the signal voltage V. Data Its second port is connected to the second port of the fourth selector switch S4, and is used to select and transmit the signal voltage V. Data The first port of the fourth selection switch S4 receives a low reference voltage V. REF_L Its second port is connected to the second port of the third selector switch S3, and is used to select and transmit the low reference voltage V. REF_L .

[0042] In some examples, the signal processing module 1012 includes: a first coupling capacitor C1, a second coupling capacitor C2, a first bias switch S5, and a second bias switch S6; the first port of the first coupling capacitor C1 is connected to the second ports of the first selection switch S1 and the second selection switch S2, and the second port of the first coupling capacitor C1 is connected to the second port of the first bias switch S5 and the pre-amplification module 1013; the first coupling capacitor C1 is used to store the input offset voltage and process the first signal voltage V. A Output the first full margin voltage signal V X The first port of the second coupling capacitor C2 is connected to the second ports of the third selection switch S3 and the fourth selection switch S4, and the second port of the second coupling capacitor C2 is connected to the second port of the second bias switch S6 and the pre-amplification module 1013. The second coupling capacitor C2 is used to store the input offset voltage and process the second signal voltage V. B Output the second full margin voltage signal V Y The first port of the first bias switch S5 is connected to the bias module 1016, and the second port of the first bias switch S5 is connected to the pre-amplification module 1013 and the second port of the first coupling capacitor C1, for providing a first common-mode voltage to the pre-amplification module 1013; the first port of the second bias switch S6 is connected to the bias module 1016, and the second port of the second bias switch S6 is connected to the pre-amplification module 1013 and the second port of the second coupling capacitor C2, for providing a first common-mode voltage to the pre-amplification module 1013.

[0043] The signal processing module 1012 includes a first coupling capacitor C1, a second coupling capacitor C2, a first bias switch S5, and a second bias switch S6. The first port of the first coupling capacitor C1 is connected to the second ports of the first selection switch S1 and the second selection switch S2, and its second port is connected to the second port of the first bias switch S5 and the first input port of the pre-amplification module 1013, used to store the input offset voltage and the first signal voltage V of the processed signal. A The first full margin voltage signal V is then output. X The first port of the second coupling capacitor C2 is connected to the second ports of the third selection switch S3 and the fourth selection switch S4, and its second port is connected to the second port of the second bias switch S6 and the second input port of the pre-amplification module 1013, for storing the input offset voltage and the second signal voltage V of the processing signal. B The second full margin voltage signal V is then output. Y The first port of the first bias switch S5 is connected to the bias module 1016, and its second port is connected to the first input port of the pre-amplification module 1013 and the second port of the first coupling capacitor C1, for providing the first common-mode voltage to the pre-amplification module 1013; the first port of the second bias switch S6 is connected to the bias module 1016, and its second port is connected to the second input port of the pre-amplification module 1013 and the second port of the second coupling capacitor C2, for providing the first common-mode voltage to the pre-amplification module 1013.

[0044] Furthermore, the signal processing module 1012 has two output signals, including the first full margin voltage signal V. X Second full margin voltage signal V Y The differential signal differs between the offset storage stage and the read decision stage. In the former stage, it is the input offset voltage of the pre-amplification module 1013, while in the latter stage, it is the input offset voltage plus the high reference voltage V. REF_H With low reference voltage V REF_L The difference.

[0045] In some examples, the pre-amplification module 1013 includes: a first input port, a second input port, a first output port, and a second output port; the first input port is connected to the second port of the first coupling capacitor C1 and the first bias switch S5, and is used to receive the first full margin voltage signal V output by the first coupling capacitor C1. X The second input port is connected to the second coupling capacitor C2 and the second port of the second bias switch S6, and is used to receive the second full margin voltage signal V output by the second coupling capacitor C2. YThe first output port is connected to the zero-adjustment module 1014, and is used to adjust the voltage based on the first full margin voltage signal V. X Output the first amplified signal S A The second output port is connected to the zero-adjustment module 1014 and is used to adjust the voltage based on the second full margin voltage signal V. Y Output the second amplified signal S B .

[0046] The pre-amplification module 1013 includes a first input port, a second input port, a first output port, and a second output port. The first input port is connected to the second port of the first coupling capacitor C1 and the first bias switch S5 of the signal processing module 1012, and is used to receive the first full-margin voltage signal VX and the first common-mode voltage output from the signal processing module 1012. The first common-mode voltage ensures the normal operation of the pre-amplification module 1013. The second input port is connected to the second port of the second coupling capacitor C2 and the second bias switch S6 of the signal processing module 1012, and is used to receive the second full-margin voltage signal and the first common-mode voltage output from the signal processing module 1012. The first common-mode voltage ensures the normal operation of the pre-amplification module 1013. The first output port of the pre-amplification module 1013 is connected to the first port of the third coupling capacitor C3 of the zeroing module 1014, and outputs the first amplified signal SX. A The second output port is connected to the first port of the fourth coupling capacitor C4 of the zeroing module 1014, and outputs the second amplified signal S. B ;

[0047] Optionally, a differential amplifier circuit structure with dual-input and dual-output is adopted. During the offset storage stage, the input offset voltage between the first input port and the second input port is amplified. During the read decision stage, the input offset voltage is amplified plus the high reference voltage V. REF_H With low reference voltage V REF_L The difference is used to achieve a full margin reading decision.

[0048] In some examples, the zeroing module 1014 includes: a third coupling capacitor C3, a fourth coupling capacitor C4, a third bias switch S7, and a fourth bias switch S8; the first port of the third coupling capacitor C3 is connected to the first output port, and the second port of the third coupling capacitor C3 is connected to the second port of the third bias switch S7 and the signal comparison module 1015, for superimposing the offset voltage onto the first amplified signal S. A The first comparison signal S is obtained XThe first port of the fourth coupling capacitor C4 is connected to the second output port, and the second port of the fourth coupling capacitor C4 is connected to the second port of the fourth bias switch S8 and the signal comparison module 1015, for superimposing the offset voltage onto the second amplified signal S. B The second comparison signal S is obtained. Y The first port of the third bias switch S7 is connected to the bias module 1016, and the second port of the third bias switch S7 is connected to the second port of the third coupling capacitor C3 and the first port of the signal comparison module 1015, for providing a second common-mode voltage to the signal comparison module 1015; the first port of the fourth bias switch S8 is connected to the bias module 1016, and the second port of the fourth bias switch S8 is connected to the second port of the fourth coupling capacitor C4 and the second port of the signal comparison module 1015, for providing a second common-mode voltage to the signal comparison module 1015.

[0049] The zeroing module 1014 includes a third coupling capacitor C3, a fourth coupling capacitor C4, a third bias switch S7, and a fourth bias switch S8. The first port of the third coupling capacitor C3 is connected to the first output port of the pre-amplification module 1013, and its second port is connected to the second port of the third bias switch S7 and the first input terminal of the signal comparison module 1015, for receiving the first amplified signal S from the pre-amplification module 1013. A The first comparison signal S of the output signal X The first port of the fourth coupling capacitor C4 is connected to the second output port of the pre-amplification module 1013, and its second port is connected to the second port of the fourth bias switch S8 and the second input terminal of the signal comparison module 1015, for receiving the second amplified signal S output by the pre-amplification module 1013. B The second comparison signal S is output later. Y The first port of the third bias switch S7 is connected to the bias module 1016, and its second port is connected to the second port of the third coupling capacitor C3 and the first input port of the signal comparison module 1015, for providing a second common-mode voltage to the signal comparison module 1015; the first port of the fourth bias switch S8 is connected to the bias module 1016, and its second port is connected to the second port of the fourth coupling capacitor C4 and the second input port of the signal comparison module 1015, for providing a second common-mode voltage to the signal comparison module 1015; furthermore, the two output terminals of the zeroing module 1014 are connected to the first comparison signal S. X Second comparison signal S Y The voltage difference between them eliminated the output offset voltage of the pre-amplifier module 1013;

[0050] The third coupling capacitor C3 and the equivalent resistance of the third bias switch S7 form a high-pass filter to filter out low-frequency noise in the output signal of the pre-amplification module 1013; the fourth coupling capacitor C4 and the equivalent resistance of the fourth bias switch S8 form a high-pass filter to filter out low-frequency noise in the output signal of the pre-amplification module 1013.

[0051] In some examples, the signal comparison module 1015 includes a third input port, a fourth input port, and an output port; the third input port is connected to the third coupling capacitor C3 of the zeroing module 1014 and the second port of the third bias switch S7, and is used to receive the first comparison signal S output by the zeroing module 1014. X and the second common-mode signal; the fourth input port is connected to the second port of the fourth coupling capacitor C4 and the fourth bias switch S8 of the zero-adjustment module 1014, and is used to receive the second comparison signal S output by the zero-adjustment module 1014. Y and the second common-mode signal; the output port of the signal comparison module 1015 will output the first comparison signal S X and the second comparison signal S Y The comparison is performed, and the comparison result is output as the data reading result.

[0052] The signal comparison module 1015 includes a third input port, a fourth input port, and an output port. The third input port is connected to the second port of the third coupling capacitor C3 and the third bias switch S7 of the zeroing module 1014, and is used to receive the output signal S1, the first comparison signal S7, from the zeroing module 1014. X The second common-mode voltage ensures the normal operation of the signal comparison module 1015;

[0053] The fourth input port of the signal comparison module 1015 is connected to the second port of the fourth coupling capacitor C4 and the fourth bias switch S8 of the zeroing module 1014, and is used to receive the output signal S of the zeroing module 1014, the second comparison signal S. Y The second common-mode voltage ensures the normal operation of the signal comparison module 1015; wherein the output port of the signal comparison module 1015 outputs the first comparison signal S. X Second comparison signal S Y The output of the data result is either a binary symbol "1" or a binary symbol "0". Optionally, a dynamic comparator structure is used, which compares the two input signals through positive feedback to obtain the result. The core of this structure is a latch structure composed of two inverters connected end to end.

[0054] A read decision circuit includes a reference selection module, a signal processing module, a pre-amplification module, a zero-adjustment module, and a signal comparison module. The reference selection module receives a high reference voltage, a low reference voltage, and a signal voltage, and outputs a first signal voltage and a second signal voltage based on these voltages. The signal processing module receives the first signal voltage and the second signal voltage, and outputs a first full-margin voltage signal and a second full-margin voltage signal based on these voltages. The pre-amplification module outputs a first amplified signal and a second amplified signal based on the first and second full-margin voltage signals. The zero-adjustment module superimposes the offset voltage onto the first and second amplified signals to obtain a first comparison signal and a second comparison signal. The signal comparison module obtains a data read result based on the first and second comparison signals. This read decision circuit improves sensing resolution and reduces the impact of offset voltage on memory data reads, thereby improving the reliability of non-volatile memory data reads.

[0055] According to one aspect of the embodiments of this application, a data reading method is provided, the method being applied to the read decision circuit described in the above embodiments, the data reading method comprising:

[0056] Receive high reference voltage V REF_H Low reference voltage V REF_L and signal voltage V Data And based on the high reference voltage V REF_H The low reference voltage V REF_L and the signal voltage V Data Output first signal voltage V A Second signal voltage V B ;

[0057] Receive the first signal voltage V A and the second signal voltage V B And based on the first signal voltage V A and the second signal voltage V B Output first full margin voltage signal V X Second full margin voltage signal V Y ;

[0058] Based on the first full margin voltage signal V X and the second full margin voltage signal V Y Output the first amplified signal S A Second amplified signal S B ;

[0059] The offset voltage is superimposed on the first amplified signal S. A and the second amplified signal S B The first comparison signal S is obtained. X Second comparison signal S Y ;

[0060] Based on the first comparison signal S X and the second comparison signal S Y The data reading results are obtained.

[0061] The data reading method includes an offset storage stage (K0), a sampling stage (K1), a hold stage (K2), a subtraction stage (K3), and a decision stage (K4). In stage K0, switches S5-S8 are closed and switches S1-S4 are open. The signal processing module 1012 bias pre-amplification module 1013 is in normal working condition, and the zeroing module 1014 stores the offset voltages of the pre-amplification module 1013 and the signal comparison module 1015 in coupling capacitors C3 and C4. In stage K1, switches S2, S4, S5, and S6 are closed and switches S1, S3, S7, and S8 are open. At this time, the two plates of coupling capacitor C1 are connected to V... Data and V CM The signal then has V H =V CM The two plates of capacitor C2 are connected to V respectively. REF_L and V CM The signal then has V L =V CM In stage K2, switches S1-S8 are open. At this time, capacitors C1 and C2 have no discharge path, and the voltage of each plate of the capacitor remains unchanged. Therefore, V H =V CM and V L =V CM In stage K3, switches S1 and S3 are closed, and switches S2, S4, and S5-S8 are open, then V H =V CM +V REF_H -V Data and VL=V CM +V Data -V REF_L In stage K4, signal comparison module 1015 compares S. X and S Y Signals are used to read data from non-volatile memory cells.

[0062] Specifically, the data reading method includes the following four steps:

[0063] A1. During the offset storage stage, the first common-mode voltage and the second common-mode voltage are provided by the bias module 1016. At this time, the input terminals of the pre-amplification module 1013 and the signal comparison module 1015 are both stable DC voltages. The differential-mode voltage of the two input terminals of the pre-amplification module 1013 is the offset voltage. The pre-amplification module 1013 amplifies the input offset voltage and stores it in the coupling capacitor of the zeroing module 1014.

[0064] A2. During the execution of the read decision phase, the reference selection module 1011 selects the high reference voltage V. REF_H Signal voltage V Data and low reference voltage V REF_L The signal is used to obtain the first signal voltage V. A Second signal voltage V B and the signal V A and V B The signal is transmitted to the signal processing module 1012 for processing, and the pre-amplification module 1013 amplifies the signal based on V from the signal processing module 1012. A and V B Output signal V X and V Y The differential mode signal between them, the output of the pre-amplifier module 1013 is based on V A and V Y Amplified signal S A and S B The zeroing module 1014 is based on S A and S B The output signal S that eliminates offset voltage X and S Y The bias module 1016 outputs an enable voltage signal V. SAE The signal comparison module 1015 compares the output signal of the zeroing module 1014 to obtain the data reading result;

[0065] Furthermore, the output signal V of the signal processing module 1012 for reading the judgment stage statement X and V Y The differential signal between them is the input offset voltage plus the high reference voltage V. REF_H With low reference voltage V REF_L The difference is the voltage difference for the full margin decision;

[0066] Among them, the output high reference voltage V REF_H Low reference voltage V REF_L and signal voltage V Data The circuit contains at least three ports, one of which is used to input the analog output value V in the storage unit. Data The two ports are used to input two different reference voltage values. The reference voltage value with the higher value is denoted as V. REF_HThe reference voltage value with the lower value is denoted as V. REF_L ;

[0067] Furthermore, the analog output values ​​in the storage unit are respectively compared with V REF_H and V REF_L Compare and obtain the corresponding differences;

[0068] Furthermore, the output result is determined to be greater than the decision threshold based on the reference voltage value with the smallest difference.

[0069] Furthermore, the decision threshold region where the simulated output value is located is determined and the discrete value corresponding to the region is output, that is, the full margin decision operation is completed.

[0070] Optionally, a high reference voltage V REF_H It is the upper limit voltage value of the decision threshold region that is higher than the decision threshold;

[0071] Optionally, a high reference voltage V REF_H This corresponds to the maximum voltage value on the memory device in a high-resistivity state;

[0072] Optionally, low reference voltage V REF_L It is the lower limit voltage value of the decision threshold region, which is lower than the decision threshold.

[0073] Optionally, low reference voltage V REF_L This corresponds to the minimum voltage value on the memory device in a low-resistance state.

[0074] At least one of the aforementioned decision thresholds is required to perform a single data read.

[0075] Furthermore, a decision threshold set is formed by one or more of the aforementioned decision thresholds;

[0076] Furthermore, the decision threshold set divides all resistance value ranges of the analog memory cell into multiple decision threshold regions;

[0077] Furthermore, for a set of inputs, the V REF_H and the V REF_L The decision threshold is greater than V. REF_L And less than the V REF_H The aforementioned decision threshold will determine the V REF_H and the V REF_L It is divided into two decision threshold regions. Optionally, one decision threshold region is defined as having a decision threshold as the upper limit and V. REF_L The lower limit region is the region where V is the decision threshold region. REF_H The region is defined by its upper limit and lower limit as the decision threshold.

[0078] Optionally, in one of the full margin decisions, when the analog output value V in the storage cell... Data If the value is higher than the aforementioned decision threshold, the binary symbol "1" is output; otherwise, the binary symbol "0" is output.

[0079] Based on the same concept, this embodiment also provides a memory cell array, which includes multiple memory blocks, each of the multiple memory blocks including multiple memory cells, each memory cell containing at least one memory device, each memory device having two or more resistance states and being switchable between different resistance states; optionally, the different resistance states have different resistance values; optionally, the resistance states have non-volatile characteristics.

[0080] Furthermore, by writing an analog input value into the storage unit, the data is stored in the storage device of the analog storage unit in the form of a certain resistive state;

[0081] Optionally, the devices include those based on magnetic tunnel junctions, those based on resistive switching materials, those based on ferroelectric capacitors, and those based on amorphous oxide thin-film transistors.

[0082] Optionally, the device based on the magnetic tunnel junction can be a read head, a sensitive amplifier, a sensor, or a memory chip, including address decoders, control circuits, and other peripheral circuits of the memory chip.

[0083] Optionally, when the magnetic tunnel junction-based device is a memory computing chip, the high reference V REF_H The reference signal is generated by connecting two or more sets of non-volatile memory cells storing logic "0" and logic "1" in series and parallel. The low reference reference V REF_L The reference signal is generated by connecting two or more sets of non-volatile memory cells containing logic "0" and logic "1" in series and parallel.

[0084] Other embodiments of this application will readily conceive of by considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0085] The above content is merely a preferred exemplary embodiment of this application and is not intended to limit the implementation of this application. Those skilled in the art can easily make corresponding modifications or alterations based on the main concept and spirit of this application. Therefore, the scope of protection of this application should be determined by the scope of protection claimed in the claims.

Claims

1. A read decision circuit, characterized in that, The read decision circuit includes: a reference selection module, a signal processing module, a pre-amplification module, a zeroing module, and a signal comparison module; wherein, The reference selection module is used to receive a high reference voltage, a low reference voltage, and a signal voltage, and output a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage, and the signal voltage; The signal processing module is used to receive the first signal voltage and the second signal voltage, and output a first full margin voltage signal and a second full margin voltage signal based on the first signal voltage and the second signal voltage; The pre-amplification module is used to output a first amplified signal and a second amplified signal based on the first full-margin voltage signal and the second full-margin voltage signal; The zero-adjustment module is used to superimpose the offset voltage onto the first amplified signal and the second amplified signal to obtain a first comparison signal and a second comparison signal; The signal comparison module is used to obtain data reading results based on the first comparison signal and the second comparison signal; Specifically, the differential signal between the first full-margin voltage signal and the second full-margin voltage signal at the two output terminals of the signal processing module differs between the offset storage stage and the read decision stage. In the offset storage stage, it is the input offset voltage of the pre-amplification module, while in the read decision stage, it is the input offset voltage plus the difference between the high reference voltage and the low reference voltage. The pre-amplification module adopts a differential amplifier circuit structure with dual-ended input and dual-ended output. In the offset storage stage, it amplifies the input offset voltage between the first input port and the second input port. In the read decision stage, it amplifies the input offset voltage plus the difference between the high reference voltage and the low reference voltage to achieve full-margin read decision.

2. The read decision circuit according to claim 1, characterized in that, The read decision circuit also includes: a bias module; The bias module is connected to the signal processing module and is used to provide a first common-mode voltage to the signal processing module. The bias module is connected to the zero-adjustment module and is used to provide a second common-mode voltage to the zero-adjustment module; The bias module is connected to the signal comparison module and is used to provide an enable voltage for the signal comparison module.

3. The read decision circuit according to claim 2, characterized in that, The reference selection module includes: a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; The first port of the first selection switch is connected to the high reference voltage, and the second port of the first selection switch is connected to the second port of the second selection switch, for selecting and transmitting the high reference voltage; The first port of the second selection switch is connected to the signal voltage, and the second port of the second selection switch is connected to the second port of the first selection switch, for selecting and transmitting the signal voltage; The first port of the third selection switch receives and is connected to the signal voltage, and the second port of the third selection switch is connected to the second port of the fourth selection switch, for selecting and transmitting the signal voltage; The first port of the fourth selector switch is connected to the low reference voltage, and the second port of the fourth selector switch is connected to the second port of the third selector switch, for selecting and transmitting the low reference voltage.

4. The read decision circuit according to claim 3, characterized in that, The signal processing module includes: a first coupling capacitor, a second coupling capacitor, a first bias switch, and a second bias switch; The first port of the first coupling capacitor is connected to the second port of the first selection switch and the second selection switch. The second port of the first coupling capacitor is connected to the second port of the first bias switch and the pre-amplification module. The first coupling capacitor is used to store the input offset voltage and process the first signal voltage to output the first full margin voltage signal. The first port of the second coupling capacitor is connected to the second ports of the third and fourth selection switches, the second port of the second coupling capacitor is connected to the second port of the second bias switch and the pre-amplification module, and the second coupling capacitor is used to store the input offset voltage and process the second signal voltage to output the second full margin voltage signal. The first port of the first bias switch is connected to the bias module, and the second port of the first bias switch is connected to the pre-amplification module and the second port of the first coupling capacitor, for providing a first common-mode voltage to the pre-amplification module; The first port of the second bias switch is connected to the bias module, and the second port of the second bias switch is connected to the pre-amplification module and the second port of the second coupling capacitor, for providing a first common-mode voltage to the pre-amplification module.

5. The read decision circuit according to claim 4, characterized in that, The pre-amplification module includes: a first input port, a second input port, a first output port, and a second output port; The first input port is connected to the second port of the first coupling capacitor and the first bias switch, and is used to receive the first full margin voltage signal output by the first coupling capacitor and the first common mode voltage transmitted by the first bias switch. The second input port is connected to the second port of the second coupling capacitor and the second bias switch, and is used to receive the second full margin voltage signal output by the second coupling capacitor and the first common mode voltage transmitted by the second bias switch; The first output port is connected to the zero-adjustment module and is used to output the first amplified signal based on the first full margin voltage signal; The second output port is connected to the zeroing module and is used to output the second amplified signal based on the second full margin voltage signal.

6. The read decision circuit according to claim 5, characterized in that, The zeroing module includes: a third coupling capacitor, a fourth coupling capacitor, a third bias switch, and a fourth bias switch; The first port of the third coupling capacitor is connected to the first output port, and the second port of the third coupling capacitor is connected to the second port of the third bias switch and the signal comparison module, for superimposing the offset voltage onto the first amplified signal to obtain the first comparison signal; The first port of the fourth coupling capacitor is connected to the second output port, and the second port of the fourth coupling capacitor is connected to the second port of the fourth bias switch and the signal comparison module, for superimposing the offset voltage onto the second amplified signal to obtain the second comparison signal; The first port of the third bias switch is connected to the bias module, and the second port of the third bias switch is connected to the second port of the third coupling capacitor and the first port of the signal comparison module, for providing a second common-mode voltage to the signal comparison module; The first port of the fourth bias switch is connected to the bias module, and the second port of the fourth bias switch is connected to the second port of the fourth coupling capacitor and the second port of the signal comparison module, for providing a second common-mode voltage to the signal comparison module.

7. The read decision circuit according to claim 6, characterized in that, The signal comparison module includes: a third input port, a fourth input port, and an output port; The third input port is connected to the third coupling capacitor of the zero-adjustment module and the second port of the third bias switch, and is used to receive the first comparison signal and the second common-mode signal output by the zero-adjustment module; The fourth input port is connected to the second port of the fourth coupling capacitor and the fourth bias switch of the zero-adjustment module, and is used to receive the second comparison signal and the second common-mode signal output by the zero-adjustment module; The output port of the signal comparison module compares the first comparison signal and the second comparison signal, and outputs the comparison result as the data reading result.

8. A data reading method, characterized in that, The data reading method includes: It receives a high reference voltage, a low reference voltage, and a signal voltage, and outputs a first signal voltage and a second signal voltage based on the high reference voltage, the low reference voltage, and the signal voltage; Receive the first signal voltage and the second signal voltage, and output a first full margin voltage signal and a second full margin voltage signal based on the first signal voltage and the second signal voltage; Based on the first full-margin voltage signal and the second full-margin voltage signal, output a first amplified signal and a second amplified signal; The offset voltage is superimposed on the first amplified signal and the second amplified signal to obtain the first comparison signal and the second comparison signal; The data reading result is obtained based on the first comparison signal and the second comparison signal; Among them, the differential signal between the first full margin voltage signal and the second full margin voltage signal is different in the offset storage stage and the read decision stage. In the offset storage stage, it is the input offset voltage of the pre-amplification module, and in the read decision stage, it is the input offset voltage plus the difference between the high reference voltage and the low reference voltage. The step of outputting a first amplified signal and a second amplified signal based on the first full-margin voltage signal and the second full-margin voltage signal includes: During the offset storage stage, the input offset voltage between the first input port and the second input port is amplified. During the read decision stage, the input offset voltage is amplified and the difference between the high reference voltage and the low reference voltage is added to achieve full margin read decision.

Images