A super junction type semiconductor device and a manufacturing method thereof

Abstract

The application discloses a super-junction type semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate of a first semiconductor type; forming at least two epitaxial layers on the surface of the substrate in sequence; in the growth of each epitaxial layer, injecting deep level impurity ions into the upper region of each epitaxial layer to form deep level recombination centers; making each deep level recombination center and the epitaxial layer of the lower region to be intermittently gradient distributed; injecting ions of a second conductor type into the upper region of each epitaxial layer to obtain a columnar structure, which is used for longitudinally connecting to form a column region; forming a gate structure on the epitaxial layer of the topmost layer; injecting ions of the second conductor type into the surface of the epitaxial layer to form a body region; injecting ions of the first semiconductor type into the surface of the epitaxial layer to form a source region; manufacturing a front metal layer on the gate structure; and manufacturing a back metal layer. The application can improve the reverse recovery capability of the body diode in the semiconductor device without additional manufacturing procedures and time.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a superjunction semiconductor device and its fabrication method. Background Technology

[0002] In the prior art, in order to improve the fast recovery capability of the body diode of superjunction semiconductor devices (superjunction MOSFET devices), it is usually necessary to bombard the silicon wafer with external electron / neutron irradiation or to use a heavy metal source (platinum / gold) for high-temperature thermal diffusion to cause crystal atomic displacement or generate defects, thereby forming deep energy level recombination centers, so as to reduce the minority carrier lifetime in the body diode of the device and achieve the purpose of reducing the reverse recovery time.

[0003] However, the above-mentioned semiconductor device processing methods have the following drawbacks: on the one hand, they require additional manufacturing processes and are costly; on the other hand, the above processing methods require foundry platforms for manufacturing, but due to the large differences in process control levels among different foundry platforms, consistency is uncontrollable, and there are many combinations of process menu conditions, resulting in long process correction and optimization times; furthermore, if the foundry platform chooses to outsource secondary manufacturing, it may prolong the manufacturing time and affect the production efficiency of the product. Summary of the Invention

[0004] Therefore, it is necessary to provide a superjunction semiconductor device and its fabrication method to address the above-mentioned technical problems, so as to solve the problem that the existing technology requires additional manufacturing processes and time to improve the reverse recovery capability of the body diode in the semiconductor device, resulting in low semiconductor device fabrication efficiency.

[0005] To achieve the above objectives, in a first aspect, a method for fabricating a superjunction semiconductor device is provided, comprising the following steps:

[0006] Provide a substrate of the first semiconductor type;

[0007] At least two epitaxial layers are sequentially formed on the surface of the substrate, and the conductor type of each epitaxial layer is a first semiconductor type; during the sequential growth of each epitaxial layer, deep-level impurity ions are injected into the upper region of each epitaxial layer to form deep-level recombination centers; so that each deep-level recombination center and each lower region of the epitaxial layer are intermittently gradient distributed;

[0008] Ions of a second conductor type are injected into the upper region of each of the epitaxial layers to obtain columnar structures, and each columnar structure is used to form a columnar region by longitudinal connection;

[0009] forming a gate structure on the topmost epitaxial layer; implanting ions of a second semiconductor type into the surface of the topmost epitaxial layer to form a body region; implanting ions of a first semiconductor type into the surface of the topmost epitaxial layer to form a source region in the body region;

[0010] forming a front metal layer on the gate structure; and forming a back metal layer.

[0011] Optionally, the columnar structures are longitudinally connected to form column regions.

[0012] The columnar structures are longitudinally connected to form the column regions by a high-temperature annealing process to repair defects of part of the deep energy level recombination centers distributed in the column regions.

[0013] Optionally, after the body region is formed, the method further comprises:

[0014] The ions in the body region are redistributed by the high-temperature annealing process again to control the defect distribution of the deep energy level recombination centers distributed in the body region.

[0015] Optionally, the body region is provided with deep energy level recombination centers in the topmost epitaxial layer.

[0016] Optionally, the forming of the gate structure on the topmost epitaxial layer comprises:

[0017] forming a gate oxide layer on the topmost epitaxial layer, and forming a polysilicon layer on the upper surface of the gate oxide layer to obtain the gate structure.

[0018] In a second aspect, an ultra-junction type semiconductor device is provided, which comprises:

[0019] a substrate of a first semiconductor type;

[0020] The substrate is provided with at least two epitaxial layers, each epitaxial layer being of the first semiconductor type; each epitaxial layer comprises an upper region and a lower region, each upper region being implanted with deep energy level impurity ions to form deep energy level recombination centers; and each deep energy level recombination center and the lower region of each epitaxial layer are intermittently gradient-distributed;

[0021] a column region formed by longitudinally connecting columnar structures provided in part of the lower regions of each epitaxial layer; the column region is provided with a body region and a source region in the body region;

[0022] The substrate is provided with a gate structure on the topmost epitaxial layer, and is provided with a front metal layer on the gate structure; and is provided with a back metal layer on the lower surface of the substrate.

[0023] Optionally, the body region is distributed in part of the deep-level recombination center and part of the lower region in the topmost epitaxial layer.

[0024] Optionally, the gate structure includes:

[0025] A gate oxide layer, wherein the gate oxide layer is disposed on the surface of the topmost epitaxial layer;

[0026] A polysilicon layer is disposed on the upper surface of the gate oxide layer.

[0027] Optionally, an insulating dielectric layer is provided on the upper surface of the polysilicon layer and on both sides of the gate oxide layer.

[0028] Optionally, the front metal layer is disposed on the upper surface of the insulating dielectric layer and on the upper surface of the body region and the source region.

[0029] The above technical solution has the following beneficial effects:

[0030] The superjunction semiconductor device and its fabrication method of the present invention, in the fabrication process, from the epitaxial layer growth stage, by growing multiple epitaxial layers, so that the recombination centers of deep-level impurity ions injected into each epitaxial layer form an intermittent gradient distribution with the epitaxial layer in the lower region, thereby fabricating a semiconductor device with multiple deep-level recombination centers introduced in the bulk, reducing the lifetime and concentration of minority carriers, and reducing the reverse recovery time of the bulk diode in the semiconductor device without affecting the breakdown voltage and other parameter performance, thus improving the reverse recovery capability of the bulk diode in the semiconductor device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart of a superjunction semiconductor device and its fabrication method provided in one embodiment of the present invention;

[0033] Figure 2 This is a substrate structure diagram of a first semiconductor type provided in one embodiment of the present invention;

[0034] Figure 3 This is a diagram of an epitaxial layer structure formed sequentially on a substrate surface, provided in one embodiment of the present invention;

[0035] Figure 4 This is a diagram showing the formation of a columnar structure provided in one embodiment of the present invention;

[0036] Figure 5 is a diagram of forming column structures by each epitaxial layer in an embodiment of the present application;

[0037] Figure 6 is a diagram of forming column region structures by each column structure longitudinally communicating in an embodiment of the present application;

[0038] Figure 7 is a diagram of forming a gate structure on the topmost epitaxial layer in an embodiment of the present application;

[0039] Figure 8 is a diagram of forming a body region and a source region in the body region in an embodiment of the present application;

[0040] Figure 9 is a diagram of making a front metal layer structure on the gate structure in an embodiment of the present application;

[0041] The symbols are explained as follows:

[0042] 1, substrate; 21, first epitaxial layer; 22, second epitaxial layer; 23, third epitaxial layer; 24, fourth epitaxial layer; 210, 220, 230, 240, upper region of epitaxial layer; 211, 221, 231, 241, lower region of epitaxial layer; 31, 32, 33, column structure; 3, column region; 4, gate oxide layer; 5, polysilicon layer; 6, body region; 7, source region; 8, insulating dielectric layer; 9, photoresist; 10, front metal layer. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0044] It should also be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] It will also be understood that, when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component or intervening components can be present. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intervening components present.

[0046] It will also be understood that the terms "upper", "lower", "left", "right", "front", "rear", "bottom", "intermediate", "middle", "top", and the like in reference to an element of a structure are used herein to indicate the orientation of the element in the drawings as they appear grasping the present application and simplifying the description thereof, and are not meant in any way as indicating or implying that a particular orientation of the device or element is required to practice or use the present application in its preferred form, and therefore such elements should not be limited to any particular orientation unless specified herein.

[0047] These terms are used only to distinguish one element from another. For example, a first element can be termed an "upper" element, and a second element can be termed an "upper" element, in accordance with the relative orientation of these elements, without departing from the scope of the present disclosure.

[0048] It is further understood that the terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] In an embodiment, a method for manufacturing a super-junction type semiconductor device is provided, as shown in FIG. 1, comprising the following steps: Figure 1 As shown in FIG. 1, comprising the following steps:

[0051] S101: providing a substrate of a first semiconductor type.

[0052] As shown in FIG. 1, comprising the following steps: Figure 2 As shown in FIG. 1, comprising the following steps:

[0053] S102: At least two epitaxial layers are sequentially formed on the surface of the substrate, and the conductor type of each epitaxial layer is a first semiconductor type; during the sequential growth of each epitaxial layer, deep-level impurity ions are injected into the upper region of each epitaxial layer to form deep-level recombination centers; so that each deep-level recombination center and each lower region of the epitaxial layer are intermittently gradient distributed.

[0054] For example, such as Figure 3 As shown, a first epitaxial layer 21 is first grown on the surface of substrate 1. Then, deep-level impurity ions, such as gold ions (Au) or platinum ions (Pt), are implanted into the surface of the first epitaxial layer 21, dividing the first epitaxial layer 21 into two regions: an upper region implanted with deep-level impurity ions (i.e., deep-level recombination centers) and a lower region without implanted deep-level impurity ions. Then, a second epitaxial layer is grown on the surface of the first epitaxial layer 21, and the above process is repeated to form the deep-level recombination centers and lower region of the second epitaxial layer; and so on. When N epitaxial layers are formed, N deep-level recombination centers and N lower regions can be obtained, resulting in an intermittent gradient distribution of the epitaxial layers of each deep-level recombination center and lower region. For example, when N=4, i.e., four epitaxial layers are formed, the resulting epitaxial layers of the four deep-level recombination centers and lower regions exhibit an intermittent gradient distribution. Figure 5 As shown.

[0055] S103: Ion of a second conductor type is injected into the upper region of each of the epitaxial layers to obtain a columnar structure, and each columnar structure is used to form a columnar region by longitudinal connection;

[0056] The process of obtaining the columnar structure includes:

[0057] like Figure 4 As shown, after forming an upper region (210, 220) and a lower region (211, 221) in each epitaxial layer, second conductor type ions are injected into the upper region of each epitaxial layer using photoresist 9 as a barrier to obtain a columnar structure (P-pillar) 31.

[0058] For example, when forming four epitaxial layers, according to the above steps, second conductor type ions are sequentially implanted into the upper regions (220, 230, 240) of the three epitaxial layers in the order of the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24, resulting in columnar structures (31, 32, 33) distributed in each upper region, such as... Figure 5 As shown.

[0059] In one example, the various columnar structures used to form a columnar region through longitudinal connection include:

[0060] The columnar structures are longitudinally connected to form the column region through a high-temperature annealing process, so as to repair defects in some deep-level composite centers distributed within the column region.

[0061] For example, using a high-temperature annealing process, for Figure 5 The shown columnar structures (31, 32, 33) are processed to connect them longitudinally, forming column region 3, as shown. Figure 6 As shown. Furthermore, the high-temperature annealing process is equivalent to repairing the defect region (i.e., some deep-level recombination centers near the columnar structure) distributed near the ions of the second conductor type.

[0062] For example, when the substrate is N-type, the corresponding first semiconductor type is N-type and the second semiconductor type is P-type, that is, multiple N-type epitaxial layers are formed in step S102, and P-type pillar regions are formed in step S103. Alternatively, when the substrate is P-type, the corresponding first semiconductor type is P-type and the second semiconductor type is N-type, that is, multiple P-type epitaxial layers are formed in step S102, and N-type pillar regions are formed in step S103.

[0063] S104: A gate structure is formed on the top epitaxial layer;

[0064] In one example, forming the gate structure on the topmost epitaxial layer includes:

[0065] A gate oxide layer is formed on the topmost epitaxial layer, and a polysilicon layer is formed on the upper surface of the gate oxide layer to obtain the gate structure.

[0066] For example, when four epitaxial layers (21, 22, 23, 24) are formed on substrate 1, the fourth epitaxial layer 24 is the top epitaxial layer. A gate oxide layer 4 is grown on the surface of the fourth epitaxial layer 24, and polysilicon is deposited on the upper surface of the gate oxide layer 4 to form a polysilicon layer 5, thereby obtaining the gate structure, as shown below. Figure 7 As shown.

[0067] S105: Injecting ions of a second conductor type into the surface of the topmost epitaxial layer to form a bulk region.

[0068] For example, when four epitaxial layers (21, 22, 23, 24) are formed on substrate 1, the fourth epitaxial layer 24 is the top epitaxial layer. Ionizing of a second conductor type is performed on the surface of the fourth epitaxial layer 24 to obtain the bulk region 6, as shown below. Figure 8 As shown.

[0069] In one example, a deep level recombination center is disposed within the body region in the top epitaxial layer. Since multiple epitaxial layers are grown in step S102, resulting in an overlapping distribution of deep level recombination centers and the lower epitaxial layer, after completing steps S103 to S104, a portion of the deep level recombination centers in the top epitaxial layer are introduced into the body region by performing ion implantation of a second conductor type on the surface of the epitaxial layer in a region without a gate structure.

[0070] S106: Implant ions of a first semiconductor type into the surface of the top epitaxial layer to form a source region located within the bulk region.

[0071] After forming the bulk region, photolithography is performed on the surface of the top epitaxial layer using a source region mask. Ion implantation of a first semiconductor type is then performed in the pre-lithographic region to obtain the source region 7 located within the bulk region, as shown below. Figure 8 As shown.

[0072] S107: A front metal layer is formed on the gate structure; and a back metal layer is formed.

[0073] The fabrication of the front-side metal layer on the gate structure includes:

[0074] An insulating dielectric layer 8 is deposited on the polysilicon layer of the gate structure and on both sides of the gate oxide layer;

[0075] Metal is deposited on the insulating dielectric layer and the remaining epitaxial layer to form the front metal layer 10, such as... Figure 9 As shown.

[0076] The fabrication of the back metal layer includes:

[0077] Metal is deposited on the lower surface of the substrate to form a back metal layer.

[0078] The method for fabricating the superjunction semiconductor device in this embodiment has the following advantages:

[0079] (1) In the process of manufacturing semiconductor devices, from the epitaxial layer growth stage, by growing multiple epitaxial layers, the recombination centers of deep-level impurity ions injected into each epitaxial layer and the remaining epitaxial growth (i.e., the lower region) form an intermittent gradient distribution, thereby producing a semiconductor device with multiple deep-level recombination centers introduced in the bulk, reducing the lifetime and concentration of minority carriers, and reducing the reverse recovery time of the bulk diode in the semiconductor device without affecting the breakdown voltage and other parameter performance of the bulk diode, thus improving the reverse recovery capability of the bulk diode in the semiconductor device.

[0080] (2) It takes into account the manufacturing process of traditional superjunction MOSFET devices. After metallization, the remaining back-side technology process can be completed directly without increasing the additional manufacturing cost, which can effectively shorten the device manufacturing cost cycle.

[0081] (3) No additional secondary outsourcing is required to directly prepare superjunction semiconductor devices that meet performance requirements. This effectively saves time and manufacturing costs compared to existing technologies.

[0082] In other embodiments, after forming the body region in step S105 and before step S106, the method for fabricating the superjunction semiconductor device further includes:

[0083] The high-temperature annealing process is used again to redistribute ions within the bulk region, thereby controlling the defect distribution of deep-level recombination centers within the bulk region.

[0084] The control of defect distribution in deep-level recombination centers is mainly achieved through two high-temperature annealing processes for defect repair. The first defect repair is carried out in step S103, when the various columnar structures are longitudinally connected to form column regions through the high-temperature annealing process. During this process, defect regions near the second conductor type ions are repaired, while defect regions without second conductor type ions are not repaired. The second defect repair is carried out in this embodiment by using the high-temperature annealing process again to redistribute the lightly doped second conductor type ions in the bulk region. At the same time, the charge balance of the deep-level recombination centers distributed in the epitaxial layer is also redistributed and repaired.

[0085] Therefore, the redistribution process of lightly doped second conductor ions in the aforementioned bulk region effectively controls the defect distribution of deep recombination centers in the bulk region; and the high-temperature thermal propulsion process repairs the leakage channel, ensuring that the device performance is not affected, thereby reducing leakage current when the device is reverse biased.

[0086] In one embodiment, a superjunction semiconductor device is provided, such as Figure 9 As shown, the superjunction semiconductor device includes:

[0087] Substrate 1 of the first semiconductor type;

[0088] At least two epitaxial layers are disposed on the surface of the substrate 1. Figure 9 The image shows four epitaxial layers, as shown below. Figure 5As shown), the conductor type of each epitaxial layer (21, 22, 23, 24) is a first semiconductor type; each epitaxial layer includes an upper region (210, 220, 230, 240) and a lower region (211, 221, 231, 241), and deep-level impurity ions are implanted in each of the upper regions (210, 220, 230, 240) to form deep-level recombination centers; and each of the deep-level recombination centers and the lower region of each epitaxial layer are intermittently gradient distributed;

[0089] The column region 3 is formed by longitudinally connecting columnar structures set in the lower regions (211, 221, 231, 241) of each of the epitaxial layers; a body region 6 is set above the column region 3, and a source region 7 is set inside the body region 6.

[0090] A gate structure is disposed on the topmost epitaxial layer, and a front metal layer 10 is disposed on the gate structure; a back metal layer is disposed on the lower surface of the substrate. Figure 9 (Not shown in the image).

[0091] In one example, the body region 6 is distributed in part of the deep-level recombination centers and part of the lower region in the topmost epitaxial layer. For example, Figure 9 In the semiconductor device, the deep-level recombination centers and the lower region 241 of the fourth epitaxial layer 24 are distributed in the body region 6.

[0092] In one example, the gate structure includes:

[0093] Gate oxide layer 4, wherein the gate oxide layer 4 is disposed on the surface of the topmost epitaxial layer;

[0094] A polysilicon layer 5 is disposed on the upper surface of the gate oxide layer 4.

[0095] In one example, an insulating dielectric layer 6 is disposed on the upper surface of the polysilicon layer 5 and on both sides of the gate oxide layer 4.

[0096] In one example, the front metal layer 10 is disposed on the upper surface of the insulating dielectric layer 6 and the upper surfaces of the body region 6 and the source region 7.

[0097] It should be noted that the number of epitaxial layers in the above-mentioned superjunction semiconductor device can be set according to specific needs. It is not limited to four layers. Two, three, or five layers can be set, as long as it can meet the requirements of forming deep-level recombination centers and intermittent gradient distribution between the lower regions of each epitaxial layer.

[0098] The superjunction semiconductor device of this embodiment, by introducing multiple deep-level recombination centers in the semiconductor device, reduces the lifetime and concentration of minority carriers. Without affecting the breakdown voltage and other performance parameters of the body diode, it reduces the reverse recovery time of the body diode in the semiconductor device, thereby improving the reverse recovery capability of the body diode in the semiconductor device.

[0099] Furthermore, since the superjunction semiconductor device introduces corresponding deep-level impurity vacancy defects (deep-level recombination centers) during the epitaxial layer growth process, combined with the pillar structure of the superjunction semiconductor device and the alternating distribution of epitaxial layers with deep-level recombination centers within the effective die of the device, these alternating P / N pillars have the same potential, and no breakdown phenomenon occurs between the P / N pillars. When the superjunction semiconductor device is in operation and switching, the hole defects in the epitaxial layer can effectively reduce and suppress the P / N junction depletion rate, thereby improving the gate oscillation problem of the semiconductor device structure.

[0100] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a superjunction semiconductor device, characterized in that, Includes the following steps: Provide a substrate of the first semiconductor type; At least two epitaxial layers are sequentially formed on the surface of the substrate, and the conductor type of each epitaxial layer is a first semiconductor type; during the sequential growth of each epitaxial layer, deep-level impurity ions are injected into the upper region of each epitaxial layer to form deep-level recombination centers; so that each deep-level recombination center and each lower region of the epitaxial layer are intermittently gradient distributed; Ions of a second conductor type are injected into the upper region of each of the epitaxial layers to obtain columnar structures, and each columnar structure is used to form a columnar region by longitudinal connection; A gate structure is formed on the top epitaxial layer; ions of a second conductor type are implanted into the surface of the top epitaxial layer to form a body region; ions of a first semiconductor type are implanted into the surface of the top epitaxial layer to form a source region located within the body region; A front-side metal layer is fabricated on the gate structure; And the fabrication of the back metal layer; The various columnar structures used to form columnar zones through longitudinal connection include: The columnar structures are longitudinally connected to form the column region through a high-temperature annealing process, so as to repair defects in some deep-level composite centers distributed within the column region.

2. The method for fabricating a superjunction semiconductor device as described in claim 1, characterized in that, After the body region is formed, the following is also included: The high-temperature annealing process is used again to redistribute ions within the bulk region, thereby controlling the defect distribution of deep-level recombination centers within the bulk region.

3. The method for fabricating a superjunction semiconductor device as described in any one of claims 1 to 2, characterized in that, The body region contains a deep-level recombination center located in the topmost epitaxial layer.

4. The method for fabricating a superjunction semiconductor device as described in claim 1, characterized in that, The formation of the gate structure on the topmost epitaxial layer includes: A gate oxide layer is formed on the topmost epitaxial layer, and a polysilicon layer is formed on the upper surface of the gate oxide layer to obtain the gate structure.

5. A superjunction semiconductor device, characterized in that, The superjunction semiconductor device includes: Substrate of the first semiconductor type; At least two epitaxial layers are disposed on the surface of the substrate, and the conductor type of each epitaxial layer is a first semiconductor type; each epitaxial layer includes an upper region and a lower region, and deep-level impurity ions are implanted in each upper region to form deep-level recombination centers; and each deep-level recombination center and the lower region of each epitaxial layer are intermittently gradient distributed. The column region is formed by longitudinally connecting columnar structures disposed in the upper regions of each of the epitaxial layers; a body region is disposed above the column region, and a source region is disposed within the body region; A gate structure is disposed on the top epitaxial layer, and a front metal layer is disposed on the gate structure; a back metal layer is disposed on the lower surface of the substrate.

6. The superjunction semiconductor device as described in claim 5, characterized in that, The body region is distributed in part of the deep-level recombination centers and part of the lower region in the topmost epitaxial layer.

7. The superjunction semiconductor device as described in claim 5, characterized in that, The gate structure includes: A gate oxide layer, wherein the gate oxide layer is disposed on the surface of the topmost epitaxial layer; A polysilicon layer is disposed on the upper surface of the gate oxide layer.

8. The superjunction semiconductor device as described in claim 7, characterized in that, An insulating dielectric layer is provided on the upper surface of the polysilicon layer and on both sides of the gate oxide layer.

9. The superjunction semiconductor device as described in claim 8, characterized in that, The front metal layer is disposed on the upper surface of the insulating dielectric layer and on the upper surface of the body region and the source region.

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