semiconductor structure

Abstract

This invention discloses a semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a protective layer. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The protective layer is disposed on the first conductive layer and the dielectric layer. The protective layer includes a first upper surface and a second upper surface. The first upper surface is located above the top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. The height of the first upper surface is higher than the height of the second upper surface. The height of the second upper surface is lower than or equal to the height of the lower surface of the first conductive layer located between the top surface of the dielectric layer and the first conductive layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a protective layer. Background Technology

[0002] In some semiconductor structures, a protective layer is formed on top of the conductive layer. However, during subsequent high-temperature fabrication processes, the conductive layer expands due to heat, generating stress on the protective layer, which often leads to cracks at the corners of the protective layer. Therefore, reducing the stress on the protective layer is a current ongoing research goal. Summary of the Invention

[0003] The present invention provides a semiconductor structure that can effectively reduce the stress applied to the protective layer.

[0004] This invention proposes a semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a protective layer. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The protective layer is disposed on the first conductive layer and the dielectric layer. The protective layer includes a first upper surface and a second upper surface. The first upper surface is located above the top surface of the first conductive layer. The second upper surface is located to one side of the first conductive layer. The height of the first upper surface is higher than the height of the second upper surface. The height of the second upper surface is lower than or equal to the height of the lower surface of the first conductive layer, which is located between the top surface of the dielectric layer and the first conductive layer.

[0005] According to one embodiment of the present invention, in the above-described semiconductor structure, the protective layer may include multiple insulating layers. The uppermost insulating layer may be a nitride layer. The uppermost insulating layer may have a first upper surface and a second upper surface.

[0006] According to one embodiment of the present invention, in the above-described semiconductor structure, an opening may be provided on one side of the first conductive layer. A protective layer may be located on the sidewall and bottom surface of the opening.

[0007] According to one embodiment of the present invention, in the above-described semiconductor structure, the opening may extend into the dielectric layer.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure, the angle between the sidewall of the opening and the bottom surface of the opening can be greater than 95 degrees and less than or equal to 120 degrees.

[0009] According to an embodiment of the present invention, in the above-described semiconductor structure, the angle between the sidewall of the opening and the bottom surface of the opening can be greater than or equal to 95.5 degrees and less than or equal to 110 degrees.

[0010] According to an embodiment of the present invention, in the above-described semiconductor structure, the protective layer may include a first insulating layer and a second insulating layer. The second insulating layer is disposed on the first insulating layer. The second insulating layer may have a first upper surface and a second upper surface.

[0011] According to an embodiment of the present invention, in the above semiconductor structure, the angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer can be greater than 95 degrees and less than or equal to 120 degrees.

[0012] According to an embodiment of the present invention, in the above semiconductor structure, the included angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer can be greater than or equal to 95.5 degrees and less than or equal to 110 degrees.

[0013] According to one embodiment of the present invention, in the above-described semiconductor structure, the dielectric layer may have rounded corners at a position adjacent to the bottom of the opening.

[0014] According to one embodiment of the present invention, in the above-described semiconductor structure, the protective layer may further include a connection surface. The connection surface is located between the first upper surface and the second upper surface, and connects the first upper surface and the second upper surface.

[0015] According to one embodiment of the present invention, in the above-described semiconductor structure, a portion of the protective layer may be located in the dielectric layer.

[0016] According to an embodiment of the present invention, in the above semiconductor structure, the first conductive layer may be a single-layer structure.

[0017] According to an embodiment of the present invention, in the above-described semiconductor structure, the first conductive layer may be a multilayer structure.

[0018] According to one embodiment of the present invention, in the above-described semiconductor structure, the first conductive layer may include a barrier layer and a conductor layer. The conductor layer is disposed on the barrier layer.

[0019] According to one embodiment of the present invention, the semiconductor structure described above may further include a second conductive layer. The second conductive layer is located between the dielectric layer and the substrate.

[0020] According to an embodiment of the present invention, in the above-described semiconductor structure, the first conductive layer and the second conductive layer can be separated from each other through a dielectric layer.

[0021] According to an embodiment of the present invention, in the above-described semiconductor structure, the first conductive layer may be electrically connected to the second conductive layer.

[0022] According to one embodiment of the present invention, in the above-described semiconductor structure, the protective layer may expose a portion of the first conductive layer.

[0023] According to one embodiment of the present invention, the semiconductor structure described above may further include a capping layer. The capping layer is located between the dielectric layer and the second conductive layer.

[0024] Based on the above, in the semiconductor structure proposed in this invention, since the height of the second upper surface of the protective layer is lower than or equal to the height of the lower surface of the first conductive layer located between the top surface of the dielectric layer and the first conductive layer, the stress applied to the protective layer can be effectively reduced. Therefore, cracks in the protective layer can be prevented, thereby improving the electrical performance of the semiconductor device.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figure 1 These are cross-sectional views of semiconductor structures according to some embodiments of the present invention;

[0027] Figure 2 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention;

[0028] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention. Detailed Implementation

[0029] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same components will be designated with the same symbols in the following description.

[0030] Figure 1 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 2 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention. Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention.

[0031] Please refer to Figure 1 The semiconductor structure 10 includes a substrate 100, a dielectric layer 102, a conductive layer 104, and a protective layer 106. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, in... Figure 1 Although not shown, the substrate 100 may have the required components such as doped regions and / or isolation structures, and the substrate 100 may have the required components such as semiconductor elements (such as active (active) elements and / or passive (passive) elements), dielectric layers and interconnect structures, which are omitted here.

[0032] A dielectric layer 102 is disposed on the substrate 100. The dielectric layer 102 may be an inter-metal dielectric (IMD) layer. The material of the dielectric layer 102 is, for example, an oxide, such as silicon oxide.

[0033] A conductive layer 104 is disposed on the dielectric layer 102. The conductive layer 104 may be a single-layer structure or a multi-layer structure. In some embodiments, the conductive layer 104 may be the top metal layer in the semiconductor structure 10. In this embodiment, the conductive layer 104 is exemplified by a multi-layer structure. For example, the conductive layer 104 may include a barrier layer 108 and a conductor layer 110. The material of the barrier layer 108 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The conductor layer 110 is disposed on the barrier layer 108. The conductor layer 110 is, for example, a metal layer. In this embodiment, the conductor layer 110 may be the top metal layer in the semiconductor structure 10. The material of the conductor layer 110 is, for example, aluminum.

[0034] In some embodiments, the semiconductor structure 10 may include multiple conductive layers 104, but the present invention is not limited thereto. Any semiconductor structure 10 that includes more than one conductive layer 104 is within the scope of the present invention. In this embodiment, the semiconductor structure 10 may include conductive layers 104a and 104b that are adjacent to each other. Conductive layer 104a may be a conductive line, and conductive layer 104b may be a pad.

[0035] A protective layer 106 is disposed on the conductive layer 104 and the dielectric layer 102. Furthermore, a portion of the protective layer 106 may be located within the dielectric layer 102. The protective layer 106 includes an upper surface S1 and an upper surface S2. The upper surface S1 is located above the top surface TS1 of the conductive layer 104. The upper surface S2 is located on one side of the conductive layer 104. The height H1 of the upper surface S1 is higher than the height H2 of the upper surface S2. The height H2 of the upper surface S2 is lower than or equal to the height H3 of the lower surface LS of the conductive layer 104 located between the top surface TS2 of the dielectric layer 102 and the conductive layer 104, thereby effectively reducing the stress applied to the protective layer 106. Additionally, the protective layer 106 may also include a connecting surface S3. The connecting surface S3 is located between and connects the upper surfaces S1 and S2.

[0036] Furthermore, the protective layer 106 may include multiple insulating layers 112, but the present invention is not limited thereto. The protective layer 106 is within the scope of the present invention as long as it includes more than one insulating layer 112. For example, the protective layer 106 may include insulating layers 112a and 112b. Insulating layer 112a may be an oxide layer. The material of insulating layer 112a is, for example, silicon oxide. Insulating layer 112b is disposed on insulating layer 112a. The uppermost insulating layer 112 (e.g., insulating layer 112b) may have an upper surface S1 and an upper surface S2. The uppermost insulating layer 112 (e.g., insulating layer 112b) may be a nitride layer. The material of insulating layer 112 is, for example, silicon nitride or silicon oxynitride.

[0037] Furthermore, an opening OP may be provided on one side of the conductive layer 104. The opening OP may be located between two adjacent conductive layers 104 (e.g., conductive layer 104a and conductive layer 104b). The protective layer 106 may be located on the sidewall and bottom surface of the opening OP. The opening OP may extend into the dielectric layer 102. In some embodiments, the angle θ1 between the sidewall and the bottom surface of the opening OP may be greater than 95 degrees and less than or equal to 120 degrees. In some embodiments, the angle θ1 between the sidewall and the bottom surface of the opening OP may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees. By setting the angle θ1 between the sidewall and the bottom surface of the opening OP within the above range, the dielectric layer 102 may have a rounded corner R near the bottom of the opening OP, thereby further reducing the stress applied to the protective layer 106. In some embodiments, the angle θ2 between the sidewall and the bottom surface of the insulating layer 112b may be greater than 95 degrees and less than or equal to 120 degrees. In some embodiments, the included angle θ2 between the sidewall of the insulating layer 112b and the bottom surface of the insulating layer 112b may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees.

[0038] The semiconductor structure 10 may further include a conductive layer 114. The conductive layer 114 is located between the dielectric layer 102 and the substrate 100. The material of the conductive layer 114 is, for example, copper. Additionally, the semiconductor structure 10 may include multiple conductive layers 114, but this is not a limitation of the invention. The semiconductor structure 10 is within the scope of this invention as long as it includes more than one conductive layer 114. For example, the semiconductor structure 10 may include conductive layers 114a and 114b. Conductive layers 104 may overlap with corresponding conductive layers 114 in a direction D perpendicular to the substrate 100. For example, conductive layer 104a may overlap with conductive layer 114a in a direction D perpendicular to the substrate 100. Conductive layer 104a (e.g., a wire) and conductive layer 114a may be separated from each other by the dielectric layer 102. A protective layer 106 may cover conductive layer 104a (e.g., a wire). Conductive layer 104b may overlap with conductive layer 114b in a direction D perpendicular to the substrate 100. The conductive layer 104b (e.g., a pad) may be electrically connected to the conductive layer 114b. The protective layer 106 may expose a portion of the conductive layer 104b (e.g., a pad).

[0039] The semiconductor structure 10 may further include a dielectric layer 116. The dielectric layer 116 is located between the dielectric layer 102 and the substrate 100. A conductive layer 114 may be located within the dielectric layer 116. Furthermore, the dielectric layer 116 may be located between conductive layers 114a and 114b. The dielectric layer 116 may be an intermetallic dielectric layer. The dielectric layer 116 may be a single-layer structure or a multilayer structure. The material of the dielectric layer 116 is, for example, an oxide (e.g., silicon oxide), a nitride (e.g., silicon oxynitride, silicon carbide nitride, or silicon nitride), or a combination thereof.

[0040] The semiconductor structure 1 may further include a capping layer 118. In this embodiment, the capping layer 118 may be located between the dielectric layer 102 and the conductive layer 114, and between the dielectric layer 102 and the dielectric layer 116. The material of the capping layer 118 is, for example, a nitride (e.g., silicon nitride).

[0041] In this embodiment, the semiconductor structure 10 is exemplified by having conductive layers 104a (e.g., wires) and conductive layers 104b (e.g., pads) located on both sides of the opening OP, but the present invention is not limited thereto. In other embodiments, such as Figure 2 As shown, the semiconductor structure 10 may include two conductive layers 104a (e.g., wires) located on either side of the opening OP. In other embodiments, such as Figure 3 As shown, the semiconductor structure 10 may include two conductive layers 104b (e.g., pads) located on both sides of the opening OP.

[0042] As can be seen from the above embodiments, in the semiconductor structure 10, since the height H2 of the upper surface S2 of the protective layer 106 is lower than or equal to the height H3 of the lower surface LS of the conductive layer 104 located between the top surface TS2 of the dielectric layer 102 and the conductive layer 104, the stress applied to the protective layer 106 can be effectively reduced. Therefore, cracks in the protective layer 106 can be prevented, thereby improving the electrical performance of the semiconductor device.

[0043] In summary, the semiconductor structure of the above embodiments can effectively reduce the stress applied to the protective layer, thereby preventing cracks in the protective layer and improving the electrical performance of the semiconductor device.

[0044] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A semiconductor structure, comprising: Base; A dielectric layer is disposed on the substrate; A first conductive layer is disposed on the dielectric layer; as well as A protective layer is disposed on the first conductive layer and the dielectric layer, wherein The protective layer includes a first upper surface and a second upper surface. The first upper surface is located above the top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. The height of the first upper surface is higher than the height of the second upper surface, and The height of the second upper surface is lower than or equal to the height of the lower surface of the first conductive layer located between the top surface of the dielectric layer and the first conductive layer.

2. The semiconductor structure of claim 1, wherein the protective layer comprises a plurality of insulating layers, the uppermost insulating layer being a nitride layer, and the uppermost insulating layer having a first upper surface and a second upper surface.

3. The semiconductor structure of claim 1, wherein an opening is provided on one side of the first conductive layer, and the protective layer is located on the sidewall and bottom surface of the opening.

4. The semiconductor structure of claim 3, wherein the opening extends into the dielectric layer.

5. The semiconductor structure of claim 3, wherein the angle between the sidewall of the opening and the bottom surface of the opening is greater than 95 degrees and less than or equal to 120 degrees.

6. The semiconductor structure of claim 3, wherein the angle between the sidewall of the opening and the bottom surface of the opening is greater than or equal to 95.5 degrees and less than or equal to 110 degrees.

7. The semiconductor structure of claim 3, wherein the protective layer comprises: First insulating layer; as well as A second insulating layer is disposed on the first insulating layer, wherein the second insulating layer has the first upper surface and the second upper surface.

8. The semiconductor structure of claim 7, wherein the angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer is greater than 95 degrees and less than or equal to 120 degrees.

9. The semiconductor structure of claim 7, wherein the angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer is greater than or equal to 95.5 degrees and less than or equal to 110 degrees.

10. The semiconductor structure of claim 7, wherein the dielectric layer has rounded corners at a position adjacent to the bottom of the opening.

11. The semiconductor structure of claim 1, wherein the protective layer further comprises: The connecting surface is located between the first upper surface and the second upper surface, and connects the first upper surface and the second upper surface.

12. The semiconductor structure of claim 1, wherein a portion of the protective layer is located within the dielectric layer.

13. The semiconductor structure of claim 1, wherein the first conductive layer comprises a single-layer structure.

14. The semiconductor structure of claim 1, wherein the first conductive layer comprises a multilayer structure.

15. The semiconductor structure of claim 1, wherein the first conductive layer comprises: Barrier layer; as well as A conductor layer is disposed on the barrier layer.

16. The semiconductor structure of claim 1, further comprising: The second conductive layer is located between the dielectric layer and the substrate.

17. The semiconductor structure of claim 16, wherein the first conductive layer and the second conductive layer are separated from each other through the dielectric layer.

18. The semiconductor structure of claim 16, wherein the first conductive layer is electrically connected to the second conductive layer.

19. The semiconductor structure of claim 18, wherein the protective layer exposes a portion of the first conductive layer.

20. The semiconductor structure of claim 16, further comprising: A top cover layer is located between the dielectric layer and the second conductive layer.

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