RF Switching Transistor and its Manufacturing Method

Abstract

This invention provides a radio frequency switch, including a substrate on which multiple semiconductor device structures are sequentially formed. Each of the semiconductor structures includes: a gate structure and source and drain regions formed on both sides of the gate structure; an etch stop layer covering the gate structure; a first interlayer dielectric layer formed on the etch stop layer; first and second metal layers for leading out the source and drain regions, respectively; a first dielectric barrier layer formed on the first and second metal layers and the first interlayer dielectric layer; and a second interlayer dielectric layer formed on the first dielectric barrier layer. The first and second interlayer dielectric layers are both made of low dielectric constant materials. A first groove is formed on the second interlayer dielectric layer and the first dielectric barrier layer below it. The first groove is filled with a third metal layer, which is electrically connected to the first and second metal layers, respectively. This invention requires only one photolithography layer, significantly reducing costs; and it does not significantly affect the harmonic performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radio frequency switch and its manufacturing method. Background Technology

[0002] Due to the presence of parallel capacitance in the buried oxide layer, SOI (silicon-on-insulator) substrates result in uneven voltage distribution between transistor stages. Please see Figure 1 When the device is off, it has to withstand the high voltage at the antenna end (approximately equal to the input end). At this time, the tube closest to the antenna withstands the highest voltage. This uneven voltage distribution will cause the RF switch to be unable to withstand high power operating conditions.

[0003] Please see Figure 2 In the existing technology, capacitors of different sizes are connected in parallel on each stage of transistors to make the equivalent capacitance of each stage equal and the voltage division uniform. However, the parallel capacitors use a metal MOM (Metal-Oxide-Metal sandwich structure) or MIM (Metal-Insulator-Metal sandwich structure), which requires an additional 2 to 3 photolithography processes, resulting in high costs.

[0004] To solve the above problems, a new type of radio frequency switch and its manufacturing method are needed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a radio frequency switch transistor and its manufacturing method, which solves the problem that in the prior art, when the device is turned off, it has to withstand a high voltage at the antenna end (approximately equal to the input end), at which time the transistor closest to the antenna bears the largest voltage. This uneven voltage distribution will cause the radio frequency switch to be unable to withstand high power operating conditions. By connecting capacitors of different sizes in parallel on each stage transistor, the equivalent capacitance of each stage is made equal, and the voltage distribution is uniform. However, the parallel capacitors use a metal MOM (Metal-Oxide-Metal, a sandwich structure composed of metal-oxide-metal) or MIM (a sandwich structure composed of three thin films of metal, insulator, and metal), which requires an additional 2 to 3 layers of photolithography process, resulting in high cost.

[0006] To achieve the above and other related objectives, the present invention provides a radio frequency switch transistor, comprising: A substrate, on which multiple semiconductor device structures are sequentially formed; wherein, The semiconductor structures described herein all include: Gate structure and source and drain regions formed on both sides of the gate structure; Etching stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to draw out the source region and the drain region, respectively; A first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the first dielectric barrier layer. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer dielectric and the first dielectric barrier layer below it. The first groove is filled with a third metal layer, which is electrically connected to the first and second metal layers respectively. A second groove is formed on the second interlayer dielectric layer, and a high dielectric constant material layer is filled in the second groove. A third dielectric barrier layer is formed on the third metal layer, the second interlayer dielectric layer, and the high dielectric constant material layer. The remaining semiconductor structures all include: Gate structure and source and drain regions formed on both sides of the gate structure; Etching stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to draw out the source region and the drain region, respectively; A first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the first dielectric barrier layer. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer dielectric and the first dielectric barrier layer below it. The first groove is filled with a third metal layer, which is electrically connected to the first and second metal layers respectively. A third dielectric barrier layer is formed on the third metal layer and the second interlayer dielectric layer.

[0007] Preferably, the substrate comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0008] Preferably, the material of the dielectric layer between the first and second layers is silicon dioxide.

[0009] Preferably, the materials of the first and second metal layers are tungsten.

[0010] Preferably, the material of the third metal layer is copper.

[0011] Preferably, the material of the etching stop layer is silicon nitride.

[0012] Preferably, the material of the first and third dielectric barrier layers is doped silicon carbide.

[0013] Preferably, the material of the high dielectric constant material layer includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

[0014] Preferably, n semiconductor device structures are sequentially formed on the substrate, and an antenna end structure is also formed on one side of each semiconductor structure. Some of the semiconductor structures are the first two or three semiconductor structures close to the antenna end structure, where n is an integer greater than 3.

[0015] The present invention also provides a method for manufacturing a radio frequency switch transistor, comprising: Step 1: Provide a substrate on which a plurality of semiconductor device structures are sequentially formed; wherein each of the semiconductor structures includes: Gate structure and source and drain regions formed on both sides of the gate structure; Etching stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to bring out the source region and the drain region, respectively; a first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer; and a second interlayer dielectric layer is formed on the first dielectric barrier layer. Step 2: Form a photoresist layer on the second interlayer dielectric layer, and use photolithography to open the photoresist layer on the semiconductor device structure, so that the second interlayer dielectric layer to be etched underneath is exposed. Step 3: Etch the exposed second interlayer dielectric layer and the first interlayer dielectric layer below it to form a first groove, thereby exposing the first and second metal layers, and then remove the remaining photoresist layer; Step 4: A third metal layer is formed to fill the first groove by deposition and grinding, and then a second dielectric barrier layer is formed on the third metal layer and the second interlayer dielectric layer. Step 5: Etch the second dielectric barrier layer between the third metal layers of the semiconductor structure and the second interlayer dielectric layer below it to form a second groove. Form a high dielectric constant material layer on the second groove. Then, grind the high dielectric constant material layer and the second dielectric barrier layer below it until the third metal layer is exposed. Then, form a third dielectric barrier layer on the third metal layer, the high dielectric constant material layer, and the second interlayer dielectric layer. Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0016] Preferably, n semiconductor device structures are sequentially formed on the substrate in step one, and an antenna end structure is also formed on one side of each semiconductor structure. Some of the semiconductor structures are the first two or three semiconductor structures close to the antenna end structure, where n is an integer greater than 3.

[0017] Preferably, the material of the etching stop layer in step one is silicon nitride.

[0018] Preferably, the materials of the first and second interlayer dielectric layers in step one are both silicon dioxide.

[0019] Preferably, the materials of the first and second metal layers in step one are both tungsten.

[0020] Preferably, the materials of the first dielectric barrier layer in step one, the second dielectric barrier layer in step four, and the third dielectric barrier layer in step five are all doped silicon carbide.

[0021] Preferably, the material of the third metal layer in step four is copper.

[0022] Preferably, the material of the high dielectric constant material layer in step five includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

[0023] As described above, the radio frequency switch and its manufacturing method of the present invention have the following beneficial effects: Compared to traditional methods of adding MIM structures (sandwich structures composed of three thin films: metal, insulator, and metal), this invention only requires one layer of photolithography, greatly reducing costs; and by filling the first 2-3 dielectric layers near the antenna end with a high dielectric constant material layer, it will not have a significant impact on the harmonic performance of the device. Attached Figure Description

[0024] Figure 1 The diagram shown is a schematic of a radio frequency switch transistor in the prior art. Figure 2 The diagram shows an existing technology involving the addition of a parallel capacitor to adjust the equivalent capacitance. Figure 3 The diagram shows the substrate and the structure thereon of the present invention. Figure 4 The diagram shown illustrates the formation of the first groove according to the present invention. Figure 5 The diagram shown illustrates the formation of the third metal layer according to the present invention. Figure 6 The diagram shown illustrates the formation of the second dielectric barrier layer according to the present invention. Figure 7 The diagram shown illustrates the formation of the second groove according to the present invention. Figure 8 The diagram shown is a schematic diagram of the deposited high dielectric constant material layer of the present invention. Figure 9 The diagram shows the grinding of the high dielectric constant material layer to the third metal layer according to the present invention. Figure 10 The diagram shown illustrates the formation of the third dielectric barrier layer according to the present invention. Figure 11 The diagram shows a parallel capacitor formed on multiple semiconductor structures according to the present invention. Figure 12 The diagram shows a comparison between the transistor voltage divider of the present invention and the transistor voltage divider of the prior art. Figure 13 The diagram shown is a schematic representation of the process flow of this invention. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] Please see Figure 11 The present invention provides a radio frequency switch transistor, comprising: Substrate 101, on which multiple semiconductor device structures are sequentially formed; In embodiments of the present invention, substrate 101 includes a bulk semiconductor substrate 101 or a silicon-on-insulator (SOI) substrate 101. The SOI substrate 101 includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate 101. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates 101 that may be used include multilayer substrates 101, gradient substrates 101, or mixed-orientation substrates 101.

[0027] Some of these semiconductor structures include: The gate structure and the source and drain regions formed on both sides of the gate structure, the gate structure including a polysilicon gate 102 and sidewalls 103 located on both sides of the polysilicon gate 102, the material of the sidewalls 103 typically including at least one of silicon dioxide and silicon nitride. In an embodiment of the present invention, n semiconductor device structures are sequentially formed on the substrate 101, and an antenna end structure is also formed on one side of the semiconductor structure. Some of the semiconductor structures are the first 2 or 3 semiconductor structures close to the antenna end structure, where n is an integer greater than 3. Only the high dielectric constant material layer 110 is filled between the first 2-3 dielectric layers close to the antenna end structure, which will not have a significant impact on the harmonic performance of the device.

[0028] For example, please refer to Figure 11 n semiconductor device structures are sequentially formed on substrate 101. An antenna terminal structure is also formed on one side of the semiconductor structure. Some of the semiconductor structures are the first two semiconductor structures close to the antenna terminal structure, where n is an integer greater than 3. Only the first 2-3 dielectric layers of high dielectric constant material 110 are filled between the dielectric layers close to the antenna terminal structure. The source-drain voltage (Vds) of the n semiconductor device structures without high dielectric constant material layer 110 is shown as curve 201. The source-drain voltage (Vds) of the n semiconductor device structures with high dielectric constant material layer 110 is shown as curve 202. When n is greater than 7, the source-drain voltage decreases.

[0029] Etching stop layer 112 covering the gate structure; In an embodiment of the present invention, the material of the etch stop layer 112 is silicon nitride.

[0030] The first interlayer dielectric layer 104 is formed on the etch stop layer 112; The first and second metal layers (113, 105) are used to extract the source and drain regions, respectively. In an embodiment of the present invention, the material of the first and second metal layers (113, 105) is tungsten.

[0031] The first dielectric barrier layer 106 formed on the first and second metal layers (113, 105) and the first interlayer dielectric layer 104 is intended to prevent metal from diffusing into the dielectric. The second interlayer dielectric layer 107 formed on the first dielectric barrier layer 106 is also present. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer medium and the first dielectric barrier layer 106 below it. A third metal layer 108 is filled in the first groove. The third metal layer 108 is electrically connected to the first and second metal layers (113, 105) respectively. In an embodiment of the present invention, the material of the third metal layer 108 is copper.

[0032] In an embodiment of the present invention, the material of the dielectric layer between the first and second layers is silicon dioxide.

[0033] A second groove is formed on the second interlayer dielectric layer 107, and a high dielectric constant material layer 110 is filled in the second groove, which is equivalent to connecting a capacitor in parallel on the semiconductor structure, which can reduce the voltage division of the transistor. A third dielectric barrier layer 111 is formed on the planarized third metal layer 108, the high dielectric constant material layer 110, the second interlayer dielectric layer 107, and the high dielectric constant material layer 110. In embodiments of the present invention, the materials of the first and third dielectric barrier layers are doped silicon carbide.

[0034] In embodiments of the present invention, the material of the high dielectric constant material layer 110 includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

[0035] The remaining semiconductor structures all include: Gate structure and source and drain regions formed on both sides of the gate structure; Etching stop layer 112 covering the gate structure; In an embodiment of the present invention, the material of the etch stop layer 112 is silicon nitride.

[0036] The first interlayer dielectric layer 104 is formed on the etch stop layer 112; The first and second metal layers (113, 105) are used to extract the source and drain regions, respectively. In an embodiment of the present invention, the material of the first and second metal layers (113, 105) is tungsten.

[0037] A first dielectric barrier layer 106 is formed on the first and second metal layers (113, 105) and the first interlayer dielectric layer 104, and a second interlayer dielectric layer 107 is formed on the first dielectric barrier layer 106. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer dielectric layer 107 and the first dielectric barrier layer 106 below it. A third metal layer 108 is filled in the first groove. The third metal layer 108 is electrically connected to the first and second metal layers (113, 105) respectively. In an embodiment of the present invention, the material of the third metal layer 108 is copper.

[0038] In an embodiment of the present invention, the material of the dielectric layer between the first and second layers is silicon dioxide.

[0039] A third dielectric barrier layer is formed on the third metal layer 108, the high dielectric constant material layer 110, and the second interlayer dielectric layer 107.

[0040] In embodiments of the present invention, the materials of the first and third dielectric barrier layers are doped silicon carbide.

[0041] Please see Figure 13 The present invention also provides a method for manufacturing a radio frequency switch transistor, comprising: Step 1, please refer to Figure 3 A substrate 101 is provided, on which a plurality of semiconductor device structures are sequentially formed; Each semiconductor structure includes: The gate structure and the source and drain regions formed on both sides of the gate structure, the gate structure including a polysilicon gate 102 and sidewalls 103 located on both sides of the polysilicon gate 102, the material of the sidewalls 103 typically including at least one of silicon dioxide and silicon nitride. Etching stop layer 112 covering the gate structure; The first interlayer dielectric layer 104 is formed on the etch stop layer 112; The first and second metal layers (113, 105) are used to extract the source region and the drain region, respectively; a first dielectric barrier layer 106 is formed on the first and second metal layers (113, 105) and the first interlayer dielectric layer 104; and a second interlayer dielectric layer 107 is formed on the first dielectric barrier layer 106. In embodiments of the present invention, the substrate 101 in step one comprises a bulk semiconductor substrate 101 or a silicon-on-insulator (SOI) substrate 101. The SOI substrate 101 includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate 101. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates 101 that may be used include multilayer substrates 101, gradient substrates 101, or mixed-orientation substrates 101.

[0042] In an embodiment of the present invention, substrate 101 In an embodiment of the present invention, the material of the etching stop layer 112 in step one is silicon nitride.

[0043] In the embodiments of the present invention, the materials of the first and second interlayer dielectric layers in step one are both silicon dioxide.

[0044] In an embodiment of the present invention, the materials of the first and second metal layers (113, 105) in step one are both tungsten.

[0045] Step 2: A photoresist layer is formed on the second interlayer dielectric layer 107. Photolithography (exposure, vertical film formation, development, baking, etc.) opens the photoresist layer on the semiconductor device structure, exposing the second interlayer dielectric layer 107 to be etched below it. In an embodiment of the present invention, n semiconductor device structures are sequentially formed on the substrate 101 in step two. An antenna end structure is also formed on one side of the semiconductor structure. Some of the semiconductor structures are the first two or three semiconductor structures close to the antenna end structure, where n is an integer greater than 3.

[0046] In an embodiment of the present invention, n semiconductor device structures are sequentially formed on the substrate 101, and an antenna end structure is also formed on one side of the semiconductor structure. Some of the semiconductor structures are the first 2 or 3 semiconductor structures close to the antenna end structure, where n is an integer greater than 3. Only the high dielectric constant material layer 110 is filled between the first 2-3 dielectric layers close to the antenna end structure, which will not have a significant impact on the harmonic performance of the device.

[0047] For example, please refer to Figure 11 n semiconductor device structures are sequentially formed on substrate 101. An antenna terminal structure is also formed on one side of the semiconductor structure. Some of the semiconductor structures are the first two semiconductor structures close to the antenna terminal structure, where n is an integer greater than 3. Only the first 2-3 dielectric layers of high dielectric constant material 110 are filled between the dielectric layers close to the antenna terminal structure. The source-drain voltage (Vds) of the n semiconductor device structures without high dielectric constant material layer 110 is shown as curve 201. The source-drain voltage (Vds) of the n semiconductor device structures with high dielectric constant material layer 110 is shown as curve 202. When n is greater than 7, the source-drain voltage decreases.

[0048] Step 3, please refer to Figure 4 The first groove is formed by etching the exposed second interlayer dielectric layer 107 and the first interlayer dielectric layer 104 below it. The etching method is usually dry etching, which exposes the first and second metal layers (113, 105). The remaining photoresist layer can then be removed by ashing and wet cleaning. Step 4: A third metal layer 108 is formed by deposition and grinding to fill the first groove, forming a structure as shown in the figure. Figure 5 The structure shown, for example, involves forming a third metal layer 108 by physical vapor deposition, followed by polishing the third metal layer 108 by chemical mechanical planarization, and then forming a second dielectric barrier layer 109 on the third metal layer 108 and the second interlayer dielectric layer 107, to form a structure as shown. Figure 6 The structure shown; In an embodiment of the present invention, the material of the third metal layer 108 in step four is copper.

[0049] Step 5: Etch the second dielectric barrier layer 109 between the third metal layers 108 of the semiconductor structure and the second interlayer dielectric layer 107 below it to form a second groove, forming as shown in the figure. Figure 7 The structure shown is typically etched using dry etching, forming a high dielectric constant material layer 110 on the second groove, as shown. Figure 8 The structure shown is then ground down to expose the high dielectric constant material layer 110 and the underlying second dielectric barrier layer 109 to the third metal layer 108, forming a structure as shown. Figure 9 The structure shown typically employs chemical mechanical planarization (CMP) grinding, followed by the formation of a third dielectric barrier layer 111 on the third metal layer 108, the high dielectric constant material layer 110, and the second interlayer dielectric layer 107, forming a structure as described above. Figure 10 The structure shown.

[0050] In an embodiment of the present invention, the material of the high dielectric constant material layer 110 in step five includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

[0051] In the embodiments of the present invention, the materials of the first dielectric barrier layer 106 in step one, the second dielectric barrier layer 109 in step four, and the third dielectric barrier layer 111 in step five are all doped silicon carbide.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] In summary, compared to traditional methods of adding MIM structures (sandwich structures composed of three thin films: metal, insulator, and metal), this invention requires only one layer of photolithography, significantly reducing costs. Furthermore, by filling the first 2-3 dielectric layers near the antenna end with a high-dielectric-constant material layer, it does not significantly impact the device's harmonic performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A radio frequency switching transistor, characterized in that, include: A substrate on which a plurality of semiconductor device structures are sequentially formed; wherein, n semiconductor device structures are sequentially formed on the substrate, and an antenna end structure is formed on one side of each semiconductor structure, and some of the semiconductor structures are the first 2 or 3 semiconductor structures close to the antenna end structure, where n is an integer greater than 3; The semiconductor structures described herein all include: Gate structure and source and drain regions formed on both sides of the gate structure; Etch stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to draw out the source region and the drain region, respectively; A first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the first dielectric barrier layer. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer dielectric and the first dielectric barrier layer below it. The first groove is filled with a third metal layer, which is electrically connected to the first and second metal layers respectively. A second groove is formed on the second interlayer dielectric layer, and a high dielectric constant material layer is filled in the second groove. A third dielectric barrier layer is formed on the third metal layer, the second interlayer dielectric layer, and the high dielectric constant material layer. The remaining semiconductor structures all include: Gate structure and source and drain regions formed on both sides of the gate structure; Etch stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to draw out the source region and the drain region, respectively; A first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the first dielectric barrier layer. The materials of the first and second interlayer dielectric layers are both low dielectric constant. A first groove is formed on the second interlayer dielectric and the first dielectric barrier layer below it. The first groove is filled with a third metal layer, which is electrically connected to the first and second metal layers respectively. A third dielectric barrier layer is formed on the third metal layer and the second interlayer dielectric layer.

2. The radio frequency switch transistor according to claim 1, characterized in that: The substrate includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The radio frequency switch transistor according to claim 1, characterized in that: The material of the dielectric layer between the first and second layers is silicon dioxide.

4. The radio frequency switch transistor according to claim 1, characterized in that: The first and second metal layers are made of tungsten.

5. The radio frequency switch transistor according to claim 1, characterized in that: The material of the third metal layer is copper.

6. The radio frequency switch transistor according to claim 1, characterized in that: The material of the etching stop layer is silicon nitride.

7. The radio frequency switch transistor according to claim 1, characterized in that: The first and third dielectric barrier layers are made of doped silicon carbide.

8. The radio frequency switch transistor according to claim 1, characterized in that: The material of the high dielectric constant material layer includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

9. A method for manufacturing a radio frequency switch transistor according to any one of claims 1 to 8, characterized in that, At least including: Step 1: Provide a substrate on which a plurality of semiconductor device structures are sequentially formed; n semiconductor device structures are sequentially formed on the substrate, and an antenna terminal structure is formed on one side of each semiconductor structure. Some of the semiconductor structures are the first 2 or 3 semiconductor structures closest to the antenna terminal structure, where n is an integer greater than 3; wherein each semiconductor structure includes: Gate structure and source and drain regions formed on both sides of the gate structure; Etch stop layer covering the gate structure; The first interlayer dielectric layer is formed on the etching stop layer; The first and second metal layers are used to bring out the source region and the drain region, respectively; a first dielectric barrier layer is formed on the first and second metal layers and the first interlayer dielectric layer; and a second interlayer dielectric layer is formed on the first dielectric barrier layer. Step 2: Form a photoresist layer on the second interlayer dielectric layer, and use photolithography to open the photoresist layer on the semiconductor device structure, so that the second interlayer dielectric layer to be etched underneath is exposed. Step 3: Etch the exposed second interlayer dielectric layer and the first interlayer dielectric layer below it to form a first groove, thereby exposing the first and second metal layers, and then remove the remaining photoresist layer; Step 4: A third metal layer is formed to fill the first groove by deposition and grinding, and then a second dielectric barrier layer is formed on the third metal layer and the second interlayer dielectric layer. Step 5: Etch the second dielectric barrier layer between the third metal layers of the semiconductor structure and the second interlayer dielectric layer below it to form a second groove. Form a high dielectric constant material layer on the second groove. Then grind the high dielectric constant material layer and the second dielectric barrier layer below it until the third metal layer is exposed. Then form a third dielectric barrier layer on the third metal layer, the high dielectric constant material layer, and the second interlayer dielectric layer.

10. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

11. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The material of the etching stop layer in step one is silicon nitride.

12. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The material of the first and second interlayer dielectric layers in step one is silicon dioxide.

13. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The materials of the first and second metal layers in step one are both tungsten.

14. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The materials of the first dielectric barrier layer in step one, the second dielectric barrier layer in step four, and the third dielectric barrier layer in step five are all doped silicon carbide.

15. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The material of the third metal layer in step four is copper.

16. The method for manufacturing a radio frequency switch transistor according to claim 9, characterized in that: The material of the high dielectric constant material layer in step five includes at least one of SION, ALO, HfO2, Ta2O5, TiO2, and ZrO2.

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