A two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor and its fabrication method

Abstract

This invention discloses a two-dimensional gallium oxide ferroelectric gate enhancement-mode field-effect transistor and its fabrication method, belonging to the field of semiconductor device technology, and solving the problem of the difficulty in fabricating enhancement-mode Ga2O3 devices. The transistor includes a substrate layer, a channel layer, and an electrode layer connected layer by layer. The channel is obtained by mechanically lifting or epitaxially fabricating a Ga2O3 thin film, which is simpler and easier to operate compared to other fabrication methods. In addition, the substrate can be selected from a wide range of materials with good compatibility. The structure of the charge storage gate has minimal impact on the channel conductivity. The two-dimensional ferroelectric gate acts as a charge storage gate, utilizing its spontaneous in-plane and out-of-plane polarization effects to collect channel carriers and deplete the channel, thus realizing an enhancement-mode Ga2O3 device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor and its fabrication method. Background Technology

[0002] Ga2O3, as an emerging ultra-wide bandgap semiconductor material, boasts a bandgap of 4.5-4.9 eV and a critical breakdown field strength as high as approximately 8 MV / cm, theoretically achieving more than twice the power of SiC and GaN. Simultaneously, its low ionization rate and extremely low theoretical on-resistance result in significantly lower losses in unipolar devices compared to SiC and GaN. Ga2O3 exhibits five crystal morphologies: α, β, γ, δ, and ε. β-Ga2O3, due to its chemical stability and direct bandgap, has been widely studied and applied. β-Ga2O3 belongs to the monoclinic crystal system, is transparent, and can be cleaved along the (100) plane to form films, allowing Ga2O3 devices to be fabricated using a simple mechanical exfoliation method. Its ability to be exfoliated into nanofilms and its high theoretical power give Ga2O3 unique advantages in power electronic devices. However, at the same time, it also faces many difficulties. In addition to the significant self-heating effect, the difficulty in achieving p-type doping, and the low mobility, the difficulty in fabricating enhanced Ga2O3 devices is one of the most urgent problems to be solved, because Ga2O3 devices are the preferred devices in a wide range of practical power switching applications. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, the present invention aims to provide a two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor.

[0004] The objective of this invention can be achieved through the following technical solutions:

[0005] A two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor includes a substrate layer, a channel layer, and an electrode layer connected layer by layer. The electrode layer includes a gate electrode module, a source electrode, and a drain electrode. The gate electrode module is disposed on the top surface of the channel layer. The source electrode and drain electrode are disposed on opposite sides of the gate electrode module and connected to the top surface of the channel layer. The gate electrode module includes a charge tunneling layer, a charge storage gate, and a gate electrode. The charge tunneling layer is disposed on the top surface of the channel layer, the gate electrode is disposed on the top surface of the charge tunneling layer, and the charge storage gate is embedded between the charge tunneling layer and the gate electrode.

[0006] The present invention also aims to provide a method for fabricating a two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor. This method, applied to the aforementioned two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor, includes the following steps:

[0007] Step 1: Take a sample of the original substrate material and clean the surface of the original substrate material in sequence with acetone, isopropanol and deionized water to obtain a clean substrate.

[0008] Step 2: Place the blocky β-Ga2O3 crystal on the first tape and repeatedly tear it to obtain a two-dimensional β-Ga2O3 crystal, i.e., a Ga2O3 film. Transfer the Ga2O3 film on the first tape through the second tape and select a Ga2O3 film of appropriate thickness under an optical microscope.

[0009] Step 3: Transfer the Ga2O3 film to the surface of the substrate, with the Ga2O3 film serving as a channel;

[0010] Step 4: Coat the substrate surface with photoresist, and after pre-baking, masking, photolithography and development, rinse with deionized water and dry with nitrogen to form the source and drain regions of the opening.

[0011] Step 5: Deposit metal in the source and drain regions of the opening, place the sample after metal deposition in the stripping solution, and form the source and drain electrodes after stripping.

[0012] Step 6: Anneal the stripped sample to form an ohmic contact between the source and drain electrodes;

[0013] Step 7: The resulting charge tunneling layer is obtained after processing;

[0014] Step 8: The obtained ferroelectric grating thin film is used as a charge storage gate;

[0015] Step 9: Deposit the gate electrode onto the second tape and heat the second tape. Align the gate electrode with the charge storage gate and completely cover it. After 60 seconds, peel off the second tape and transfer the gate electrode to the top surface of the charge storage gate to form a Schottky contact for the gate electrode. Clean the sample again with acetone, isopropanol, and deionized water to complete the fabrication of the device.

[0016] As a preferred embodiment of the present invention: the substrate in step 1 is adopted. The substrate or the structure is made of diamond.

[0017] As a preferred embodiment of the present invention: the β-Ga₂O₃ crystal in step 2 should be n-type doped with a doping concentration of 1×10⁻⁶. 16 -2×10 18 cm- 3 Within this range, the thickness is 100-500nm.

[0018] As a preferred technical solution of the present invention: the channel in step 3 is made by mechanical peeling or by epitaxy.

[0019] As a preferred technical solution of the present invention: the metal in step 5 is composed of Ti / Au.

[0020] As a preferred embodiment of the present invention, the annealing temperature for forming the ohmic contact in step 6 is 450-480°C, and the annealing time is 60-90 seconds.

[0021] As a preferred technical solution of the present invention: the charge tunneling layer in step 7 is made by mechanically peeling off h-BN, or the charge tunneling layer is made by Al2O3.

[0022] As a preferred technical solution of the present invention: the ferroelectric grid film in step 8 is made by mechanically peeling off In2Se3, or the ferroelectric grid film is made by spin coating P(VDF-TrFE).

[0023] As a preferred technical solution of the present invention: the gate electrode in step 9 is made of vapor-deposited Mo / Au.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] 1. The channels are obtained by mechanical exfoliation or epitaxy to prepare Ga2O3 thin films. Compared with other preparation methods, it is simple and easy to operate, and has advantages such as high interface quality, low leakage channels and low density defects.

[0026] 2. Based on this, since the Ga2O3 thin film serves as the channel, the substrate can be selected from a wide range of materials with good compatibility. If the substrate is made of diamond with high thermal conductivity, it can effectively suppress the self-heating effect of Ga2O3 devices caused by poor heat dissipation.

[0027] 3. The structure based on the charge storage gate has minimal impact on the channel conductivity, avoiding damage to the gate electrode caused by dry etching, which affects the carrier mobility and device reliability.

[0028] 4. Two-dimensional ferroelectric gates are used as charge storage gates. They utilize their spontaneous in-plane and out-of-plane polarization effects to collect channel carriers and deplete the channel, thereby realizing enhanced Ga2O3 devices. Attached Figure Description

[0029] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0030] Figure 1 This is a side view of the device structure of the present invention;

[0031] Figure 2 This is a top view of the device structure of the present invention;

[0032] Figure 3 This is a process flow diagram of the present invention.

[0033] Explanation of reference numerals in the attached figures:

[0034] 1. Substrate layer; 2. Channel layer; 3. Charge tunneling layer; 4. Charge storage gate; 5. Gate electrode; 6. Source electrode; 7. Drain electrode. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Please see Figure 1-2 This invention provides a two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor, comprising a substrate layer 1, a channel layer 2, and an electrode layer connected layer by layer. The electrode layer includes a gate electrode module, a source electrode 6, and a drain electrode 7. The gate electrode module is disposed on the top surface of the channel layer 2. The source electrode 6 and the drain electrode 7 are disposed on opposite sides of the gate electrode module and connected to the top surface of the channel layer 2. The gate electrode module includes a charge tunneling layer 3, a charge storage gate 4, and a gate electrode 5. The charge tunneling layer 3 is disposed on the top surface of the channel layer 2, the gate electrode 5 is disposed on the top surface of the charge tunneling layer 3, and the charge storage gate 4 is embedded between the charge tunneling layer 3 and the gate electrode 5.

[0037] Please see Figure 3 The present invention also provides a method for fabricating a two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor, which is applied to the aforementioned two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor.

[0038] Example 1: Substrate used The charge tunneling layer is fabricated using mechanically stripped h-BN, and the charge storage gate is fabricated using mechanically stripped In2Se3.

[0039] Step 1: Select and clean Substrate.

[0040] Select a thickness of approximately 300nm The reaction was carried out using acetone, isopropanol, and deionized water in sequence. The surface was cleaned for 15 minutes, 15 minutes and 5 minutes, and then dried with nitrogen to obtain a clean substrate.

[0041] Step 2: Prepare Ga2O3 thin film.

[0042] The doping type was selected as n-type, and the doping concentration was 1.8 × 10⁻⁶.17 cm- 3 A 350nm thick blocky β-Ga2O3 crystal was obtained, its (100) crystal orientation was found, and it was placed on NITTO blue tape. The two-dimensional β-Ga2O3 crystal, i.e. Ga2O3 film, was obtained by repeatedly tearing it. The Ga2O3 film on the NITTO blue tape was transferred through PDMS tape, and a Ga2O3 film with a thickness of 100nm was selected under an optical microscope.

[0043] Step 3: Transfer the Ga2O3 thin film.

[0044] Using the cantilever beam of the transfer platform, the PDMS tape with the Ga2O3 film from step 2 is slowly applied close to the surface of the substrate, and a 1200 g / cm² pressure is applied to the bonding area. 2 The pressure was applied and held for 40 seconds before the PDMS tape was peeled off to allow the van der Waals forces to fully exert their effect, transferring the Ga2O3 film to the surface of the substrate. The substrate was then placed in a vacuum environment for 30 minutes to remove air bubbles, thereby obtaining good interface properties. The Ga2O3 film served as the channel.

[0045] Step 4: Form the source / drain region.

[0046] First, photoresist is uniformly coated on the sample surface; then the sample is placed on a heating plate at 100°C and dried for 120 seconds to obtain a photoresist with a thickness of 1 μm; then the sample is masked and exposed using a photolithography machine for 4 seconds; finally, the sample is placed in a developing solution for 90 seconds, and then rinsed with deionized water and dried with nitrogen to form the source and drain regions with openings.

[0047] Step 5: Deposit metal and strip it.

[0048] 20 / 80 nm Ti / Au metal was deposited in the source and drain regions of the opening using an electron beam evaporation E-Beam system. The deposited sample was then placed in a stripping solution and stripped to form the source and drain electrodes.

[0049] Step 6: Annealing to form ohmic contacts.

[0050] The stripped sample was placed in an annealing furnace and annealed for 60 seconds in a nitrogen atmosphere at 480°C to form an ohmic contact between the source and drain electrodes.

[0051] Step 7: Strip and transfer the h-BN charge tunneling layer.

[0052] First, select the original material for the charge tunneling layer; second, place it on NITTO blue tape and cleave it to obtain an h-BN film; third, cut out small pieces of transparent PDMS tape and attach the h-BN film from the NITTO blue tape to the PDMS tape; fourth, select a film of suitable area using atomic force microscopy and optical microscopy, and mechanically peel it off to obtain an h-BN film with a thickness of 15 nm; fifth, process the h-BN film; sixth, transfer the processed h-BN film to the surface of the channel as the charge tunneling layer.

[0053] In this embodiment, the fifth detailed process flow is as follows: First, the mechanically fixed transparent peel with Pritt tape is spin-coated with a 1μm methacrylate copolymer molten in methyl isobutyl ketone solution (MIBK solvent); then the transfer film is baked at 120°C for 10 min to remove the MIBK solvent from the copolymer, and an h-BN nanofilm is deposited on the methacrylate copolymer at an ambient temperature of 75-100°C; then the copolymer with h-BN flakes is aligned with the gallium oxide channel, and the polymer-side mask is lowered onto the heated substrate so that the polymer contacts the substrate surface and melts and adheres to the substrate; finally, the methacrylate polymer is removed by soaking in acetone solution for 30 min, and then the copolymer is removed by rinsing with isopropanol.

[0054] Step 8: Strip and transfer the In2Se3 charge storage gate.

[0055] First, a 10 nm thick bulk α-In₂Se₃ crystal was selected. Then, it was placed on NITTO blue tape and mechanically peeled off to obtain a two-dimensional α-In₂Se₃ crystal, i.e., an In₂Se₃ thin film. Next, the In₂Se₃ thin film was transferred and aligned to the surface of the h-BN charge tunneling layer using an XYZ transfer alignment system, ensuring that the area of ​​the In₂Se₃ thin film was smaller than the area of ​​the h-BN charge tunneling layer. Finally, the transferred sample was immersed in acetone solution for 20 min, rinsed with deionized water and dried with nitrogen gas to remove residual NITTO blue tape. The obtained In₂Se₃ thin film was used as a charge storage gate.

[0056] Step 9: Transfer the gate electrode to form a Schottky contact.

[0057] Mo / Au deposited at 10 / 80 nm was deposited as the gate electrode on PDMS tape. The PDMS tape was heated at 60 °C for 1 min to align the gate electrode with and completely cover the In2Se3 charge storage gate. After 60 s, the PDMS tape was peeled off, and the gate electrode was transferred to the top surface of the In2Se3 charge storage gate to form a Schottky contact for the gate electrode. The sample was then cleaned again with acetone, isopropanol, and deionized water to complete the fabrication of the device.

[0058] Example 2: The substrate is made of diamond, the charge tunneling layer is made of Al2O3, and the charge storage gate is made of mechanically stripped In2Se3.

[0059] Step 1: Select and clean Substrate.

[0060] Diamond was selected and acid-washed for 20 minutes at 250°C in a 1:1 HNO3:H2SO4 solution.

[0061] Select a thickness of approximately 300nm The diamond surface was cleaned sequentially with acetone, isopropanol and deionized water for 15 min, 15 min and 5 min respectively, to obtain a clean substrate.

[0062] Step 2: Prepare Ga2O3 thin film.

[0063] The doping type was selected as n-type, and the doping concentration was 1.8 × 10⁻⁶. 17 cm- 3 A 350nm thick blocky β-Ga2O3 crystal was found with its (100) crystal orientation and placed on a NITTO blue tape. The two-dimensional β-Ga2O3 crystal, i.e. Ga2O3 film, was obtained by repeatedly tearing it. The Ga2O3 film on the NITTO blue tape was transferred through PDMS tape, and a Ga2O3 film with a thickness of 200nm was selected under an optical microscope.

[0064] Step 3: Transfer the Ga2O3 thin film.

[0065] Using the cantilever beam of the transfer platform, the PDMS tape with the Ga2O3 film from step 2 is slowly applied close to the surface of the substrate, and a 1200 g / cm² pressure is applied to the bonding area. 2 The pressure was applied and held for 40 seconds before the PDMS tape was peeled off to allow the van der Waals forces to fully exert their effect, transferring the Ga2O3 film to the surface of the substrate. The substrate was then placed in a vacuum environment for 30 minutes to remove air bubbles, thereby obtaining good interface properties. The Ga2O3 film served as the channel.

[0066] Step 4: Form the source / drain region.

[0067] First, photoresist is uniformly coated on the sample surface; then the sample is placed on a heating plate at 100°C and dried for 120 seconds to obtain a photoresist with a thickness of 1 μm; then the sample is masked and exposed using a photolithography machine for 4 seconds; finally, the sample is placed in a developing solution for 90 seconds, and then rinsed with deionized water and dried with nitrogen to form the source and drain regions with openings.

[0068] Step 5: Deposit metal and strip it.

[0069] 20 / 80 nm Ti / Au metal was deposited in the source and drain regions of the opening using an electron beam evaporation E-Beam system. The deposited sample was then placed in a stripping solution and stripped to form the source and drain electrodes.

[0070] Step 6: Annealing to form ohmic contacts.

[0071] The stripped sample was placed in an annealing furnace and annealed for 60 seconds in a nitrogen atmosphere at 480°C to form an ohmic contact between the source and drain electrodes.

[0072] Step 7: Deposit and strip the Al2O3 charge tunneling layer.

[0073] First, photoresist is uniformly coated on the sample surface. After pre-baking, masking, photolithography and development, the patterned sample is placed in the PEALD chamber. Al2O3 is deposited using TMA and H2O as precursors, with a deposition thickness of about 20 nm. Finally, the sample is placed in the stripping solution to remove the photoresist. The surface of the treated channel serves as the charge tunneling layer.

[0074] Step 8: Strip and transfer the In2Se3 charge storage gate.

[0075] First, a 10 nm thick bulk α-In₂Se₃ crystal was selected. Then, it was placed on NITTO blue tape and mechanically peeled off to obtain a two-dimensional α-In₂Se₃ crystal, i.e., an In₂Se₃ thin film. Next, the In₂Se₃ thin film was transferred and aligned to the surface of the h-BN charge tunneling layer using an XYZ transfer alignment system, ensuring that the area of ​​the In₂Se₃ thin film was smaller than the area of ​​the h-BN charge tunneling layer. Finally, the transferred sample was immersed in acetone solution for 20 min, rinsed with deionized water and dried with nitrogen gas to remove residual NITTO blue tape. The obtained In₂Se₃ thin film was used as a charge storage gate.

[0076] Step 9: Transfer the gate electrode to form a Schottky contact.

[0077] Mo / Au deposited at 10 / 80 nm was deposited as the gate electrode on PDMS tape. The PDMS tape was heated at 60 °C for 1 min to align the gate electrode with and completely cover the In2Se3 charge storage gate. After 60 s, the PDMS tape was peeled off, and the gate electrode was transferred to the top surface of the In2Se3 charge storage gate to form a Schottky contact for the gate electrode. The sample was then cleaned again with acetone, isopropanol, and deionized water to complete the fabrication of the device.

[0078] Example 3: The substrate is made of diamond, the charge tunneling layer is fabricated by mechanical lift-off h-BN, and the charge storage gate is fabricated by spin coating P(VDF-TrFE).

[0079] Step 1: Select and clean Substrate.

[0080] Diamond was selected and acid-washed for 20 minutes at 250°C in a 1:1 HNO3:H2SO4 solution.

[0081] Select a thickness of approximately 300nm The diamond surface was cleaned sequentially with acetone, isopropanol and deionized water for 15 min, 15 min and 5 min respectively, to obtain a clean substrate.

[0082] Step 2: Prepare Ga2O3 thin film.

[0083] The doping type was selected as n-type, and the doping concentration was 1.8 × 10⁻⁶. 17 cm- 3 A 350nm thick blocky β-Ga2O3 crystal was obtained, its (100) crystal orientation was found, and it was placed on NITTO blue tape. The two-dimensional β-Ga2O3 crystal, i.e. Ga2O3 film, was obtained by repeatedly tearing it. The Ga2O3 film on the NITTO blue tape was transferred through PDMS tape, and a Ga2O3 film with a thickness of 100nm was selected under an optical microscope.

[0084] Step 3: Transfer the Ga2O3 thin film.

[0085] Using the cantilever beam of the transfer platform, the PDMS tape with the Ga2O3 film from step 2 is slowly applied close to the surface of the substrate, and a 1200 g / cm² pressure is applied to the bonding area. 2 The pressure was applied and held for 40 seconds before the PDMS tape was peeled off to allow the van der Waals forces to fully exert their effect, transferring the Ga2O3 film to the surface of the substrate. The substrate was then placed in a vacuum environment for 30 minutes to remove air bubbles, thereby obtaining good interface properties. The Ga2O3 film served as the channel.

[0086] Step 4: Form the source / drain region.

[0087] First, photoresist is uniformly coated on the sample surface; then the sample is placed on a heating plate at 100°C and dried for 120 seconds to obtain a photoresist with a thickness of 1 μm; then the sample is masked and exposed using a photolithography machine for 4 seconds; finally, the sample is placed in a developing solution for 90 seconds, and then rinsed with deionized water and dried with nitrogen to form the source and drain regions with openings.

[0088] Step 5: Deposit metal and strip it.

[0089] 20 / 80 nm Ti / Au metal was deposited in the source and drain regions of the opening using an electron beam evaporation E-Beam system. The deposited sample was then placed in a stripping solution and stripped to form the source and drain electrodes.

[0090] Step 6: Annealing to form ohmic contacts.

[0091] The stripped sample was placed in an annealing furnace and annealed for 60 seconds in a nitrogen atmosphere at 480°C to form an ohmic contact between the source and drain electrodes.

[0092] Step 7: Strip and transfer the h-BN charge tunneling layer.

[0093] First, select the original material for the charge tunneling layer; second, place it on NITTO blue tape and cleave it to obtain an h-BN film; third, cut out small pieces of transparent PDMS tape and attach the h-BN film from the NITTO blue tape to the PDMS tape; fourth, select a film of suitable area using atomic force microscopy and optical microscopy, and mechanically peel it off to obtain an h-BN film with a thickness of 15 nm; fifth, process the h-BN film; sixth, transfer the processed h-BN film to the surface of the channel as the charge tunneling layer.

[0094] In this embodiment, the fifth detailed process flow is as follows: First, the mechanically fixed transparent peel with Pritt tape is spin-coated with a 1μm methacrylate copolymer molten in methyl isobutyl ketone solution (MIBK solvent); then the transfer film is baked at 120°C for 10 min to remove the MIBK solvent from the copolymer, and an h-BN nanofilm is deposited on the methacrylate copolymer at an ambient temperature of 75-100°C; then the copolymer with h-BN flakes is aligned with the gallium oxide channel, and the polymer-side mask is lowered onto the heated substrate so that the polymer contacts the substrate surface and melts and adheres to the substrate; finally, the methacrylate polymer is removed by soaking in acetone solution for 30 min, and then the copolymer is removed by rinsing with isopropanol.

[0095] Step 8: Spin-coat and strip the P(VDF-TrFE) charge storage gate.

[0096] First, photoresist is uniformly coated onto the sample surface. After pre-baking, masking, photolithography, and development, a portion of the area above the charge tunneling layer is retained. The sample is then rinsed with deionized water and dried with nitrogen. Next, P(VDF-TrFE) and N-dimethylformamide (DMF) solution are mixed uniformly at a ratio of 2:8 to serve as the stripping solution. Simultaneously, the sample is placed in a spin coater for deposition, with spin coating parameters set to 2000 r / min for 60 s. The sample is then dried in a 100°C oven for 120 s. Finally, when the P(VDF-TrFE) copolymer has deposited to form a P(VDF-TrFE) film in the area to be deposited, the sample is placed in the stripping solution. The resulting P(VDF-TrFE) film serves as a charge storage gate.

[0097] Step 9: Transfer the gate electrode to form a Schottky contact.

[0098] Mo / Au deposited at 10 / 80 nm was deposited as the gate electrode on PDMS tape. The PDMS tape was heated at 60 °C for 1 min to align the gate electrode with and completely cover the P(VDF-TrFE) charge storage gate. After 60 s, the PDMS tape was peeled off, and the gate electrode was transferred to the top surface of the P(VDF-TrFE) charge storage gate to form a Schottky contact for the gate electrode. The sample was then cleaned again with acetone, isopropanol, and deionized water to complete the fabrication of the device.

[0099] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A two-dimensional gallium oxide ferroelectric gate enhanced field effect transistor, characterized by: The substrate layer (1), the channel layer (2) and the electrode layer including layer-by-layer connection, the electrode layer includes the gate electrode module, the source electrode (6) and the drain electrode (7), the gate electrode module is arranged on the top surface of the channel layer (2), the source electrode (6) and the drain electrode (7) are arranged on the opposite sides of the gate electrode module and are connected with the top surface of the channel layer (2), the gate electrode module includes the charge tunneling layer (3), the charge storage gate (4) and the gate electrode (5), the charge tunneling layer (3) is arranged on the top surface of the channel layer (2), the gate electrode (5) is arranged on the top surface of the charge tunneling layer (3), and the charge storage gate (4) is embedded between the charge tunneling layer (3) and the gate electrode (5), wherein two-dimensional gallium oxide is used as the channel layer (2), and ferroelectric gate film is used as the charge storage gate (4).

2. A preparation method of a two-dimensional gallium oxide ferroelectric gate enhanced field effect transistor, which is applied to the two-dimensional gallium oxide ferroelectric gate enhanced field effect transistor of claim 1, wherein the preparation method comprises the following steps: The method comprises the following steps: ​ Step 1: sample the substrate raw material, and sequentially clean the surface of the substrate raw material by using acetone, isopropyl alcohol and deionized water to obtain a clean substrate; Step 2: place the block-shaped β-Ga2O3 crystal on a first adhesive tape, repeatedly tear to obtain a two-dimensional β-Ga2O3 crystal, i.e. Ga2O3 film, transfer the Ga2O3 film on the first adhesive tape through a second adhesive tape, and select a Ga2O3 film with appropriate thickness under an optical microscope; Step 3: transfer the Ga2O3 film to the surface of the substrate, and the Ga2O3 film is used as the channel layer; Step 4: uniformly coat photoresist on the surface of the substrate, after pre-baking, masking, photoetching and developing, rinse with deionized water and dry with nitrogen, to form an open source-drain region; Step 5: deposit metal in the open source-drain region, place the sample after metal deposition in a stripping solution, and form a source electrode and a drain electrode after stripping; Step 6: anneal the sample after stripping to form ohmic contact of the source electrode and the drain electrode; Step 7: process to obtain a charge tunneling layer; Step 8: process to obtain a ferroelectric gate film as a charge storage gate; Step 9: deposit a gate electrode on a second adhesive tape and heat the second adhesive tape, the gate electrode is aligned with and completely covers the charge storage gate, tear off the second adhesive tape after staying for 60s, transfer the gate electrode to the top surface of the charge storage gate to form Schottky contact of the gate electrode, and clean the sample again by using acetone, isopropyl alcohol and deionized water to complete the fabrication of the device.

3. The method of claim 2, wherein the method further comprises: The substrate of step 1 is made of SiO2 / p + Si, or the substrate is made of diamond.

4. The method of claim 2, wherein the method further comprises: The two-dimensional β-Ga2O3crystal of step 2 should be n-type with a doping concentration of 1×10 16 -2×10 18 cm -3 in the range of 100-500 nm in thickness.

5. The method of claim 2, wherein the method further comprises: The metal in step 5 is composed of Ti / Au.

6. The method of claim 2, wherein the method further comprises: The annealing temperature for forming ohmic contact in step 6 is 450-480 DEG C, and the annealing time is 60-90s.

7. The method of claim 2, wherein the method further comprises: depositing a gate dielectric layer on the substrate; depositing a gate electrode on the gate dielectric layer; and depositing a passivation layer on the gate electrode. The charge tunneling layer in step 7 is made of mechanically exfoliated h-BN, or the charge tunneling layer is made of Al2O3.

8. The method of claim 2, wherein the method further comprises: depositing a gate dielectric layer on the substrate; depositing a gate electrode on the gate dielectric layer; and depositing a passivation layer on the gate electrode. The ferroelectric gate film in step 8 is made of mechanically exfoliated In2Se3, or the ferroelectric gate film is made of spin-coated P(VDF-TrFE).

9. The method of claim 2, wherein the method further comprises: depositing a gate dielectric layer on the substrate; depositing a gate electrode on the gate dielectric layer; and depositing a passivation layer on the gate electrode. The gate electrode in step 9 is composed of evaporated Mo / Au.

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