A high-frequency ferroelectric negative-capacitance field effect transistor and a preparation method and application thereof

Abstract

The application discloses a high-frequency ferroelectric negative capacitance field effect transistor and a preparation method thereof, and belongs to the field of field effect transistor logic devices and circuits of CMOS super-large integrated circuits. The high-frequency negative capacitance field effect transistor provided by the application overcomes problems of low working frequency and large hysteresis of a traditional negative capacitance field effect transistor by taking a needle-shaped ferroelectric domain structure ferroelectric film with a fast ferroelectric negative capacitance effect as a gate dielectric layer and combining specific device structures and processes. Compared with similar devices, the product has the outstanding advantages of fast operation speed, small hysteresis and low power consumption, and has important academic and application values in the fields of microelectronic devices, military industry and aerospace.

Description

Technical Field

[0001] This invention relates to the field of microelectronic devices, and more specifically to a high-frequency ferroelectric negative capacitance field-effect transistor, its fabrication method, and its application. Background Technology

[0002] The rapid development of microelectronics technology is based on the continuous iteration of chip manufacturing processes. However, the thermal power consumption of chips has become a constraint on the reduction of chip manufacturing processes. Generally speaking, the subthreshold swing of traditional field-effect transistors cannot be less than 60mV / dec, which leads to a theoretical lower limit on their power consumption. In order to effectively reduce chip power consumption, novel device structures such as two-dimensional materials, quantum tunneling, and ferroelectric negative capacitance effect transistors have been proposed.

[0003] Ferroelectric negative capacitance transistors can effectively reduce subthreshold swing to below 60mV / dec, theoretically reducing power consumption of electronic devices by more than 10 times. However, the ferroelectric negative capacitance effect has problems such as low operating frequency and mismatch with chip operating frequency, and relatively serious hysteresis (polarization switching behavior usually involves multiple domain switching stages, which makes the total duration of polarization switching current often in μs or ms. When the total duration is longer than the operating signal period, the polarization switching charge will interfere with the normal operation of the device, which is simply referred to as "hysteresis"). These problems have brought many obstacles to the application of ferroelectric negative capacitance transistors.

[0004] In recent years, negative capacitance effect transistors based on hafnium oxide and antiferroelectric materials have been reported. Hafnium oxide ferroelectric negative capacitance effect transistors have the advantage of CMOS process compatibility, but they suffer from problems such as low operating frequency (typically less than 10MHz), difficulty in preparing single-crystal pure phase, poor stability, and small polarization. Antiferroelectric materials have a symmetrical unidirectional multi-potential well structure, which enables them to achieve a negative capacitance effect under a unidirectional electric field. However, because the antiferroelectric negative capacitance effect is based on a slow and unstable antiferroelectric-ferroelectric phase transition process, these antiferroelectric transistor devices suffer from problems such as low operating frequency (~1MHz), large hysteresis, the need for high electric field driving, and difficulty in electric field control.

[0005] Therefore, providing a negative capacitance field-effect transistor that can be applied at high frequencies, with low hysteresis and excellent power consumption control is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a high-frequency ferroelectric negative capacitance field-effect transistor, its fabrication method, and its application. By using a lead zirconate titanate ferroelectric thin film material with a needle-like ferroelastic domain structure exhibiting a fast negative capacitance effect as the gate dielectric layer in an NC-FET, the present invention not only overcomes the limitation of low operating frequency of NC-FETs and enables the device to operate in a high-frequency (>10MHz) environment, but also possesses advantages such as low hysteresis, good stability, low power consumption, and low cost, showing promising application prospects.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A high-frequency ferroelectric negative capacitance field-effect transistor includes a substrate and a channel layer;

[0009] The channel layer is deposited on top of the substrate;

[0010] A buffer layer is deposited above the middle position of the channel layer, a gate dielectric layer is deposited above the buffer layer, and a gate electrode is deposited above the gate dielectric layer.

[0011] The channel layer includes a channel and a source region and a drain region respectively disposed on both sides of the channel;

[0012] An active electrode is deposited above the source region, and a drain electrode is deposited above the drain region.

[0013] Furthermore, the substrate is made of one or more of the following materials: Si, Ge, SiGe, Ga2O3, GaAs, and GaN.

[0014] Preferably, the substrate is made of at least one or a combination of Si, Ge, and SiGe.

[0015] Furthermore, the channel layer is made of one or more combinations of SiO2, ZnO, SnO2, and GeO2; the thickness of the channel layer is 5–200 nm.

[0016] Preferably, the channel layer is made of one or more of ZnO, SiO2, and SnO2, and the thickness of the channel layer is 5 to 100 nm.

[0017] Furthermore, the buffer layer is one or more combinations of CoFe2O4, SrTiO3, PbTiO3, and PbZrO3; the thickness of the buffer layer is 5–100 nm.

[0018] Preferably, the buffer layer is one or a combination of SrTiO3, PbTiO3, and PbZrO3, and the thickness of the buffer layer is 5 to 50 nm.

[0019] Further, the material of the source electrode is one or a combination of more than one of Au, Pt, and SrRuO3, and the thickness of the source electrode is 5 - 150 nm;

[0020] Preferably, the source electrode is Au and / or SrRuO3, and the electrode thickness is 10 - 60 nm.

[0021] Further, the material of the drain electrode is one or a combination of more than one of Au, Pt, and SrRuO3, and the thickness of the drain electrode is 5 - 150 nm.

[0022] Preferably, the drain electrode is Au and / or SrRuO3, and the electrode thickness is 10 - 60 nm.

[0023] Further, the material of the gate dielectric layer is one or a combination of more than one of PbZr x Ti 1-x O3, BiFeO3, PbTiO3, BaTiO3, where 0 < x < 1; the gate dielectric layer has a needle-shaped ferroelastic domain structure inside; the thickness of the gate dielectric layer is 5 nm - 300 nm.

[0024] Furthermore, the free energy potential well curve of the gate dielectric layer under the action of an external electric field is a double potential well curve, where the potential barrier height is 1 - 60 J·cm -3 .

[0025] Preferably, the material of the gate dielectric layer is one or a combination of more than one of PbZr x Ti 1-x O3, BiFeO3, PbTiO3, where the value of X is 0.2 or 0.3 or 0.4; the potential barrier height of the free energy potential well curve of the gate dielectric layer under the action of an external electric field is 30 - 60 J·cm -3 ; the thickness of the gate dielectric layer is 50 nm - 200 nm.

[0026] The beneficial effect of adopting the above further scheme is that although ferroelastic domains are very common in ferroelectric thin films, ferroelastic domains are usually sheet-shaped or columnar, etc., and will play a role in pinning and hindering the reversal of ferroelectric domains. The needle-shaped ferroelastic domains that appear under specific stress-strain states in the present invention are different from traditional ferroelastic domains, and the energy density distribution at各处 of the needle-shaped ferroelastic domains is significantly different. Some studies have shown that high elastic energy and high electrostatic energy regions will form at the tips of the needles, which can significantly promote the nucleation process of the reversal of electric domains.

[0027] Because the formation of acicular ferroelastic domains requires stringent stress-strain conditions, the selection of substrates and buffer layers is subject to strict requirements. Only by selecting substrates and buffer layers that are well matched with the lattice parameters of ferroelectric thin films and meet the lattice mismatch range of acicular ferroelastic domains can the epitaxial conditions of the gate dielectric layer be better provided, thereby controlling the epitaxial stress and growth orientation of the gate dielectric layer, and ensuring that a high-quality ferroelectric gate dielectric layer with controllable acicular ferroelastic domain density can be grown.

[0028] Furthermore, the gate electrode is one or more of Au, Pt, and SrRuO3, and the thickness of the gate electrode is 5 to 150 nm;

[0029] Preferably, the gate electrode is Au and / or SrRuO3, and the electrode thickness is 10–60 nm.

[0030] The absolute value of the working electrical signal of the gate electrode is 0.01 to 10V, the working frequency is 50Hz to 50GHz, and the electrical signal is an alternating positive and negative signal.

[0031] Furthermore, the working electrical signal of the gate electrode is an alternating electrical pulse signal with an absolute value of 0.5 to 8V and a frequency of 1kHz to 50GHz. This electrical signal can be a sine wave, square wave, trapezoidal wave, or triangular wave, etc.

[0032] This invention also provides a method for fabricating the above-mentioned high-frequency ferroelectric negative capacitance field-effect transistor, comprising the following steps:

[0033] (1) A channel layer is deposited on the upper surface of the substrate, and then the channel layer is divided into source region, drain region and channel by photolithography.

[0034] (2) Ion implantation is performed on the source and drain regions, followed by annealing to form activated source and drain regions;

[0035] (3) Deposit a buffer layer on the channels of the channel layer;

[0036] (4) Deposit a gate dielectric layer on the deposited buffer layer;

[0037] (5) Deposit a gate electrode on the deposited gate dielectric layer, and deposit a source electrode and a drain electrode above the source region and the drain region respectively to obtain a high-frequency ferroelectric negative capacitance field-effect transistor.

[0038] Furthermore, the deposition methods used in steps (1)-(5) above are all low-temperature solid-source molecular beam epitaxy, pulsed laser physical deposition, radio frequency magnetron sputtering, or atomic layer deposition.

[0039] In this invention, the deposition methods of the channel layer, buffer layer, gate electrode, source electrode and drain electrode include, but are not limited to, the pulsed laser physical deposition or radio frequency magnetron sputtering described above, and other common practices in the industry may also be adopted.

[0040] Furthermore, the operating conditions for the pulsed laser deposition method are as follows: the vacuum degree of the sample deposition chamber is 1×10⁻⁶. -8 ~1×10 -6 Pa, deposition temperature 600–800℃, deposition oxygen pressure 50–100 mtorr, laser energy density 30–2000 mJ·cm⁻¹ -2 The laser pulse frequency is 5-10 Hz.

[0041] Preferably, the operating conditions for the pulsed laser deposition method are: a vacuum degree of 1×10⁻⁶ in the sample deposition chamber. -8 ~1×10 -7 Pa; deposition temperature: 620–700℃; deposition oxygen pressure: 60–86 mtorr; laser energy density: 100–800 mJ·cm⁻¹ -3 The laser pulse frequency is 6–8 Hz.

[0042] Furthermore, the annealing temperature in step (2) is 850–950°C, and the annealing time is 20–30 min.

[0043] The present invention also provides applications of the above-mentioned high-frequency ferroelectric negative capacitance field-effect transistor in microelectronics, military industry and aerospace.

[0044] The beneficial effects of this invention are as follows: By using a ferroelectric thin film material with a needle-like ferroelastic domain structure as the gate dielectric layer in an NC-FET, this invention utilizes the characteristic that the high energy density of the needle-like ferroelastic domains promotes domain flipping and accelerates the negative capacitance effect (referred to as the "needle-like ferroelastic domain fast negative capacitance effect") to overcome the limitation of low operating frequency of NC-FETs, enabling the device to operate normally in a high-frequency (>10MHz) environment, and further reducing hysteresis. Compared with material systems such as hafnium oxide and antiferroelectric materials that exhibit phase transitions in the negative capacitance effect, this invention also has advantages such as good stability, low power consumption, and low cost, and has good academic and application value.

[0045] This invention also provides a method for fabricating a high-frequency ferroelectric negative capacitance field-effect transistor. This method is simple to operate. By carefully designing the process parameters in methods such as pulsed laser physical deposition, and combining specific substrate and buffer layer materials, a better window for the epitaxial growth of needle-like ferroelastic domains is selected. This enables the control of the state and density of needle-like ferroelastic domains inside the gate dielectric layer, thereby fabricating a high-quality epitaxial ferroelectric gate dielectric layer with a fast negative capacitance effect and its high-frequency ferroelectric negative capacitance field-effect transistor. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1 A schematic diagram of the structure of the high-frequency ferroelectric negative capacitance field-effect transistor provided by the present invention;

[0048] Appendix Figure 1 In the diagram, the structures indicated by each number are: 1-substrate, 2-channel layer, 21-source region, 22-drain region, 211-source electrode, 221-drain electrode, 3-buffer layer, 4-gate dielectric layer, and 5-gate electrode.

[0049] Figure 2 In Embodiment 1 of the present invention, (001)-PbZr 0.2 Ti 0.8 Voltage-time domain curves of O3 thin films;

[0050] Figure 3 In Embodiment 1 of the present invention, (001)-PbZr 0.2 Ti 0.8 Transient voltage drop time of O3 thin film under different external resistors;

[0051] Figure 4 In Embodiment 1 of the present invention, (001)-PbZr 0.2 Ti 0.8 Double potential well curve of O3 thin film under 6V pulse electrical signal. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0054] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0055] Example 1

[0056] (1) Select a material with a thickness of 0.5 mm and a size of 0.25 cm. 2 A Si wafer was used as the substrate; a ZnO layer with a thickness of 20 nm was epitaxially grown on the substrate using a low-temperature solid-source molecular beam epitaxy process; the epitaxial temperature was 600℃ and the deposition rate was 0.3 μm / h.

[0057] (2) An active layer (including source region, drain region and channel) is formed on the ZnO layer using photolithography; then, an active layer is formed on the N-type ZnO layer using ion implantation. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions; The source and drain regions were activated by thermal annealing at 850℃ for 30 min to obtain the activated source and drain regions;

[0058] (3) A (001) oriented SrTiO3 buffer layer was deposited on the channel using pulsed laser deposition technology. The operating conditions for pulsed laser deposition were as follows: the sample deposition chamber was continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 50 mtorr, laser energy density 0.35 J·cm³ -2 The deposition time was 15 min and the laser pulse frequency was 8 Hz, resulting in a 12 nm thick SrTiO3 buffer layer.

[0059] (4) Using pulsed laser deposition technology, (001)-PbZr is deposited on the buffer layer. 0.2 Ti 0.8 O3 gate dielectric layer, wherein the operating conditions for pulsed laser deposition are: the sample deposition chamber is first continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 80 mtorr, laser energy density 0.6 J·cm³ -2The deposition time was 40 min, and the laser pulse frequency was 8 Hz, resulting in a 120 nm thick (001)-PbZr deposit. 0.2 Ti 0.8 O3 gate dielectric layer;

[0060] (5) Using photolithography and magnetron sputtering technology, Au electrodes with a thickness of about 40 nm are grown on the gate dielectric layer, source region and drain region respectively, and finally a high-frequency ferroelectric negative capacitance field-effect transistor is obtained.

[0061] In this embodiment, a needle-like ferroelastic domain structure (001)-PbZr is used. 0.2 Ti 0.8 The fast negative capacitance characteristic of the O3 gate dielectric layer is a key factor in achieving high-frequency applications and reducing hysteresis in transistors. Therefore, it is necessary to study the (001)-PbZr... 0.2 Ti 0.8 The transient negative capacitance and potential well curves of the O3 gate dielectric layer were tested and analyzed.

[0062] In this embodiment, the ferroelectric negative capacitance effect is used to characterize the (001)-PbZr system. 0.2 Ti 0.8 The negative capacitance effect of the O3 gate dielectric layer was tested and analyzed. The experimental results are as follows: Figure 2 , 3 As shown in Figure 4.

[0063] from Figure 2 As can be seen, the gate dielectric layer exhibits a rapid transient voltage drop under square wave pulse excitation of less than 6V (the external resistance in the RC circuit test is 800Ω at this time), with a duration of approximately 247.2ns. It is generally believed that the external resistance value delays the observation window of the transient voltage drop, and the intrinsic transient voltage drop duration changes linearly with the external resistance value. Therefore, by repeatedly changing the external resistance value in the ferroelectric negative capacitance effect characterization system and then converting it using linear resistance, the results are as follows... Figure 3 As shown, it was found that in the actual working circuit (external resistance ≈ 0Ω), the speed can be as fast as 25ns, which translates to the frequency being able to operate at up to 40MHz with low hysteresis.

[0064] from Figure 4 From this, we can see that (001)-PbZr 0.2 Ti 0.8 The O3 gate dielectric layer possesses a low potential barrier; under a pulsed voltage of 6V, only one potential barrier was experimentally observed, with an energy barrier of approximately 34.20 J·cm⁻¹. -3 .

[0065] In summary, (001)-PbZr with a needle-like ferroelastic domain structure 0.2 Ti 0.8Compared to conventional domain structure gate dielectric layers, O3 gate dielectric layers have a lower energy barrier, and more importantly, they exhibit a fast negative capacitance effect under alternating electric fields. Therefore, based on (001)-PbZr... 0.2 Ti 0.8 Ferroelectric negative capacitance field-effect transistors with an O3 gate dielectric layer have outstanding advantages such as high operating frequency, low hysteresis, low power consumption, and low cost, and their beneficial effects are significant.

[0066] Example 2

[0067] (1) Select a thickness of 1mm and a size of 1cm. 2 SiGe wafers were used as substrates; then, a SnO2 layer with a thickness of 100 nm was epitaxially grown on the substrate using a low-temperature solid-source molecular beam epitaxy process, with an epitaxial temperature of 400 °C and a deposition rate of 1 μm / h.

[0068] (2) Using photolithography, an active layer (including source region, drain region, and channel) is formed on the SnO2 layer; then, using ion implantation, an active layer is formed on the N2 layer. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions; then the source and drain regions were activated by thermal annealing at 950℃ for 20 min to obtain the activated source and drain regions;

[0069] (3) A (001) oriented PbZrO3 buffer layer was deposited on the active layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition included: the sample deposition chamber was continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 80 mtorr, laser energy density 0.3 J·cm³ -2 The deposition time was 20 min and the laser pulse frequency was 8 Hz, resulting in a 30 nm thick PbZrO3 buffer layer.

[0070] (4) Using pulsed laser deposition technology, (001)-PbZrO3 buffer layer is deposited. 0.3 Ti 0.7 O3 gate dielectric layer, wherein the operating conditions for pulsed laser deposition are: the sample deposition chamber is first continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 80 mtorr, laser energy density 0.5 J·cm³ -2 The deposition time was 60 min, and the laser pulse frequency was 8 Hz, resulting in a 140 nm thick (001)-PbZr deposit. 0.3 Ti 0.7O3 gate dielectric layer;

[0071] (5) Using photolithography and magnetron sputtering technology, 50 nm thick Pt electrodes are grown on the gate dielectric layer, source region and drain region respectively to obtain a high-frequency ferroelectric negative capacitance field-effect transistor.

[0072] The transistor of Example 2 was tested according to the test method of Example 1. The results showed that the performance of the transistor of Example 2 was basically the same as that of Example 1.

[0073] Example 3

[0074] (1) Select a thickness of 1mm and a size of 1cm. 2 A SiGe wafer was used as the substrate; a ZnO layer with a thickness of 20 nm was epitaxially grown on the substrate using pulsed laser physical deposition technology, with an epitaxial temperature of 600℃ and a deposition rate of 0.3 μm / h.

[0075] (2) Using standard photolithography, an active layer (including source region, drain region, and channel) is formed on the ZnO layer. Then, using ion implantation, an active layer is formed on the N2O layer. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions; then the source and drain regions were activated by thermal annealing at 950℃ for 20 min to obtain the activated source and drain regions;

[0076] (3) A (001) oriented PbTiO3 buffer layer was deposited on the active layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition were as follows: the sample deposition chamber was continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 690℃, deposition oxygen pressure 80 mtorr, laser energy density 0.38 J·cm³ -2 The deposition time was 20 min, the laser pulse frequency was 8 Hz, and a 25 nm thick PbTiO3 buffer layer was obtained.

[0077] (4) A (001)-BaTiO3 gate dielectric layer was deposited on a (001) oriented PbTiO3 buffer layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition were as follows: the sample deposition chamber was continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 650℃, deposition oxygen pressure 80 mtorr, laser energy density 0.4 J·cm³ -2 The deposition time was 60 min and the laser pulse frequency was 8 Hz, resulting in a 120 nm thick (001)-BaTiO3 gate dielectric layer.

[0078] (5) Using photolithography and magnetron sputtering technology, 50nm thick Pt electrodes are grown on the gate dielectric layer, source region and drain region respectively, and finally a high-frequency ferroelectric negative capacitance field-effect transistor is obtained.

[0079] The transistor of Example 3 was tested according to the test method of Example 1. The results showed that the performance of the transistor of Example 3 was basically the same as that of Example 1.

[0080] Example 4

[0081] (1) Select a material with a thickness of 0.5 mm and a size of 0.25 cm. 2 The SiGe wafer was used as the substrate; firstly, a SnO2 layer with a thickness of about 100 nm was epitaxially grown on the substrate using radio frequency magnetron sputtering technology, with an epitaxial temperature of 400℃ and a deposition rate of 1 μm / h.

[0082] (2) Using photolithography, an active layer (including source region, drain region, and channel) is formed on the SnO2 layer. Then, using ion implantation, an active layer is formed on the N2 layer. + The source and drain regions were injected with an energy of 25 keV and a dose of 10. 19 cm -3 Si + Ions; then the source and drain regions were activated by thermal annealing at 950℃ for 20 min to obtain the activated source and drain regions;

[0083] (3) A (001) oriented CoFe2O4 buffer layer was deposited on the active layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition were as follows: the sample deposition chamber was continuously evacuated to 1×10⁻⁶. -8 The deposition chamber temperature was 620℃, the deposition oxygen pressure was 60 mtorr, and the laser energy density was 0.32 J·cm⁻¹. -2 The deposition time was 20 min, the laser pulse frequency was 8 Hz, and a 10 nm thick CoFe2O4 buffer layer was obtained.

[0084] (4) A BiFeO3 gate dielectric layer was deposited on a (001) oriented CoFe2O4 buffer layer using pulsed laser deposition technology. The operating conditions for pulsed laser deposition were as follows: the sample deposition chamber was first continuously evacuated to 1×10⁻⁶. -8 Pa, deposition chamber temperature 600℃, deposition oxygen pressure 80 mtorr, laser energy density 0.45 J·cm³ -2 The deposition time was 60 min and the laser pulse frequency was 8 Hz, resulting in a 160 nm thick BiFeO3 gate dielectric layer.

[0085] (5) Using photolithography and magnetron sputtering technology, 50nm thick Pt electrodes are grown on the gate dielectric layer, source region and drain region respectively, and finally a high-frequency ferroelectric negative capacitance field-effect transistor is obtained.

[0086] The transistor of Example 4 was tested according to the test method of Example 1. The results showed that the performance of the transistor of Example 4 was basically the same as that of Example 1.

[0087] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A high-frequency ferroelectric negative capacitance field-effect transistor, characterized in that, Including substrate and channel layer; The channel layer is deposited on top of the substrate; A buffer layer is deposited above the middle position of the channel layer, a gate dielectric layer is deposited above the buffer layer, and a gate electrode is deposited above the gate dielectric layer. The channel layer includes a channel and a source region and a drain region respectively disposed on both sides of the channel; An active electrode is deposited above the source region, and a drain electrode is deposited above the drain region; The material of the substrate is one or more combinations of Si, Ge, SiGe, Ga2O3, GaAs, GaN; the buffer layer is one or more combinations of CoFe2O4, SrTiO3, PbTiO3, PbZrO3; the thickness of the buffer layer is 5 to 100 nm; the material of the gate dielectric layer is PbZr x Ti 1-x O3, BiFeO3, PbTiO3, BaTiO3, where 0 < x < 1; the gate dielectric layer has a needle-like ferroelastic domain structure inside; the thickness of the gate dielectric layer is 5 nm to 300 nm.

2. The high-frequency ferroelectric negative capacitance field-effect transistor according to claim 1, characterized in that, The channel layer is one or more combinations of SiO2, ZnO, SnO2, and GeO2; the thickness of the channel layer is 5~200 nm.

3. The high-frequency ferroelectric negative capacitance field-effect transistor according to claim 1, characterized in that, The source electrode is made of one or more combinations of Au, Pt, and SrRuO3, and the thickness of the source electrode is 5~150 nm. The drain electrode is one or more of Au, Pt, and SrRuO3, and the thickness of the drain electrode is 5~150 nm.

4. The high-frequency ferroelectric negative capacitance field-effect transistor according to claim 1, characterized in that, The gate electrode is one or more of Au, Pt, and SrRuO3, and the thickness of the gate electrode is 5~150 nm. The absolute value of the working electrical signal of the gate electrode is 0.01~10 V, the working frequency is 50 Hz~50 GHz, and the electrical signal is an alternating positive and negative signal.

5. A method for fabricating a high-frequency ferroelectric negative capacitance field-effect transistor according to any one of claims 1 to 4, characterized in that, Includes the following steps: (1) A channel layer is deposited on the upper surface of the substrate, and then the channel layer is divided into source region, drain region and channel by photolithography. (2) Ion implantation is performed on the source and drain regions, followed by annealing to form activated source and drain regions; (3) Deposit a buffer layer on the channels of the channel layer; (4) Deposit a gate dielectric layer on the deposited buffer layer; (5) Deposit a gate electrode on the deposited gate dielectric layer, and deposit a source electrode and a drain electrode above the source region and the drain region respectively to obtain a high-frequency ferroelectric negative capacitance field-effect transistor.

6. The method for fabricating a high-frequency ferroelectric negative capacitance field-effect transistor according to claim 5, characterized in that, The deposition methods used in steps (1)-(3) are all low-temperature solid-source molecular beam epitaxy, pulsed laser physical deposition, radio frequency magnetron sputtering, or atomic layer deposition.

7. The application of a high-frequency ferroelectric negative capacitance field-effect transistor as described in any one of claims 1 to 4 in microelectronics, military industry and aerospace.

Images