A bootstrap voltage recovery circuit based on typical buck under PSM mode

Abstract

The application provides a bootstrap voltage recovery circuit based on a typical BUCK PSM mode, comprising a BUCK circuit; a high-low end driving circuit for driving high-low end power tubes; a bootstrap circuit for lifting the voltage of a high potential VBOOT; a voltage dividing feedback circuit for feeding back to the bootstrap voltage recovery circuit in the case of current change of an output voltage, so as to be used as a signal for starting a current source of the bootstrap voltage recovery circuit, and the output voltage of the voltage dividing feedback circuit is controlled to change along with the change of the output voltage; and the bootstrap voltage recovery circuit uses VFB and VBOOT signals as trigger signals for starting and stopping the current source. The application uses a logic signal to control the charging principle of the current source switch to provide a 5V voltage difference between VBOOT and VSW for the normal work of the PSM mode, simplifies the circuit structure, does not need complex logic structure and logic control, has low cost, and can realize the recovery of the 5V voltage difference between VBOOT and VSW within 10-35V.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a bootstrap voltage recovery circuit based on a typical BUCK under a PSM mode. BACKGROUND

[0002] The bootstrap voltage circuit is indispensable as part of the driving of the NMOS tube in the light and heavy load high-voltage DC-DC circuit above 5V. Taking a typical BUCK circuit as an example, when the circuit is switched from the PWM mode to the PSM mode, the output voltage will suddenly increase, and the high-end power tube and the low-end power tube are all turned off at this time, and the output voltage is only discharged through the load to enter the charging threshold of the PSM mode. However, while the output voltage is discharging, the 5V voltage on the external capacitor lifted by the bootstrap circuit will also gradually decrease, and when the load is particularly light under light load, the time of the output voltage discharging will be very long, and the 5V voltage on the external capacitor lifted by the bootstrap circuit will gradually decrease to 0, resulting in that when the output voltage decreases to the charging threshold of the PSM mode, the high-end power tube cannot be turned on to charge, and the PSM mode cannot work normally. Commonly, during the discharging process of the output voltage, the low-end power tube is turned on once every interval, so that the VSW point voltage decreases, the bootstrap circuit works, and the 5V voltage difference between VBOOT and VSW is recovered once.

[0003] The above method recovers the 5V voltage difference between VBOOT and VSW once at a fixed interval, and the inductive current flows back at each time when the low-end power tube is turned on, which will have a large energy loss, and the zero-crossing detection module needs to be stopped during this period, and the logic design will be complex. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a bootstrap voltage recovery circuit based on a typical BUCK under a PSM mode. The technical problems to be solved by the application are solved through the following technical scheme:

[0005] The bootstrap voltage recovery circuit based on a typical BUCK under a PSM mode provided by the application comprises a high-low end power tube driving circuit, a bootstrap circuit, a BUCK circuit, a bootstrap voltage recovery circuit and a voltage division feedback circuit.

[0006] The high-low end power tube driving circuit is used for providing a logic voltage to the high-low power tube in the BUCK circuit to turn on and turn off the high-low power tube.

[0007] The bootstrap circuit is used for pulling up the logic voltage for driving the high power tube to be turned on by itself under the condition that the high power tube is turned on.

[0008] The bootstrap voltage recovery circuit is used to generate a recovery current according to the feedback voltage of the voltage division feedback circuit and feed back the recovery current to the logic voltage to control the high power tube to open or not generate current according to the feedback voltage of the voltage division feedback circuit to make the high power tube to be turned off with time consumption power;

[0009] The voltage division feedback circuit is used to detect whether the output voltage of the BUCK circuit is stable, and generate a feedback voltage when the fluctuation amplitude of the output voltage exceeds a threshold value;

[0010] The BUCK circuit is used to output a stable output voltage.

[0011] Optionally, the high-low end power tube driving circuit includes a high end power tube driving circuit and a low end power tube driving circuit, the BUCK circuit includes a high end power tube M H , a low end power tube M L , a power inductor L, an output capacitor C OUT , a heavy load resistor R3, a light load resistor R4, switching switches T1 and T2, the voltage division feedback circuit includes voltage division feedback resistors R1 and R2, and the bootstrap circuit is composed of a diode D1 and a capacitor C1.

[0012] In the high end power tube driving circuit, the high potential is connected to VBOOT, the low potential is connected to VSW, VSW is the intersection of the source stage of the high end power tube M H and the drain of the low end power tube M L , the output V_GH of the high end power tube driving circuit is connected to the gate V_GH of the high end power tube M H ; in the low end power tube driving circuit, the high potential is connected to VDD_5, which is a 5V voltage, the low potential is connected to GND, which is a 0 potential, and the output of the low end power tube driving circuit V_GL is connected to the gate V_GL of the low end power tube M L ; the drain of the high end power tube M H is connected to the input voltage VIN, the drain of the low end power tube is connected to VSW, and the source end is connected to the ground; the drain of the high end power tube is connected to VIN, the gate is connected to the output V_GH of the high end power tube, and the source stage is connected to VSW and the lower plate of the bootstrap circuit C1 and the left end of the power inductor; in the low end power tube driving circuit, the high potential is connected to VDD_5, which is a 5V voltage, the low potential is connected to GND, which is a 0 potential, and the output V_GL of the low end power tube driving circuit is connected to the gate of the low end power tube M L ; the source of the low end power tube M L is connected to GND;

[0013] The positive end of the diode D1 is connected to VDD_5, the other end is connected to the upper plate of the capacitor C1, the lower plate is connected to the first end of the power inductor L and the intersection VSW, and the second end of the power inductor L is connected to the output capacitor C OUTthe upper plate of the capacitor, the first end of the voltage division feedback resistor R1, the first end of the heavy load resistor R3, and the first end of the light load resistor R4; the second end of the voltage division feedback resistor R1 is connected to the first end of R2 and the input end of the bootstrap voltage recovery circuit, and the second end of R2, the second end of the switching switches T1 and T2 are connected to GND; the first end of the switching switch T1 is connected to the second end of the heavy load resistor R3, and the first end of the switching switch T2 is connected to the second end of the light load resistor R4; and the first end of the light load resistor R4 is the output end of the BUCK circuit.

[0014] Optionally,

[0015] When the overall circuit starts to start, the high voltage of the diode D1 in the bootstrap circuit is used to charge the capacitor C1, so as to raise the voltage at the VSW intersection point from 0 to 4.3V;

[0016] The high-side power tube driving circuit generates a high potential VBOOT to control the high-side power tube M H to turn on; when the high-side power tube M H turns on, the VSW at the intersection point will become VIN, and the high potential VBOOT will be raised to (VIN+5)V, thereby realizing the function of bootstrap voltage, and the power inductor L starts to charge, and the heavy load resistor R3 or the light load resistor R4 is connected to the circuit, and the output end outputs a stable output voltage V O ;

[0017] The switching switches T1 and T2 constitute a heavy-light load switching circuit, when the switching switch T1 is turned on and the switching switch T2 is turned off, the heavy load resistor R3 is connected to the circuit, and the circuit works in a heavy load PWM mode; when the switching switch T1 is turned off and the switching switch T2 is turned on, the R4 is connected to the circuit, and the circuit is switched from the heavy load PWM mode to the light load PSM mode;

[0018] In the light load PSM mode, the low-side power tube driving circuit is always in an off state; the source stage of the high-side power tube M H is turned off; and the output voltage V O of the BUCK circuit is discharged through the light load resistor R4; when the output voltage V O drops to 5V, the voltage division feedback circuit feeds back the voltage division V O that changes with the output voltage V FB to the bootstrap voltage recovery circuit, and the bootstrap voltage recovery circuit generates a current to charge the high potential VBOOT until the voltage of the high potential VBOOT is not lower than 5V, at which time the bootstrap voltage recovery circuit is closed.

[0019] Optionally, the bootstrap voltage recovery circuit comprises LDPMOS 1 transistor 1 (M1), LDPMOS transistor 2 (M2), LDPMOS transistor 3 (M3), LDPMOS transistor 4 (M4), LDPMOS transistor 5 (M5), LDPMOS transistor 6 (M6), LDNMOS transistor 7 (M7), LDNMOS transistor 8 (M8), LDNMOS transistor 9 (M9), LDNMOS transistor 10 (M 10 ), NMOS transistor 11 (M 11 ), the fifth resistor (R5), the sixth resistor (R6), the first comparator (COMP1), the second comparator (COMP2), two rising edge detection modules, one two-input AND gate and one RS flip-flop;

[0020] Wherein, the source terminals of LDPMOS 1 transistor 1 (M1), LDPMOS transistor 2 (M2) and LDPMOS transistor 3 (M3) are connected to VIN, the gate terminals of LDPMOS transistor 3 (M3) and LDPMOS transistor 6 (M6) are connected to external bias V_BIAS_P1 and V_BIAS_P2 respectively, the positive terminal of the fifth resistor (R5) is connected to input voltage (VBOOT) as the first input terminal of the voltage dividing feedback circuit, the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the sixth resistor (R6), the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the comparator COMP1, the negative terminal of COMP1 is connected to reference voltage VREF_1P2V, the output of the first comparator (COMP1) is connected to the first rising edge detection module, the output of the first rising edge detection module is connected to the S terminal of the RS flip-flop; the positive terminal of the second comparator (COMP2) is connected to reference voltage VREF_1P2V, the negative terminal is connected to feedback resistor voltage V FB in the BUCK circuit, the output of the second comparator (COMP2) is connected to the second rising edge detection module, the output of the second rising edge detection module is connected to one end of the two-input AND gate, the other end of the two-input AND gate is connected to the flag bit PWM_PSM of PWM mode and PSM mode, the output of the two-input AND gate is connected to the R terminal of the RS flip-flop, and the output of the RS flip-flop is connected to the gate of NMOS transistor 11 (M 11 ); the source terminals of LDNMOS transistor 9 (M9), LDNMOS transistor 10 (M 10 ) and NMOS transistor 11 (M 11 ) and the negative terminal of the sixth resistor (R6) are connected to GND.

[0021] Optionally, the current source circuit composed of M1-M 10 is all 40V high-voltage power transistor, M 11 is a 5V voltage-resistant transistor, and the output signal of the RS flip-flop is used as the control signal of M 11The signal of whether it is turned on, two comparators COMP1 and COMP2, two rising edge detection circuits Rise Detect, a two-input AND gate and a voltage divider feedback circuit for VBOOT composed of R5 and R6;

[0022] M 11 As a current source switch, when the gate of M11 is low, a bias current is generated and output by M1 and M4 to charge VBOOT; when M 11 When the gate of M9 and M 10 The gate of will be pulled to low level, and the current source will stop charging VBOOT;

[0023] When the PWM mode is switched to PSM, the PWM-PSM flag changes from 0 to 1, and the high-end and low-end power tubes M H 、M L All closed, V O It will rise rapidly in a short time, and the current will drop to 0 quickly. O Equipotential, VBOOT is 4.3V higher than VSW, then V O Discharge through the light load resistor R4, when V O When it drops to 5V, COMP2 flips, the RS trigger output is low, and M 11 is turned off, and the current source charges VBOOT.

[0024] Optional, M1-M 10 The current source circuit is composed of 40V high voltage power tubes, M 11 It is a 5V voltage-resistant tube, and the output signal of the RS trigger is used as the control signal of the M 11 The signal of whether it is turned on, two comparators COMP1 and COMP2, two rising edge detection circuits Rise Detect, a two-input AND gate and a voltage divider feedback circuit for VBOOT composed of R5 and R6;

[0025] In V O During the falling process, the VBOOT of the bootstrap circuit, which is 4.3V higher than VSW, will have loss and leakage. When the PSM mode V O The discharge time through the load resistor R4 is long, and the bootstrap voltage will drop to the same level as VSW and V O At the same voltage, the bootstrap circuit fails;

[0026] In the case of bootstrap circuit failure, M 11As the current source switch, when the gate of M11 is low, the bias current generated by M1, M4 is output as VBOOT charging until VBOOT is 5V higher than VSW, after the voltage value fed back by the voltage dividing circuit composed of M5, M6 rises to 1.2V, COMP1 flips, a short pulse is detected by the rising edge detection module, RS flip-flop is driven to 1, the current source circuit is closed for VBOOT charging, at this time VBOOT is 5V higher than VSW, and the high-side power tube M H is charged, so that the overall circuit can work normally in the PSM state. O is charged, so that the overall circuit can work normally in the PSM state.

[0027] The beneficial effects of the present application are:

[0028] 1. The present application provides a bootstrap voltage recovery circuit based on PSM mode under typical BUCK. After the PWM mode is converted into light load mode, V O drops to 5V, the current source is started by V FB feedback comparison to charge VBOOT, so that VBOOT and VSW are restored to 5V after the charging current source is closed, and the normal work of PSM mode is realized.

[0029] 2. The present application provides a bootstrap voltage recovery circuit based on PSM mode under typical BUCK, which uses the principle of feedback starting current source to charge VBOOT to provide 5V voltage difference of VBOOT higher than VSW for the normal work of PSM mode, simplifies the circuit structure, does not need complex logic structure, and reduces energy loss.

[0030] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0031] Figure 1 is a structural block diagram of the bootstrap voltage recovery circuit based on PSM mode under typical BUCK provided by the present application;

[0032] Figure 2 is a circuit diagram of the bootstrap voltage recovery circuit;

[0033] Figure 3 is a simulation waveform diagram of bootstrap recovery after the PWM mode is converted into PSM mode in the bootstrap voltage recovery circuit. DETAILED DESCRIPTION

[0034] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0035] As Figure 1As shown, the application provides a structure block diagram of a bootstrap voltage recovery circuit based on typical BUCK PSM mode, which comprises a high-low power tube driving circuit, a bootstrap circuit, a BUCK circuit, a bootstrap voltage recovery circuit and a voltage division feedback circuit.

[0036] The high-low power tube driving circuit is used to provide logic voltage for the high-low power tube in the BUCK circuit to open and close the high-low power tube.

[0037] The bootstrap circuit is used to pull up the logic voltage for opening the high power tube by itself when the high power tube is opened.

[0038] The bootstrap voltage recovery circuit is used to generate a recovery current according to the feedback voltage of the voltage division feedback circuit and feed back the recovery current to the logic voltage to control the opening of the high power tube, or not generate current according to the feedback voltage of the voltage division feedback circuit to make the high power tube close with the power consumption over time.

[0039] The voltage division feedback circuit is used to detect whether the output voltage of the BUCK circuit is stable, and generate a feedback voltage when the fluctuation amplitude of the output voltage exceeds a threshold value.

[0040] The BUCK circuit is used to output a stable output voltage.

[0041] The high-low power tube driving circuit comprises a high-end power tube driving circuit and a low-end power tube driving circuit, the BUCK circuit comprises a high-end power tube M H , a low-end power tube M L , a power inductor L, an output capacitor C OUT , a heavy load resistor R3, a light load resistor R4, switching switches T1 and T2, the voltage division feedback circuit comprises voltage division feedback resistors R1 and R2, and the bootstrap circuit is composed of a diode D1 and a capacitor C1.

[0042] The high-low power tube driving circuit comprises a high-end power tube driving circuit and a low-end power tube driving circuit, the BUCK circuit comprises a high-end power tube M H , a low-end power tube M L , a power inductor L, an output capacitor C OUT , a heavy load resistor R3, a light load resistor R4, switching switches T1 and T2, the voltage division feedback circuit comprises voltage division feedback resistors R1 and R2, and the bootstrap circuit is composed of a diode D1 and a capacitor C1.

[0043] In the high-end power tube driving circuit, the high potential is connected to VBOOT, and the low potential is connected to VSW, and VSW is the source level of the high-end power tube M H and the low-end power tube M Lthe output V_GH of the high-side power tube driving circuit is connected to the gate of the high-side power tube M H the high potential of the high-side power tube driving circuit is connected to VDD_5, which is 5V voltage, and the low potential is connected to GND, which is 0 potential, and the output of the high-side power tube driving circuit is connected to the gate of the high-side power tube M L the output V_GL of the low-side power tube driving circuit is connected to the gate of the low-side power tube M H the drain of the low-side power tube is connected to VSW, and the source is connected to the ground; the drain of the high-side power tube is connected to VIN, the gate is connected to the output V_GH of the high-side power tube, and the source is connected to VSW, the lower plate of the bootstrap circuit C1 and the left end of the power inductor; the high potential of the low-side power tube driving circuit is connected to VDD_5, which is 5V voltage, and the low potential is connected to GND, which is 0 potential, and the output V_GL of the low-side power tube driving circuit is connected to the gate of the low-side power tube M L the gate of the low-side power tube M L the source of the low-side power tube is connected to GND;

[0044] the positive end of the diode D1 is connected to VDD_5, the other end is connected to the upper plate of the capacitor C1, the lower plate is connected to the first end of the power inductor L and the intersection VSW, and the second end of the power inductor L is connected to the upper plate of the output capacitor C OUT the first end of the voltage dividing feedback resistor R1, the first end of the heavy load resistor R3, and the first end of the light load resistor R4; the second end of the voltage dividing feedback resistor R1 is connected to the first end of R2 and the input end of the bootstrap voltage recovery circuit, the second end of R2 and the second end of the switching switch T1 and T2 are connected to GND; the first end of the switching switch T1 is connected to the second end of the heavy load resistor R3, and the first end of T2 is connected to the second end of the light load resistor R4; the first end of the light load resistor R4 is the output end of the BUCK circuit.

[0045] When the overall circuit starts to start, the high voltage of the diode D1 in the bootstrap circuit is charged to the capacitor C1, and the voltage at the intersection VSW is raised from 0 to 4.3V;

[0046] The high-side power tube driving circuit generates a high potential VBOOT to control the high-side power tube M H to turn on; when the high-side power tube M H turns on, the intersection VSW will become VIN, the high potential VBOOT will be raised to (VIN+5)V, realizing the function of bootstrap voltage, the power inductor L starts to charge, the heavy load resistor R3 or the light load resistor R4 is connected to the circuit, and the output end outputs a stable output voltage V0;

[0047] The switching switch T1 and T2 constitute a heavy-light load switching circuit, when the switching switch T1 is turned on and the switching switch T2 is turned off, the heavy load resistor R3 is connected to the circuit, and the circuit works in a heavy load PWM mode; when the switching switch T1 is turned off and the switching switch T2 is turned on, the R4 is connected to the circuit, and the circuit is switched from the heavy load PWM mode to a light load PSM mode;

[0048] In the light load PSM mode, the low-end power tube driving circuit is always in an off state; the source stage of the high-end power tube M H is closed; the output voltage V O of the BUCK circuit is discharged through the light load resistor R4; when the output voltage V O drops to 5V, the voltage division feedback circuit feeds back the voltage division V O varying with the output voltage V FB to the bootstrap voltage recovery circuit, a current generated by the bootstrap voltage recovery circuit charges the high potential VBOOT until the voltage of the high potential VBOOT is higher than VSW and is not lower than 5V, at this time, the bootstrap voltage recovery circuit is closed for charging.

[0049] Wherein, the voltage of VIN can be 10V-35V, and a typical value 24V is taken as an example. The bootstrap circuit is composed of a diode D1 and a capacitor C1, the upper end of D1 is connected to VDD_5, the lower end is connected to VBOOT, the upper end of the capacitor C1 is connected to VBOOT, the normal conduction voltage of the diode is 0.7V, and the lower end is connected to VSW. When starting, VDD_5 will rush VBOOT to 4.3V, after the high-end power tube is turned on, VSW will become 24V, and VBOOT will be lifted to 28.3V, thereby realizing the function of bootstrap voltage.

[0050] The bootstrap voltage recovery circuit is used when the load is switched back from R3 to R4, and the high-end and low-end power tubes are both closed, V O is discharged through the load resistor R4, and when V O drops to 5V, i.e. VFB drops to 1.2V, the bootstrap voltage recovery circuit works, an internal current source charges VBOOT, and when VBOOT is charged to be 5V higher than VSW, the bootstrap voltage recovery circuit stops charging, and the PSM mode starts to work.

[0051] As an optional embodiment of the present application, referring to Figure 2 , the bootstrap voltage recovery circuit comprises an LDPMOS1 tube 1 (M1), an LDPMOS tube 2 (M2), an LDPMOS tube 3 (M3), an LDPMOS tube 4 (M4), an LDPMOS tube 5 (M5), an LDPMOS tube 6 (M6), an LDNMOS tube 7 (M7), an LDNMOS tube 8 (M8), an LDNMOS tube 9 (M9), an LDNMOS tube 10 (M 10 ), an NMOS tube 11 (M 11), a fifth resistor (R5), a sixth resistor (R6), a first comparator (COMP1), a second comparator (COMP2), two rising edge detection modules, a two-input AND gate, and an RS flip-flop;

[0052] The source terminals of LDPMOS tube 1 (M1), LDPMOS tube 2 (M2) and LDPMOS tube 3 (M3) are connected to VIN, the gate terminals of LDPMOS tube 3 (M3) and LDPMOS tube 6 (M6) are connected to external bias V_BIAS_P1 and V_BIAS_P2 respectively, the positive terminal of the fifth resistor (R5) is connected to input voltage (VBOOT) as the first input terminal of the voltage dividing feedback circuit, the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the sixth resistor (R6), the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the comparator COMP1, the negative terminal of COMP1 is connected to reference voltage VREF_1P2V, the output of the first comparator (COMP1) is connected to the first rising edge detection module, the output of the first rising edge detection module is connected to the S terminal of the RS flip-flop; the positive terminal of the second comparator (COMP2) is connected to reference voltage VREF_1P2V, the negative terminal is connected to feedback resistor voltage VFB in the BUCK circuit, the output of the second comparator (COMP2) is connected to the second rising edge detection module, the output of the second rising edge detection module is connected to one end of the two-input AND gate, the other end of the two-input AND gate is connected to the flag PWM_PSM of PWM mode and PSM mode, the output of the two-input AND gate is connected to the R terminal of the RS flip-flop, and the output of the RS flip-flop is connected to the gate terminal of NMOS tube 11 (M 11 The source terminals of LDNMOS tube 9 (M9), LDNMOS tube 10 (M 10 ) and NMOS tube 11 (M 11 ) and the negative terminal of the sixth resistor (R6) are connected to GND.

[0053] The bootstrap voltage recovery circuit includes a current source circuit composed of M1-M 10 , all of which are 40V high-voltage power tubes, M 11 is a 5V voltage-resistant tube, the output signal of the RS flip-flop is used as a signal for controlling whether M 11 is turned on or not, two comparators COMP1 and COMP2, two rising edge detection circuits Rise Detect, a two-input AND gate, and a voltage dividing circuit composed of R5 and R6 for VBOOT.

[0054] The current source circuit composed of M1-M10 is biased externally, according to the working principle of the current mirror, M 11 as a current source switch, when the gate terminal of M11 is at low level, the bias current is output by M1 and M4 to charge VBOOT; when the gate terminal of M 11 is at high level, M9 and M 10The gate of M11 will be pulled to low level, and the current source will be closed to charge VBOOT.

[0055] When the heavy load PWM mode is switched to the light load PSM, i.e. the load is switched back from R3 to R4, the PWM-PSM flag bit is changed from 0 to 1, the high-side and low-side power tubes M H , M L are all closed, V O will rise rapidly in a short time, the current will rapidly drop to 0, VSW and V O are at the same potential, VBOOT is 4.3V higher than VSW, and then V O is discharged through the load resistor R4, when V O drops to 5V, i.e. VFB drops to 1.2V, COMP2 is flipped, the RS flip-flop output is low, M 11 is closed, and the current source charges VBOOT.

[0056] In the process of V O dropping, VBOOT in the bootstrap circuit, which is 4.3V higher than VSW, will have a loss leakage, when the load is particularly light in the PSM mode, the time for V O to be discharged through the load resistor R4 will be very long, the bootstrap voltage will drop to the same voltage as VSW and V O , and the bootstrap will be invalid, when V O drops to 5V, M H cannot be opened when the gate voltage of M H is the same as VSW, and the PSM mode cannot be realized.

[0057] The present application is that, after V O drops to 5V, i.e. VFB drops to 1.2V, M 11 serves as a current source switch, when the gate of M11 is low, a bias current is generated by M1 and M4 to charge VBOOT until VBOOT is 5V higher than VSW, the voltage value fed back through the voltage divider circuit composed of M5 and M6 is raised to 1.2V, COMP1 is flipped, a short pulse is detected through the rising edge detection module, the RS flip-flop is set to 1, the current source circuit is closed to charge VBOOT, at this time, VBOOT is 5V higher than VSW, and the high-side power tube M H can be charged to V O , so that the overall circuit can work normally in the PSM state.

[0058] The present application is a bootstrap voltage recovery circuit based on the PSM mode of a typical BUCK, which can realize a voltage output of 5V lower than the input voltage within 10-35V, after the PWM mode is switched to the light load mode, V OWhen VSW drops to 5V, the current source is turned on to charge VBOOT through the feedback comparison of VFB, so that the voltage difference between VBOOT and VSW is restored to 5V, and then the charging current source is turned off to realize the normal work of the PSM mode.

[0059] The simulation experiment of the bootstrap voltage recovery circuit based on the PSM mode of the typical BUCK is carried out, and the effect is illustrated. Figure 3 , Figure 3 The simulation waveform diagram of the bootstrap voltage recovery circuit based on the PSM mode of the typical BUCK is carried out. The experimental conditions of the embodiment are that the input voltage VIN is 10V-35V, and the typical value is 24V, and the built-in period is always 1us. As shown in Figure 3 , in the embodiment, the waveform diagram of the circuit mode flag PWM-PSM, the waveform diagram of the output VO, and the waveform diagram of the voltage difference between VBOOT and VSW are intercepted, the uppermost purple waveform is the flag PWM-PSM, the middle green waveform is the output VO, and the lowermost cyan waveform is the voltage difference between VBOOT and VSW.

[0060] The bootstrap voltage recovery circuit based on the PSM mode of the typical BUCK in the embodiment can restore the voltage difference between VBOOT and VSW to 5V after the circuit enters the PSM mode. O After the voltage difference between VBOOT and VSW is restored to 5V, the current source is turned off through the feedback.

[0061] The bootstrap voltage recovery circuit based on the PSM mode of the typical BUCK comprises a high-low end driving circuit, a bootstrap circuit, a voltage division feedback circuit and a bootstrap voltage recovery circuit. The high-low end driving circuit is used for driving high-low end power tubes. The bootstrap circuit is composed of a diode D1 and a capacitor C1, and is used for lifting the voltage of VBOOT. The voltage division feedback circuit composed of R1 and R2 is used for feeding back to the bootstrap voltage recovery circuit under the condition of the current change of the output voltage, so as to serve as a signal for turning on the current source of the bootstrap voltage recovery circuit. The output voltage of the voltage division feedback circuit changes with the change of the output voltage. The bootstrap voltage recovery circuit uses VFB and VBOOT signals as trigger signals for turning on and off the current source. The bootstrap voltage recovery circuit based on the PSM mode of the typical BUCK in the embodiment uses the principle of the logic signal control current source switching charging to provide the 5V voltage difference between VBOOT and VSW for the normal work of the PSM mode, simplifies the circuit structure, does not need complex logic structure and logic control, has low cost, and can realize the 5V voltage difference recovery between VBOOT and VSW within 10-35V.

[0062] Furthermore, the terms "first", "second", etc. are used only for descriptive purposes and do not connote or imply relative importance. Thus, a feature defined with "first", "second", etc. can implicitly or explicitly include one or more of the features.

[0063] Although the present application has been described in connection with various embodiments thereof, it will be understood that other variations and modifications of the described embodiments can be made by those skilled in the art upon reading the description of the application set forth above. In the claims, the word "comprising" does not exclude other components or steps not mentioned in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0064] The above description is further to specific preferred embodiments of the present application and is not to be construed in any way as limiting the present application. Those skilled in the art who possess the benefit of the present disclosure will readily make numerous adaptations to the specific embodiments disclosed herein without departing from the essential scope of the present application.

Claims

1. A bootstrap voltage recovery circuit based on a typical BUCK PSM mode, characterized in that: include: High-end and low-end power tube drive circuit, bootstrap circuit, BUCK circuit, bootstrap voltage recovery circuit and voltage divider feedback circuit; The high-end and low-end power tube driving circuit is used to provide logic voltages for the high-end and low-end power tubes in the BUCK circuit to turn on and off the high-end and low-end power tubes; The bootstrap circuit is used to pull up the logic voltage that drives the high-power tube to turn on when the high-power tube is turned on; A bootstrap voltage recovery circuit is used to generate a recovery current according to the feedback voltage of the voltage divider feedback circuit, and feed the recovery current back to the logic voltage to control the high-power tube to turn on, or not generate current according to the feedback voltage of the voltage divider feedback circuit, so that the high-power tube consumes power over time and turns off; The voltage divider feedback circuit is used to detect whether the output voltage of the BUCK circuit is stable, and generates a feedback voltage when the output voltage fluctuation amplitude exceeds a threshold; The BUCK circuit is used to output a stable output voltage; The bootstrap voltage recovery circuit includes an LDPMOS 1 tube 1 (M1), an LDPMOS 2 (M2), an LDPMOS 3 (M3), an LDPMOS 4 (M4), an LDPMOS 5 (M5), an LDPMOS 6 (M6), an LDNMOS 7 (M7), an LDNMOS 8 (M8), an LDNMOS 9 (M9), an LDNMOS 10 (M 10 )、NMOS tube 11(M 11 ), a fifth resistor (R5), a sixth resistor (R6), a first comparator (COMP1), a second comparator (COMP2), two rising edge detection modules, a two-input AND gate and an RS flip-flop; The source terminals of LDPMOS 1 (M1), LDPMOS 2 (M2), and LDPMOS 3 (M3) are all connected to VIN, the gate terminals of LDPMOS 3 (M3) and LDPMOS 6 (M6) are respectively connected to external bias V_BIAS_P1 and V_BIAS_P2, the positive terminal of the fifth resistor (R5) is connected to the high potential VBOOT as the first input terminal of the voltage divider feedback circuit, the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the sixth resistor (R6), the negative terminal of the fifth resistor (R5) is connected to the positive terminal of the first comparator (COMP1), the negative terminal of COMP1 is connected to the reference voltage VREF_1P2V, the output of the first comparator (COMP1) is connected to the first rising edge detection module, and the output of the first rising edge detection module is connected to the S terminal of the RS trigger; the positive terminal of the second comparator (COMP2) is connected to the reference voltage VREF_1P2V, and the negative terminal is connected to the feedback resistor voltage divider V in the BUCK circuit. FB The output of the second comparator (COMP2) is connected to the second rising edge detection module, the output of the second rising edge detection module is connected to one end of the two-input AND gate, the other end of the two-input AND gate is connected to the PWM mode and PSM mode flag PWM_PSM, the output of the two-input AND gate is connected to the R end of the RS trigger, the output of the RS trigger is connected to the NMOS tube 11 (M 11 ) gate; LDNMOS tube 9 (M9), LDNMOS tube 10 (M 10 )、NMOS tube 11(M 11 ) and the negative electrode of the sixth resistor (R6) are connected to GND.

2. The bootstrap voltage recovery circuit based on the PSM mode under a typical BUCK according to claim 1, characterized in that: The high-end and low-end power tube driving circuits include a high-end power tube driving circuit and a low-end power tube driving circuit. The BUCK circuit is composed of a high-end power tube M H , low-end power tube M L , power inductor L, output capacitor C OUT , heavy-load resistor R3, light-load resistor R4, switching switches T1 and T2, the voltage divider feedback circuit includes voltage divider feedback resistors R1 and R2; the bootstrap circuit is composed of a diode D1 and a capacitor C1; Among them, the high potential in the high-end power tube drive circuit is connected to VBOOT, and the low potential is connected to VSW. VSW is the high-end power tube M H The source stage and low-end power tube M L At the intersection of the drain of the high-end power tube drive circuit, the output V_GH is connected to the high-end power tube M H The gate V_GH of the low-end power tube drive circuit is connected to the high potential of VDD_5, which is 5V voltage, and the low potential is connected to GND, which is 0 point. The output of the low-end power tube drive circuit is connected to the low-end power tube M L Gate V_GL; high-end power tube M H The drain of the high-end power tube is connected to the input voltage VIN, the drain of the low-end power tube is connected to VSW, and the source is grounded; the drain of the high-end power tube is connected to VIN, the gate is connected to the output V_GH of the high-end power tube, the source is connected to VSW and the lower plate of the bootstrap circuit C1 and the left end of the power inductor; the high potential in the low-end power tube drive circuit is connected to VDD_5, which is 5V voltage, and the low potential is connected to GND, which is 0 potential. The output V_GL of the low-end power tube drive circuit is connected to the low-end power tube M L The gate of the low-end power tube M L The source is connected to GND; The positive end of diode D1 is connected to VDD_5, and the other end is connected to the upper plate of capacitor C1. The lower plate is connected to the first end of power inductor L and the intersection VSW. The second end of power inductor L is connected to output capacitor C OUT The upper plate, the first end of the voltage divider feedback resistor R1, the first end of the heavy-load resistor R3, and the first end of the light-load resistor R4; the second end of the voltage divider feedback resistor R1 is connected to the first end of R2 and the input end of the bootstrap voltage recovery circuit, the second end of R2, the second ends of the switching switches T1 and T2 are connected to GND; the first end of the switching switch T1 is connected to the second end of the heavy-load resistor R3, and the first end of T2 is connected to the second end of the light-load resistor R4; the first end of the light-load resistor R4 is the output end of the BUCK circuit.

3. The bootstrap voltage recovery circuit based on the PSM mode under a typical BUCK according to claim 2, characterized in that: When the entire circuit starts to start, the high voltage of diode D1 in the bootstrap circuit charges capacitor C1, raising the voltage at the VSW intersection from 0 to 4.3V; The high-end power tube drive circuit generates a high potential VBOOT to control the high-end power tube M H Turn on; when the high-end power tube M H After turning on, VSW at the intersection will become VIN, and the self-high potential VBOOT will be raised to (VIN+5)V, realizing the function of bootstrap voltage. The power inductor L starts to charge, and the heavy load resistor R3 or the light load resistor R4 is connected to the circuit. The output end outputs a stable output voltage V O ; Switches T1 and T2 form a light-load and heavy-load switching circuit. When switch T1 is on and switch T2 is off, heavy-load resistor R3 is connected to the circuit, and the circuit operates in heavy-load PWM mode. When switch T1 is off and switch T2 is on, resistor R4 is connected to the circuit, and the circuit switches from heavy-load PWM mode to light-load PSM mode. In the light load PSM mode, the low-end power tube drive circuit is always in the off state; the high-end power tube M H The source stage is closed; the output voltage of the BUCK circuit V O Discharge through the light-load resistor R4; when the output voltage V O When it drops to 5V, the voltage divider feedback circuit will follow the output voltage V O Changing partial voltage V FB Feedback is sent to the bootstrap voltage recovery circuit, which generates current to charge the high potential VBOOT until the high potential VBOOT is higher than the voltage of VSW by not less than 5V. At this time, the bootstrap voltage recovery circuit turns off charging.

4. The bootstrap voltage recovery circuit based on the PSM mode under a typical BUCK according to claim 1, characterized in that: M1-M 10 The current source circuit is composed of 40V high voltage power tubes, M 11 It is a 5V voltage-resistant tube, and the output signal of the RS trigger is used as the control signal of the M 11 The signal of whether it is turned on, the first comparator (COMP1), the second comparator (COMP2), two rising edge detection circuits Rise Detect, a two-input AND gate and the voltage divider feedback circuit for VBOOT composed of R5 and R6; M 11 As a current source switch, when the gate of M11 is low, a bias current is generated and output by M1 and M4 to charge VBOOT; when M 11 When the gate of M9 and M 10 The gate of will be pulled to low level, and the current source will stop charging VBOOT; When the PWM mode is switched to PSM, the PWM-PSM flag changes from 0 to 1, and the high-end and low-end power tubes M H 、M L All closed, V O It will rise rapidly in a short time, and the current will drop to 0 quickly. O Equipotential, VBOOT is 4.3V higher than VSW, then V O Discharge through the light load resistor R4, when V O When it drops to 5V, COMP2 flips, the RS trigger output is low, and M 11 is turned off, and the current source charges VBOOT.

5. The bootstrap voltage recovery circuit based on the PSM mode under a typical BUCK according to claim 1, characterized in that: M1-M 10 The current source circuit is composed of 40V high voltage power tubes, M 11 It is a 5V voltage-resistant tube, and the output signal of the RS trigger is used as the control signal of the M 11 The signal of whether it is turned on, the first comparator (COMP1), the second comparator (COMP2), two rising edge detection circuits Rise Detect, a two-input AND gate and the voltage divider feedback circuit for VBOOT composed of R5 and R6; In V O During the falling process, the VBOOT of the bootstrap circuit, which is 4.3V higher than VSW, will have loss and leakage. When the PSM mode V O The discharge time through the load resistor R4 is long, and the bootstrap voltage will drop to the same level as VSW and V O At the same voltage, the bootstrap circuit fails; In the case of bootstrap circuit failure, M 11 As a current source switch, when the gate of M11 is at a low level, a bias current is generated and output by M1 and M4 to charge VBOOT until VBOOT is 5V higher than VSW. After the voltage value fed back by the voltage divider circuit formed by M5 and M6 rises to 1.2V, COMP1 flips over, and the rising edge detection module detects a short pulse, driving the RS trigger to set to 1, and the current source circuit is turned off to charge VBOOT. At this time, VBOOT is 5V higher than VSW, and the high-end power tube M can be turned on. H V O Charging allows the entire circuit to work normally in the PSM state.

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