Soft start control system for dual-clamp zero-voltage switching converter

Abstract

The application discloses a soft-start control system of a double-clamp zero-voltage switching converter, and belongs to the technical field of power generation, power transformation or power distribution. The system increases a third switch tube cycle-by-cycle turn-off unit in a circuit part of a third switch tube control signal generated by a control signal generation unit, and introduces a circuit unit for realizing a comparison point soft-start strategy in a circuit for detecting whether a fourth switch tube meets a soft-switching condition, so that the invention purpose of eliminating the oscillation of a converter output voltage is realized through a simple hardware circuit, and the switching frequency of the converter is reduced, and thus the excitation current amplitude during the soft start of the converter is effectively reduced.

Description

Technical Field

[0001] This invention relates to converter technology, and in particular to a soft-start control system for a dual-clamp zero-voltage switching converter, belonging to the technical field of power generation, transformation or distribution. Background Technology

[0002] The dual-clamp zero-voltage switching converter is an isolated DC / DC circuit topology. Due to its simple structure, high efficiency, primary-secondary isolation, and wide input-output range, it is widely used in power supply fields such as communications and military industries.

[0003] Figure 1 The control system of the dual-clamp zero-voltage switching converter shown includes: a main controller that generates control signals for the first to fourth switching transistors and a synchronous rectifier controller that generates control signals for the fifth switching transistor. The main controller samples the input voltage V. in Clamping capacitor C f voltage v c And the voltage v at the connection point of the third switch Q3 and the fourth switch Q4 B This generates control signals S1 to S4 for the first to fourth switching transistors, and the synchronous rectifier controller samples the drain-source voltage V of the fifth switching transistor Q5. ds The control signal S5 for the fifth switch Q5 is generated.

[0004] Since the third switch Q3 of the dual-clamp zero-voltage switching converter is controlled based on the volt-second balance detection result of the power transformer, the clamping capacitor voltage v at startup... c The low voltage causes the third switch Q3 to have a long conduction time, which can easily lead to shoot-through between the third switch Q3 and the fourth switch Q4, causing the clamping capacitor voltage v to rise. c Large fluctuations, which in turn cause the converter's output voltage v o This causes significant oscillations. Furthermore, the fourth switch Q4 only operates when the clamping capacitor voltage v... c Greater than the first reference voltage V ref1 The fourth switch, Q4, will only be switched on at a certain time. The switching on of Q4 causes a sudden change in the magnetization voltage of the power transformer in the converter, which will also cause a change in the clamping capacitor voltage v. c and output voltage v o This caused a shock.

[0005] This invention addresses the output voltage v during the startup process of a dual-clamp zero-voltage converter. o The problem of oscillation exists, and a startup control system is proposed to solve the aforementioned oscillation problem. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a soft-start control system for a dual-clamp zero-voltage switching converter. This is achieved by introducing a circuit that enables the cycle-by-cycle turn-off of the third switch and a fourth switch soft-start detection unit that implements a comparison-point-based soft-start strategy for the fourth switch into the converter's main controller circuit. This eliminates output voltage oscillations during the soft-start process of the dual-clamp zero-voltage converter and reduces the amplitude of the excitation current during soft-start, thus solving the technical problem of output voltage oscillations during the soft-start process of existing dual-clamp zero-voltage converters.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0008] The soft-start control system for a dual-clamp zero-voltage switching converter includes:

[0009] An error amplifier whose input is connected to the clamping capacitor voltage error signal and whose output is an amplified signal of the clamping capacitor voltage error.

[0010] The first switch conduction time and the third switch conduction time calculation unit has its input terminal connected to the output terminal of the error amplifier. It calculates the first switch conduction time and the third switch conduction time based on the clamping capacitor voltage, the amplified signal of the clamping capacitor voltage error, and the input voltage, and then outputs the result.

[0011] The control signal generation unit has its input terminal connected to the output terminal of the first switch turn-on time and third switch turn-on time calculation unit, the output terminal of the fourth switch soft-switching detection unit based on the comparison point soft-start strategy, and the output terminal of the periodic timer. It outputs the first switch control signal, the second switch control signal, the third switch turn-on signal, and the fourth switch control signal, which enable the converter to work sequentially in the input energy storage stage, the primary and secondary side energy transfer stage, the resonance stage, and the freewheeling stage.

[0012] The third switch transistor cycle-by-cycle turn-off unit receives the third switch transistor turn-on signal output by the control signal generation unit at its input terminal, and uses the third switch transistor turn-off signal generated according to the third switch transistor conduction time or the switch cycle start signal as the final third switch transistor turn-off signal. The third switch transistor control signal is generated according to the third switch transistor turn-on signal and the final third switch transistor turn-off signal.

[0013] The fourth switch soft-switching detection unit based on the comparison point soft-start strategy has its input terminal connected to the voltage at the connection point of the third and fourth switches. It integrates a fixed reference voltage to obtain a reference voltage that increments from 0. When the voltage at the connection point of the third and fourth switches is less than the reference voltage incremented from 0, it outputs a flag signal indicating that the fourth switch has met the zero-voltage turn-on condition.

[0014] The periodic timer has its input connected to the output of the fourth switch tube soft-switching detection unit based on the comparison point soft-start strategy, and outputs a switching cycle start signal.

[0015] Furthermore, in the soft-start control system of the dual-clamp zero-voltage switching converter, the soft-start control system also includes: a control signal mutual exclusion unit, whose input terminal is connected to the control signal of the third switch and the control signal of the fourth switch, and whose output is a fourth switch control signal that is mutually exclusive with the control signal of the third switch.

[0016] Furthermore, in the soft-start control system of the dual-clamp zero-voltage switching converter, the third switching transistor's cycle-by-cycle turn-off unit includes:

[0017] The timer's input is connected to the turn-on signal of the third switch transistor. It generates the turn-off signal of the third switch transistor based on the on-time of the third switch transistor and then outputs it.

[0018] An OR gate, one input of which is connected to the turn-off signal of the third switch, and the other input of which is connected to the start signal of the switching cycle, outputs the final turn-off signal of the third switch; and,

[0019] An RS flip-flop has its set terminal connected to the turn-on signal of the third switch, and its reset terminal connected to the output of an OR gate, outputting the control signal of the third switch.

[0020] Furthermore, in the soft-start control system of the dual-clamp zero-voltage switching converter, the soft-switching detection unit of the fourth switch transistor based on the comparison point soft-start strategy includes:

[0021] A resistor, one end of which is connected to a fixed reference voltage;

[0022] A capacitor has its positive plate connected to the other end of a resistor, and its negative plate grounded; and...

[0023] The comparator has its inverting input connected to the voltage at the junction of the third and fourth switching transistors, and its non-inverting input connected to the junction of the circuit and the negative plate of the capacitor. When the voltage at the junction of the third and fourth switching transistors is less than the reference voltage that increases from 0, it outputs a flag signal indicating that the fourth switching transistor has the zero-voltage turn-on condition.

[0024] Furthermore, in the soft-start control system of the dual-clamp zero-voltage switching converter, the control signal mutual exclusion unit is an AND gate. One input of the AND gate is connected to the inverted signal of the third switch control signal, and the other input of the AND gate is connected to the control signal of the fourth switch control signal. The output is the fourth switch control signal that is mutually exclusive with the control signal of the third switch control signal.

[0025] Furthermore, in the soft-start control system of the dual-clamp zero-voltage switching converter, the time constants of the resistor and capacitor are on the same order of magnitude as the soft-start time constant of the converter.

[0026] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0027] (1) In the main controller of the dual-clamp zero-voltage converter, the present invention adds a third switch turn-off unit in the circuit part of the control signal generation unit that generates the control signal of the third switch to the control signal of the control signal generation unit. The turn-on signal of the first switch that is not turned on at the same time as the third switch is used as one of the criteria for turning off the third switch. When the control signal generation unit outputs the third switch turn-off signal or the first switch turn-on signal arrives, the final turn-off signal of the third switch is generated, so as to achieve the purpose of turning off the third switch in cycles and avoid the problem that the low clamping capacitor voltage during soft start causes the third switch to have a long conduction time.

[0028] (2) The present invention also introduces a circuit unit for implementing the comparison point soft-start strategy in the circuit of the main controller of the dual-clamp zero-voltage converter that detects whether the fourth switch meets the soft-switching condition. This makes the reference voltage for judging whether the fourth switch meets the soft-switching condition start from 0 for soft-start. The lower comparison point voltage when the converter starts avoids the waste of demagnetizing energy and avoids the fourth switch being switched in late due to judging whether the fourth switch meets the soft-switching condition based on a fixed reference voltage. This effectively reduces the change of magnetization voltage before and after the fourth switch is switched in, and at the same time reduces the switching frequency of the converter, reduces magnetization energy, and effectively reduces the excitation current amplitude when the converter is soft-started. Without increasing the complexity of the main controller, the output voltage oscillation of the dual-clamp zero-voltage converter is eliminated through a simple hardware circuit.

[0029] (3) In order to avoid the bridge arm composed of the third switch and the fourth switch from being directly connected, the present invention can selectively add a control signal mutual exclusion unit to the cycle-by-cycle turn-off unit of the third switch, so as to achieve the purpose of the control signal of the fourth switch always being mutually exclusive with the control signal of the third switch. Attached Figure Description

[0030] Figure 1 This is a block diagram of the control system for a dual-clamp zero-voltage switching converter.

[0031] Figure 2(a) is an internal block diagram of the main controller in the prior art; Figure 2(b) is an internal block diagram of the main controller of the present invention that realizes soft start of the dual-clamp zero-voltage switching converter.

[0032] Figure 3 A typical waveform diagram of the control signal output by the control signal generation unit.

[0033] Figure 4 This is a schematic diagram illustrating the principle of detecting whether the fourth switch Q4 meets the soft-switching conditions in this invention.

[0034] Figure 5This is a waveform diagram showing the direct connection of the bridge arm composed of the third and fourth switching transistors during the startup process of a dual-clamp zero-voltage switching converter in the prior art.

[0035] Figure 6 This is a specific implementation circuit of the mutual exclusion strategy for the control signals of the third switch Q3 and the fourth switch Q4 of the present invention.

[0036] Figure 7(a) shows the circuit for the cycle-by-cycle turn-off of the third switch Q3 of the present invention, and Figure 7(b) shows the key waveform diagram for the cycle-by-cycle turn-off of the third switch Q3 of the present invention.

[0037] Figure 8 The waveforms of the control signal and clamping capacitor voltage when the fourth switch Q4 of the present invention is switched on are shown.

[0038] Figure 9 The waveform diagrams are shown before and after the fourth switch Q4 is switched on when the converter is started.

[0039] Figure 10 This is an implementation circuit for the comparison point soft-start strategy in this invention.

[0040] Figure 11 A schematic diagram showing the logic signals generated before and after the introduction of the comparison point soft-start strategy.

[0041] Figure 12(a) shows the waveform when starting up using the conventional control strategy; Figure 12(b) shows the waveform when starting up the converter after the proposed startup strategy is introduced.

[0042] Explanation of the labels in the diagram: Q1-Q5 are the first to fifth switching transistors; D1-D4 are the body diodes of the first to fourth switching transistors; C1-C4 are the parasitic capacitances of the first to fourth switching transistors; T is the power transformer; L... r For leakage sensing, C f For clamping capacitor, C o For the output capacitor, R LD The load is N1, the NOT gate is N1, the AND gate is AND1, R1 is the resistor, and C1 is the capacitor. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0044] The circuit topology of the dual-clamp zero-voltage switching converter is as follows: Figure 1 As shown, it includes: a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and a fifth switch Q5, a power transformer, and a clamping capacitor C. f Output capacitor C oThe first switch Q1 and the second switch Q2 are connected in series to form the first bridge arm, and the third switch Q3 and the fourth switch Q4 are connected in series to form the second bridge arm. The input voltage V is connected to the two ends of the first bridge arm. in The leakage inductance L of the power transformer is connected to the midpoint of the first bridge arm. r At one end, the power transformer leakage inductance L r The other end is connected to one end of the primary winding, and the other end of the primary winding is connected to the midpoint of the second bridge arm. The two ends of the second bridge arm are connected to clamping capacitor C. f The secondary winding of the power transformer, the fifth switching transistor Q5, and the output capacitor C o The series connection forms a secondary circuit, with load R LD Parallel connection to output capacitor C o Between the two stages: The body diode D1 of the first switching transistor Q1 is connected in parallel between the two stages, and the parasitic capacitance C1 of the first switching transistor is also connected between the two stages. The body diode D2 of the second switching transistor Q2 is connected in parallel between the two stages, and the parasitic capacitance C2 of the second switching transistor is also connected between the two stages. The body diode D3 of the third switching transistor Q3 is connected in parallel between the two stages, and the parasitic capacitance C3 of the third switching transistor is also connected between the two stages. The body diode D4 of the fourth switching transistor Q4 is connected in parallel between the two stages, and the parasitic capacitance C4 of the fourth switching transistor is also connected between the two stages. The body diode D5 of the fifth switching transistor Q5 is connected in parallel between the two stages, and the parasitic capacitance C5 of the fifth switching transistor is also connected between the two stages.

[0045] The converter operates in four modes within one switching cycle: input energy storage, primary-secondary energy transfer, resonant phase, and freewheeling phase. In the input energy storage phase, the first switch Q1 and the fourth switch Q4 are turned on, and the input voltage Vin is applied to the primary side of the power transformer. During this phase, the leakage inductance L... r And excitation inductance L m (i.e., the primary winding of the power transformer) stores energy; during the primary-secondary energy transfer phase, the first switch Q1 and the fourth switch Q4 are off, and the second switch Q2, the third switch Q3, and the fifth switch Q5 are on. Energy is transferred from the primary side to the secondary side of the power transformer, and the primary voltage of the power transformer is clamped by the secondary output voltage; during the resonance phase, the first switch Q1, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are off, and the second switch Q2 is on. At this time, the magnetizing inductor L... m Leakage inductance L rThe parasitic capacitances of the third switch Q3, the fourth switch Q4, and the fifth switch Q5 resonate. During the freewheeling phase, the first switch Q1, the third switch Q3, and the fifth switch Q5 are turned off, while the second switch Q2 and the fourth switch Q4 are turned on. The primary voltage of the power transformer is clamped to zero. During this phase, the primary side of the power transformer no longer transfers energy to the secondary side.

[0046] Figure 2(a) shows the internal block diagram of the main controller of the dual-clamp zero-voltage switching converter in the prior art. The main controller includes an error amplifier, a T1-T2 calculation unit, a control signal generation unit, a Q4 soft-switching detection unit, a periodic timer, a crystal oscillator, and a frequency multiplier unit. The working principles of several main functional modules are briefly introduced below to facilitate the subsequent discussion.

[0047] The T1-T2 calculation unit is used to calculate T1 and T2, where T1 is the duration of the input energy storage stage, i.e., the time when the first switch Q1 and the fourth switch Q4 are simultaneously turned on; T2 is the duration of the primary-secondary side energy transfer stage, i.e., the time when the second switch Q2 and the third switch Q3 are simultaneously turned on. The T1-T2 calculation unit has three input signals, namely the input voltage V. in The output signal v of the error amplifier err and clamping capacitor voltage v c It has two output signals, T1 and T2, and their specific expressions are as follows:

[0048]

[0049]

[0050] The control signal generation unit generates signals based on T1, T2, and S. R and S ZVS The control signals S1 to S4 for the first to fourth switching transistors are generated, where S... R S is the start signal of the switching cycle. ZVS This is a flag signal indicating whether the fourth switch Q4 has the zero-voltage turn-on condition. When S ZVS Setting it high indicates that the fourth switch Q4 has zero-voltage turn-on conditions.

[0051] Figure 3 The typical waveform of the control signal output by the control signal generation unit is given, as follows:

[0052] At time t0, S RWhen the control signal S1 of the first switch Q1 is high, the switching cycle begins, and the first switch Q1 is turned on. At time t1, S1 is low, and the first switch Q1 is turned off, t1 - t0 = T1. At time t2, the control signals S2 and S3 of the second and third switches Q2 and Q3 are high, and the second and third switches Q2 and Q3 are turned on, t2 - t1 = T. d , among which, T d This is the dead time; at time t3, S3 is set low, the third switch Q3 is turned off, t3-t2=T2; at time t4, S... ZVS Setting the signal high indicates that the fourth switch Q4 has the zero-voltage turn-on condition. At this time, the control signal S4 of the fourth switch Q4 is set high, and the fourth switch Q4 is turned on; at time t5, S R Set to high and begin the next switching cycle.

[0053] Q4 implements a soft-switching detection unit, which samples the voltage v at the connection point between the third switch Q3 and the fourth switch Q4. B and with the first reference voltage V ref1 Comparison, when v B <V ref1 S ZVS Set high, such as Figure 4 As shown.

[0054] When the above control strategy is adopted, during converter startup, due to the clamp capacitor voltage v c The voltage is relatively low. As shown in equation (2), the expression for T2 indicates that the third switch Q3 will conduct for a relatively long time. During the conduction period of the third switch Q3, the clamping capacitor voltage is equal to the voltage at the connection point between the third switch Q3 and the fourth switch Q4, i.e., v0. c =v B After the third switch Q3 is turned off, v B It began to descend slowly.

[0055] During the conduction of the second switch Q2 and the third switch Q3, the clamping capacitor C f The leakage inductance L of the transformer r To achieve resonance, during startup, the DC component of the clamping capacitor voltage builds up slowly from zero, resulting in a relatively low amplitude. The resonant component of the clamping capacitor voltage can increase the clamping capacitor voltage v. c Reduced to the first reference voltage V ref1 At this point, the fourth switch Q4 will be triggered to turn on. Simultaneously, the third and fourth switches Q3 and Q4 in the same bridge arm will be directly connected, causing the clamping capacitor to discharge rapidly to 0, resulting in a decrease in the clamping capacitor voltage V during startup. c and output voltage v oSevere oscillations. Furthermore, bridge arm shoot-through poses a risk of damaging the switching transistors. The waveforms of the control signals of the first to fourth switching transistors, the magnetizing inductor current, the leakage inductor current, the clamping capacitor voltage, the output voltage, and the error amplifier output signal under bridge arm shoot-through conditions are as follows: Figure 5 As shown. It is worth noting that during steady-state operation of the converter, the clamping capacitor voltage v... c The DC component is relatively high, and the clamping capacitor voltage v c The resonant component in the middle is small and insufficient to make the clamping capacitor voltage v c Reduced to the first reference voltage V ref1 .

[0056] To avoid the shoot-through problem between the third switch Q3 and the fourth switch Q4 during startup, and the long conduction time of the third switch during startup, this invention introduces a mutual exclusion strategy for the control signals of the third switch Q3 and the fourth switch Q4, as well as a cycle-by-cycle turn-off mechanism for the third switch. The implementation methods of these mechanisms will be described below.

[0057] Figure 6 A specific implementation of a mutual exclusion strategy for the control signals of the third switch Q3 and the fourth switch Q4 is given, including a NOT gate N1 and an AND gate And1. The control signal S3 of the third switch Q3 is connected to the input of the NOT gate N1. The output of the NOT gate N1 and the control signal S4 of the fourth switch Q4 are simultaneously connected to the input of the AND gate And1. The output S of the AND gate And1 is... 4f As the final control signal for the fourth switch Q4, its expression is:

[0058]

[0059] In addition, the control signal S4 of the fourth switch Q4 can be inverted and ANDed with the control signal S3 of the third switch Q3. The control signal after the AND operation can be used as the final control signal of the third switch.

[0060] To avoid the problem of prolonged conduction of the third switch Q3 based on volt-second balance control during startup, this invention introduces a cycle-by-cycle turn-off mechanism for the third switch Q3. The specific working principle is as follows: For a dual-clamp zero-voltage switching converter, during normal operation, excluding the dead zone and resonant phase, there are three operating modes, defined as Mode 1 to Mode 3. Mode 1 is the energy storage phase of the converter, where the first switch Q1 and the fourth switch Q4 are turned on, and the second switch Q2, the third switch Q3, and the fifth switch Q5 are turned off. Mode 2 is the primary-secondary energy transfer phase of the converter, where the first switch Q1 and the fourth switch Q4 are turned off, and the second switch Q2, the third switch Q3, and the fifth switch Q5 are turned on. Mode 3 is the freewheeling phase of the converter, where the second switch Q2 and the fourth switch Q4 are turned on, and the first switch Q1, the third switch Q3, and the fifth switch Q5 are turned off. From the above operating modes, it can be seen that there is no mode in which the first switch Q1 and the third switch Q3 are turned on simultaneously. Therefore, this invention proposes to utilize the turn-on signal of the first switch Q1, i.e., the switching cycle start signal S. R As one of the criteria for the turn-off signal of the third switch Q3, the third switch Q3 can be turned off cycle by cycle.

[0061] Figure 7(a) shows a simple implementation of the cycle-by-cycle turn-off of the third switch. An OR gate OR1 is added to the original circuit to convert the original turn-off signal S of the third switch Q3 into a single signal. 3_OFF1 and the start signal of the switching cycle S R The two inputs of OR gate OR1 are connected to the output signal S of OR gate OR1. 3_OFF This serves as the final turn-off signal for the third switch, Q3.

[0062] Figure 7(b) shows the key waveforms for the cycle-by-cycle turn-off of the third switch. From the figure, it can be seen that adding the switching cycle start signal S... R As one of the criteria for the turn-off signal of the third switch Q3, it can realize the cycle-by-cycle turn-off of the third switch Q3.

[0063] In addition to the reasons mentioned above, the timing of the fourth switch Q4's switching on may also affect the output voltage V during converter startup. o This caused a shock. Figure 8 The waveform of the clamping capacitor voltage when the fourth switch Q4 is switched on is given. When the converter starts up, the clamping capacitor voltage v is... c Start from 0. The turn-on condition for the fourth switch Q4 is: the voltage v at the connection point of the third switch Q3 and the fourth switch Q4. B From greater than the first reference voltage V ref1 Drop to the first reference voltage V ref1 The following is S ZVSThe rising delay triggers the fourth switch to turn on. And at 0-t... d_S4 During this period, due to the clamping capacitor voltage v c Always less than the first reference voltage V ref1 At this time, v B It will always be less than the first reference voltage V. ref1 At this time S ZVS In Henggao, the fourth switching transistor Q4 is always in the off state. When the clamping capacitor v... c Voltage greater than the first reference voltage V ref1 At that time, the fourth switch Q4 begins to switch according to the preset logic. For ease of description, t d_s4 Defined as the cut-in time of the fourth switch Q4.

[0064] Before the fourth switch Q4 is switched on: When the first switch Q1 is turned on, since the fourth switch Q4 is always turned off, the resonant inductor current flows through the body diode D3 of the third switch Q3 to the clamping capacitor C. f During charging, the magnetizing voltage applied across the transformer is approximately V. in -v c When the first switch Q1 is turned off, the second switch Q2, the third switch Q3, and the fifth switch Q5 are turned on, and energy is transferred from the primary side to the secondary side of the converter. At this time, the demagnetizing voltage applied across the transformer is the output voltage v of the converter. o .

[0065] After the fourth switch Q4 is switched on: When the first switch Q1 is turned on, the fourth switch Q4 is also turned on. At this time, the magnetizing voltage applied across the transformer is approximately V. in When the first switch Q1 and the fourth switch Q4 are turned off, the second switch Q2, the third switch Q3, and the fifth switch Q5 are turned on, and energy is transferred from the primary side to the secondary side of the converter. At this time, the demagnetizing voltage applied across the transformer is the output voltage v of the converter. o .

[0066] Comparing the transformer's magnetization voltage before and after the fourth switch Q4 is switched on, the voltages are respectively V. in -v c and V in When the fourth switch Q4 is switched on, the clamping capacitor voltage v c ≈V ref1 Therefore, the change in the transformer magnetization voltage before and after the fourth switch Q4 is switched on is equal to the change in the first reference voltage V. ref1 V ref1 The larger the value, the greater the change in magnetization voltage, and the easier it is to cause output voltage oscillation. Figure 9 As shown. A smaller first reference voltage V can be selected. ref1This allows the fourth switch Q4 to switch on earlier, reducing the change in magnetization voltage, but it will cause the converter's anti-interference performance to deteriorate.

[0067] To address the aforementioned issues, this invention proposes a soft-start strategy at the comparison point. When the converter starts up, the fourth switch transistor achieves the soft-switching comparison point, meaning the first reference voltage also starts soft-starting from 0. This allows the fourth switch transistor Q4 to switch in very early, effectively reducing the impact introduced when the fourth switch transistor Q4 starts switching in, without affecting the steady-state operation of the converter.

[0068] Figure 10 A circuit implementation of the soft-start strategy at the comparator point is presented. A resistor R1 and a capacitor C1 are added to the reference voltage of the original circuit. The resistor R1 and capacitor C1 are connected in series, and their connection point is connected to the positive input terminal of the comparator. The first reference voltage V... ref1 The voltage gradually increases from 0 to the comparison point voltage after passing through the integrating circuit composed of resistor R1 and capacitor C1. The comparison point voltage output by the integrating circuit is compared with vB ​​to obtain the flag signal S indicating whether the fourth switch Q4 has the zero-voltage turn-on condition. ZVS The time constants of resistor R1 and capacitor C1 are on the same order of magnitude as the soft-start time constant of the converter.

[0069] The comparison point soft-start strategy can effectively reduce the impact introduced when the fourth switch Q4 starts switching in. In addition, it has the following advantages:

[0070] 1. Avoid wasting demagnetizing energy. When the voltage at the connection point of the third switch Q3 and the fourth switch Q4 is v B When S drops to the comparison point, ZVS Set high, S ZVS The rising edge of the voltage triggers the fourth switch Q4 to turn on. The parasitic capacitance C4 of the fourth switch Q4 discharges rapidly through the channel of the fourth switch Q4, which wastes demagnetizing energy. After introducing the comparator point soft-start strategy, the comparator point voltage is low when the converter is first started, which effectively reduces the waste of demagnetizing energy.

[0071] 2. Startup frequency reduction. After introducing a soft-start strategy at the comparator point, the comparator point voltage is low when the converter first starts up. The frequency only decreases when the voltage at the connection point of the third switch Q3 and the fourth switch Q4 drops below the comparator point. B When the point voltage drops to the comparison point, S ZVS Only then will it be set higher, compared to the method of fixing the comparison point, S ZVS It will be set high later, such as Figure 11 As shown. Combining the control strategy of the dual-clamp zero-voltage converter, it can be seen that S... ZVSThe later high setting helps to reduce the switching frequency of the converter, which indirectly reduces the magnetization energy. At the same time, the longer period allows for more thorough demagnetization, making it easier for the transformer to reset during the converter startup, which can effectively reduce the amplitude of the excitation current during startup.

[0072] The internal block diagram of the main controller that implements the soft-start control strategy of the present invention is shown in Figure 2(b). A third switch turn-off unit is added to the circuit part of the control signal generation unit that generates the control signal of the third switch. A comparison point voltage generation unit is added to the soft-switching detection unit of the fourth switch. Optionally, a control signal mutual exclusion unit is connected in series after the third switch turn-off unit to avoid the bridge arm composed of the third switch and the fourth switch from being shot through.

[0073] To verify the effectiveness of the proposed startup control strategy and implementation method, a hardware experimental platform was built for verification. Figure 12(a) shows the startup waveform when using the conventional control strategy. It can be seen that there are large oscillations in the clamping capacitor voltage and the output voltage. Figure 12(b) shows the startup waveform of the converter after introducing the proposed startup strategy. The oscillations in the clamping capacitor voltage and the output voltage are completely eliminated. In addition, the frequency of the converter during startup is significantly reduced, which is beneficial for transformer reset and can effectively suppress the problem of large excitation current amplitude caused by the inability of the transformer to magnetically reset during converter startup.

[0074] In summary, the startup control strategy proposed in this invention comprises three parts: (1) a mutual exclusion strategy for the control signals of the third switch Q3 and the fourth switch Q4; (2) a cycle-by-cycle turn-off mechanism for the third switch Q3; and (3) a soft-start strategy at the comparator point. The proposed startup control strategy can effectively solve the problem of output voltage oscillation during startup of the dual-clamp zero-voltage switching converter, and can also effectively suppress the amplitude of the excitation current during startup. The proposed circuit implementation method is relatively simple and hardly increases the complexity of the system.

Claims

1. A soft-start control system for a dual-clamp zero-voltage switching converter, characterized in that, include: An error amplifier whose input is connected to the clamping capacitor voltage error signal and whose output is an amplified signal of the clamping capacitor voltage error. The first switch conduction time and the third switch conduction time calculation unit has its input terminal connected to the output terminal of the error amplifier. It calculates the first switch conduction time and the third switch conduction time based on the clamping capacitor voltage, the amplified signal of the clamping capacitor voltage error, and the input voltage, and then outputs the result. The control signal generation unit has its input terminal connected to the output terminal of the first switch turn-on time and third switch turn-on time calculation unit, the output terminal of the fourth switch soft-switching detection unit based on the comparison point soft-start strategy, and the output terminal of the periodic timer. It outputs the first switch control signal, the second switch control signal, the third switch turn-on signal, and the fourth switch control signal, which enable the converter to work sequentially in the input energy storage stage, the primary and secondary side energy transfer stage, the resonance stage, and the freewheeling stage. The third switch transistor cycle-by-cycle turn-off unit receives the third switch transistor turn-on signal output by the control signal generation unit at its input terminal, and uses the third switch transistor turn-off signal generated according to the third switch transistor conduction time or the switch cycle start signal as the final third switch transistor turn-off signal. The third switch transistor control signal is generated according to the third switch transistor turn-on signal and the final third switch transistor turn-off signal. The fourth switch soft-switching detection unit based on the comparison point soft-start strategy has its input terminal connected to the voltage at the connection point of the third and fourth switches. It integrates a fixed reference voltage to obtain a reference voltage that increments from 0. When the voltage at the connection point of the third and fourth switches is less than the incrementing reference voltage, it outputs a flag signal indicating that the fourth switch meets the zero-voltage turn-on condition. A periodic timer, whose input is connected to the output of the fourth switch tube soft-switching detection unit based on the comparison point soft-start strategy, outputs a switching cycle start signal.

2. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 1, characterized in that, The soft-start control system also includes: The control signal mutual exclusion unit has its input terminal connected to the control signals of the third and fourth switching transistors, and its output terminal is the control signal of the fourth switching transistor that is mutually exclusive with the control signal of the third switching transistor.

3. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 1 or 2, characterized in that, The third switching transistor cycle-by-cycle turn-off unit includes: The timer's input is connected to the turn-on signal of the third switch transistor. It generates the turn-off signal of the third switch transistor based on the on-time of the third switch transistor and then outputs it. An OR gate, one input of which is connected to the turn-off signal of the third switch, and the other input of which is connected to the start signal of the switching cycle, outputs the final turn-off signal of the third switch; and, An RS flip-flop has its set terminal connected to the turn-on signal of the third switch, and its reset terminal connected to the output of an OR gate, outputting the control signal of the third switch.

4. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 1 or 2, characterized in that, The fourth switch soft-switching detection unit based on the comparison point soft-start strategy includes: A resistor, one end of which is connected to a fixed reference voltage; A capacitor has its positive plate connected to the other end of a resistor, and its negative plate grounded; and... The comparator has its inverting input connected to the voltage at the junction of the third and fourth switching transistors, and its non-inverting input connected to the junction of the circuit and the negative plate of the capacitor. When the voltage at the junction of the third and fourth switching transistors is less than the reference voltage that increases from 0, it outputs a flag signal indicating that the fourth switching transistor has zero-voltage turn-on condition.

5. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 2, characterized in that, The control signal mutual exclusion unit is an AND gate. One input of the AND gate is connected to the inverted signal of the third switch control signal, and the other input of the AND gate is connected to the fourth switch control signal. The output is a fourth switch control signal that is mutually exclusive with the third switch control signal.

6. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 1, characterized in that, The expression for calculating the conduction time of the first switching transistor is: Where T1 is the on-time of the first switch, k is the proportional coefficient, and v err This is the amplified signal of the clamping capacitor voltage error, V in This is the input voltage.

7. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 1, characterized in that, The expression for calculating the conduction time of the third switch is: Where T2 is the on-time of the third switch, T1 is the on-time of the first switch, and V in The input voltage, v c This is the clamping capacitor voltage.

8. The soft-start control system for the dual-clamp zero-voltage switching converter according to claim 4, characterized in that, The time constants of the resistors and capacitors are on the same order of magnitude as the soft-start time constant of the converter.

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