Signal generation circuit

Abstract

The present application provides a signal generating circuit, including a trigger circuit, a selection circuit and an output circuit. The trigger circuit receives a target clock signal and generates a first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives a coding signal of a mode register, generates a first selection signal and a second selection signal, and the coding signal corresponds to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first selection signal and the second selection signal, and the effective level length of the target command signal corresponds to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and target command signals with different effective level lengths control the ODT to open at different times, thereby effectively controlling the opening time of the ODT.

Description

Technical Field

[0001] The present application relates to the field of semiconductor memory technology, and in particular to a signal generating circuit. Background Art

[0002] ODT (On Die Termination) is a function set in DRAM technology to reduce terminal signal reflection. When writing data, in order to achieve impedance matching of the input signal and ensure the quality of the input signal, the DRAM will turn on ODT after receiving the write control signal. The time point of turning on ODT will directly affect the quality of the DRAM write signal.

[0003] Therefore, how to effectively control the time of opening ODT is a more important issue. Summary of the invention

[0004] The present application provides a signal generating circuit, which generates a target command signal corresponding to an effective level length according to a burst length, and effectively controls an ODT opening time.

[0005] In a first aspect, the present application provides a signal generating circuit, comprising:

[0006] a trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal;

[0007] A selection circuit is configured to receive a coding signal of a mode register and generate a corresponding first selection signal and a second selection signal, wherein the coding signal corresponds to different burst length modes;

[0008] The output circuit is configured to receive the first command signal and generate a target command signal in response to the received first selection signal and the second selection signal, wherein the effective level length of the target command signal corresponds to the burst length mode.

[0009] In some embodiments, the trigger circuit includes: N cascaded triggers;

[0010] The clock input of each level of the trigger receives the target clock signal, the trigger input of the first level of the trigger receives the initial command signal, the positive phase output of the previous level of the trigger is connected to the trigger input of the next level of the trigger, and the positive phase output of each level of the trigger outputs the first command signal.

[0011] In some embodiments, the output circuit includes a first SR latch, the S input terminal of the first SR latch is connected to the positive phase output terminal of the first stage trigger, the R input terminal is connected to the positive phase output terminal of the Nth stage trigger, and the Q output terminal outputs the target command signal.

[0012] In some embodiments, the output circuit further includes a first selector and a second selector;

[0013] The control end of the first selector receives a first selection signal, the first input end of the first selector is connected to the positive phase output end of the trigger of the second stage, and the second input end of the first selector is connected to the positive phase output end of the trigger of the N-1th stage;

[0014] The control end of the second selector receives a second selection signal, the first input end of the second selector is connected to the positive phase output end of the second stage trigger, the second input end of the second selector is connected to the positive phase output end of the Mth stage trigger, <M<N-1。

[0015] In some embodiments, the output circuit includes: a first output circuit, configured to receive the first command signal and the first sub-command signal, and generate an intermediate command signal, wherein the effective level length of the intermediate command signal is twice that of the first command signal, and the first sub-command signal is obtained by delaying the first command signal by one cycle of a target clock signal.

[0016] In some embodiments, the output circuit further includes: a second output circuit configured to receive the intermediate command signal and generate a second command signal in response to the first selection signal and / or the second selection signal;

[0017] If the received first selection signal or the second selection signal is valid, the second command signal is an inverted signal of the intermediate command signal.

[0018] In some embodiments, the output circuit further includes: a third output circuit configured to receive the second command signal and generate a target command signal;

[0019] In some embodiments, the first output circuit includes a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate;

[0020] The first input end of the first NAND gate is connected to the positive phase output end of the first stage trigger, the second input end of the first NAND gate is connected to the positive phase output end of the second stage trigger, and the output end of the first NAND gate outputs the first intermediate command signal;

[0021] The first input terminal of the second NAND gate is connected to the positive phase output terminal of the third stage trigger, the second input terminal of the second NAND gate is connected to the positive phase output terminal of the fourth stage trigger, and the output terminal of the second NAND gate outputs the second intermediate command signal;

[0022] The first input terminal of the third NAND gate is connected to the positive phase output terminal of the fifth stage trigger, the second input terminal of the third NAND gate is connected to the positive phase output terminal of the sixth stage trigger, and the output terminal of the third NAND gate outputs the third intermediate command signal;

[0023] The first input terminal of the fourth NAND gate is connected to the positive phase output terminal of the seventh stage trigger, the second input terminal of the fourth NAND gate is connected to the positive phase output terminal of the eighth stage trigger, and the output terminal of the fourth NAND gate outputs a fourth intermediate command signal.

[0024] In some embodiments, the second output circuit includes a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate;

[0025] The first input terminal and the second input terminal of the fifth NAND gate are connected to the output terminal of the first NAND gate, and the output terminal of the fifth NAND gate outputs a fifth intermediate command signal, which is an inverted signal of the first intermediate command signal;

[0026] The first input terminal of the sixth NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the sixth NAND gate receives the first selection signal, and the output terminal of the sixth NAND gate outputs a sixth intermediate command signal. If the first selection signal is valid, the sixth intermediate command signal is an inverted signal of the second intermediate command signal;

[0027] The first input end of the seventh NAND gate is connected to the output end of the third NAND gate, the second input end of the seventh NAND gate receives the second selection signal, and the output end of the seventh NAND gate outputs a seventh intermediate command signal. If the second selection signal is valid, the seventh intermediate command signal is an inverted signal of the third intermediate command signal;

[0028] The first input end of the eighth NAND gate is connected to the output end of the fourth NAND gate, the second input end of the eighth NAND gate receives the second selection signal, and the output end of the eighth NAND gate outputs an eighth intermediate command signal. If the second selection signal is valid, the eighth intermediate command signal is an inverted signal of the fourth intermediate command signal.

[0029] In some embodiments, the third output circuit includes a ninth NAND gate, a tenth NAND gate, and a first NOR gate;

[0030] The first input terminal of the ninth NAND gate is connected to the output terminal of the fifth NAND gate, the second input terminal of the ninth NAND gate is connected to the output terminal of the sixth NAND gate, and the output terminal of the ninth NAND gate outputs a ninth intermediate command signal;

[0031] The first input terminal of the tenth NAND gate is connected to the output terminal of the seventh NAND gate, the second input terminal of the tenth NAND gate is connected to the output terminal of the eighth NAND gate, and the output terminal of the tenth NAND gate outputs a tenth intermediate command signal;

[0032] The first input end of the first NOR gate is connected to the output end of the ninth NAND gate, the second input end of the first NOR gate is connected to the output end of the tenth NAND gate, and the output end of the first NOR gate outputs the target command signal.

[0033] In some embodiments, the trigger circuit includes a first trigger, a clock input terminal of the first trigger receives a target clock signal, a trigger input terminal of the first trigger receives an initial command signal, and a positive phase output terminal of the first trigger outputs the first command signal.

[0034] In some embodiments, the output circuit includes: a second trigger, a third trigger, and a fourth trigger;

[0035] The clock input terminal of the second trigger receives the first command signal, the trigger input terminal of the second trigger is connected to the negative phase output terminal, and the positive phase output terminal of the second trigger outputs the first sub-target command signal;

[0036] The clock input terminal of the third trigger is connected to the positive phase output terminal of the second trigger, the trigger input terminal of the third trigger is connected to the negative phase output terminal, the control terminal of the third trigger receives the first selection signal, and the positive phase output terminal of the third trigger outputs the second sub-target command signal;

[0037] The clock input terminal of the fourth trigger is connected to the positive phase output terminal of the third trigger, the trigger input terminal of the fourth trigger is connected to the negative phase output terminal, the control terminal of the fourth trigger receives the second selection signal, and the positive phase output terminal of the fourth trigger outputs the third sub-target command signal;

[0038] If the first selection signal is invalid, the second selection signal is invalid, the first sub-target command signal is output as the target command signal;

[0039] If the first selection signal is valid and the second selection signal is invalid, the second sub-target command signal is output as the target command signal;

[0040] If the first selection signal is valid and the second selection signal is valid, the third sub-target command signal is output as the target command signal.

[0041] In some embodiments, the invention further includes a gating circuit configured to receive an initial clock signal and generate a target clock signal corresponding to the first gating signal in response to the received first gating signal.

[0042] In some embodiments, the gating circuit includes an eleventh NAND gate, a first input terminal of the eleventh NAND gate receives an initial clock signal, and a second input terminal receives a first gating signal. If the first gating signal is valid, the target clock signal is triggered.

[0043] The signal generating circuit provided in the present application includes a trigger circuit, a selection circuit and an output circuit. The trigger circuit receives a target clock signal and generates a first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives a coding signal of a mode register, generates a first selection signal and a second selection signal, and the coding signal corresponds to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first selection signal and the second selection signal, and the effective level length of the target command signal corresponds to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and target command signals with different effective level lengths control the ODT to open at different times, thereby effectively controlling the opening time of the ODT. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A circuit diagram of a signal generating circuit provided in an embodiment of the present application;

[0046] Figure 2 A circuit diagram of a signal generating circuit provided in an embodiment of the present application;

[0047] Figure 3 A timing diagram of a signal generating circuit provided in an embodiment of the present application;

[0048] Figure 4 A circuit diagram of another signal generating circuit provided in an embodiment of the present application;

[0049] Figure 5 A timing diagram of a signal generating circuit provided in an embodiment of the present application;

[0050] Figure 6 A circuit diagram of another signal generating circuit provided in an embodiment of the present application;

[0051] Figure 7 A circuit diagram of a gate control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims above.

[0054] Figure 1 A circuit diagram of a signal generating circuit provided in an embodiment of the present application. Figure 1 As shown, the signal generating circuit provided by the embodiment of the present application includes a trigger circuit 101, a selection circuit 102 and an output circuit 103. The trigger circuit 101 is configured to receive a target clock signal CLK, and in response to the received initial command signal CMD, generates a first command signal CMD1 corresponding to the initial command signal CMD. The selection circuit 102 is configured to receive the encoding signal of the mode register, generate a first selection signal SEL0 and a second selection signal SEL1, and the encoding signal corresponds to different burst length modes. The output circuit 103 is configured to receive the first command signal CMD1, and in response to the received first selection signal SEL0 and the second selection signal SEL1, generate a target command signal ODT CMD, and the effective level length of the target command signal ODT CMD corresponds to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths according to different burst length modes, and the target command signals with different effective level lengths control the ODT opening time differently, effectively control the opening time of the ODT, and save power. For example, when the burst length corresponding to the burst length mode is smaller, the effective level length of the target command signal is smaller, and the ODT opening time is controlled to be shorter; when the burst length corresponding to the burst length mode is larger, the effective level length of the target command signal is larger, and the ODT opening time is controlled to be longer.

[0055] In practical applications, the clock input terminal of the trigger circuit 101 receives the target clock signal CLK, the trigger input terminal of the trigger circuit 101 receives the initial command signal CMD, and the output terminal of the trigger circuit 101 outputs the first command signal CMD1 corresponding to the initial command signal CMD. The first command signal CMD1 can be understood as a delayed signal of the initial command signal CMD, which is valid in different clock cycles from the initial command signal CMD.

[0056] The trigger circuit 101 may include N cascaded triggers, where N is a positive integer greater than 1. The clock input terminal of the trigger of each stage receives the target clock signal CLK. The trigger input terminal of the first stage trigger serves as the trigger input terminal of the trigger circuit 101 to receive the initial command signal CMD. The positive phase output terminal of the trigger of the previous stage is connected to the trigger input terminal of the trigger of the next stage. The positive phase output terminal of the trigger of each stage outputs the first command signal CMD1. Different delay signals of the initial command signal CMD can be generated according to the number of triggers, so that the first command signal CMD1 is valid in different target clock cycles.

[0057] For example, refer to Figure 2 As shown, the trigger circuit 101 may include nine triggers, which are respectively recorded as the first-level trigger 1011, the second-level trigger 1012, the third-level trigger 1013, the fourth-level trigger 1014, the fifth-level trigger 1015, the sixth-level trigger 1016, the seventh-level trigger 1017, the eighth-level trigger 1018 and the ninth-level trigger 1019.

[0058] The clock input terminal of the first-stage flip-flop 1011 serves as the clock input terminal of the trigger circuit 101, and receives the target clock signal CLK. The trigger input terminal of the first-stage flip-flop 1011 serves as the trigger input terminal of the trigger circuit 101, and receives the initial command signal CMD. The positive phase output terminal of the first-stage flip-flop 1011 is connected to the trigger input terminal of the second-stage flip-flop 1012, and the positive phase output terminal of the first-stage flip-flop 1011 outputs the first command signal Q1. The clock input terminal of the second-stage flip-flop 1012 receives the target clock signal CLK, the positive phase output terminal of the second-stage flip-flop 1012 is connected to the trigger input terminal of the third-stage flip-flop 1013, and the positive phase output terminal of the second-stage flip-flop 1012 outputs the first command signal Q2. The clock input terminal of the third-stage flip-flop 1013 receives the target clock signal CLK, the positive phase output terminal of the third-stage flip-flop 1013 is connected to the trigger input terminal of the fourth-stage flip-flop 1014, and the positive phase output terminal of the third-stage flip-flop 1013 outputs the first command signal Q3. The clock input terminal of the fourth-stage flip-flop 1014 receives the target clock signal CLK, the positive phase output terminal of the fourth-stage flip-flop 1014 is connected to the trigger input terminal of the fifth-stage flip-flop 1015, and the positive phase output terminal of the fourth-stage flip-flop 1014 outputs the first command signal Q4. The clock input terminal of the fifth-stage flip-flop 1015 receives the target clock signal CLK, the positive phase output terminal of the fifth-stage flip-flop 1015 is connected to the trigger input terminal of the sixth-stage flip-flop 1016, and the positive phase output terminal of the fifth-stage flip-flop 1015 outputs the first command signal Q5. The clock input terminal of the sixth-stage flip-flop 1016 receives the target clock signal CLK, the positive phase output terminal of the sixth-stage flip-flop 1016 is connected to the trigger input terminal of the seventh-stage flip-flop 1017, and the positive phase output terminal of the sixth-stage flip-flop 1016 outputs the first command signal Q6. The clock input of the seventh-stage trigger 1017 receives the target clock signal CLK, the positive phase output of the seventh-stage trigger 1017 is connected to the trigger input of the eighth-stage trigger 1018, and the positive phase output of the seventh-stage trigger 1017 outputs the first command signal Q7. The clock input of the eighth-stage trigger 1018 receives the target clock signal CLK, the positive phase output of the eighth-stage trigger 1018 is connected to the trigger input of the ninth-stage trigger 1019, and the positive phase output of the eighth-stage trigger 1018 outputs the first command signal Q8. The clock input of the ninth-stage trigger 1019 receives the target clock signal CLK, and the positive phase output of the ninth-stage trigger 1019 outputs the first command signal Q9. The number of triggers in the trigger circuit 101 is determined according to the specific situation and is not limited here. In practical applications, the clock inputs of the second-stage trigger 1012 to the ninth-stage trigger 1019 can all be connected to the clock input of the first-stage trigger 1011 to receive the target clock signal CLK.

[0059] Figure 5 The timing diagram of the signal generating circuit provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, when the initial command signal CMD is valid in the first clock cycle CLK1, the first command signal Q1 output by the first-level trigger 1011 is valid in the second clock cycle CLK2, the first command signal Q2 output by the second-level trigger 1012 is valid in the third clock cycle CLK3, the first command signal Q3 output by the third-level trigger 1013 is valid in the fourth clock cycle CLK4, the first command signal Q4 output by the fourth-level trigger 1014 is valid in the fifth clock cycle CLK5, the first command signal Q5 output by the fifth-level trigger 1015 is valid in the sixth clock cycle CLK6, the first command signal Q6 output by the sixth-level trigger 1016 is valid in the seventh clock cycle CLK7, the first command signal Q7 output by the seventh-level trigger 1017 is valid in the eighth clock cycle CLK8, and the first command signal Q8 output by the eighth-level trigger 1018 is valid in the ninth clock cycle CLK9.

[0060] The selection circuit 102 may generate a first selection signal SEL0 and a second selection signal SEL1 upon receiving a coding signal of a mode register. The coding signals correspond to different burst length modes, and the burst length modes may include a first burst length mode BL8, a second burst length mode BL16, and a third burst length mode BL32. When the coding information of the mode register is 01, it corresponds to the first burst length mode BL8. When the coding signal of the mode register is 00, it corresponds to the second burst length mode BL16. When the coding signal of the mode register is 1X (X represents no care), it corresponds to the third burst length mode BL32.

[0061] In some embodiments, reference Figure 2 As shown, the output circuit 103 includes a first SR latch 104, an S input terminal of the first SR latch 104 is connected to the positive phase output terminal of the first-stage flip-flop 1011, an R input terminal of the first SR latch 104 is connected to the positive phase output terminal of the N-th stage flip-flop, and a Q output terminal of the first SR latch 104 outputs a target command signal ODT CMD, thereby controlling the delay period of the initial command signal CMD by the number of flip-flops connected to the first SR latch 104 to generate a target command signal ODT CMD corresponding to the burst length mode.

[0062] For example, the S input terminal of the first SR latch 104 is connected to the positive phase output terminal of the first-stage flip-flop 1011, the R input terminal of the first SR latch 104 is connected to the positive phase output terminal of the third-stage flip-flop 1013, the first command signal Q1 output by the first-stage flip-flop 1011 is valid (low level is valid) in the second clock cycle CLK2, the first command signal Q3 output by the third-stage flip-flop 1013 is valid (low level is valid) in the fourth clock cycle CLK4, and the target command signal ODT CMD output by the Q output terminal of the first SR latch 104 is valid (high level is valid) in the second clock cycle CLK2 to the fourth clock cycle CLK4, that is, it is valid in three clock cycles 3CLK.

[0063] In this embodiment, reference Figure 2 As shown, the output circuit 103 may further include a first NOT gate 105, the input end of the first NOT gate 105 is connected to the Q output end of the first SR latch 104, receives the target command signal ODT CMD, and outputs an inverted signal of the target command signal ODT CMD. Then, when the target command signal ODT CMD output by the first SR latch 104 is valid (high level is valid) within the second clock cycle CLK2 to the fourth clock cycle CLK4, the inverted signal of the target command signal ODT CMD output by the first NOT gate 105 is also valid (low level is valid) within the second clock cycle CLK2 to the fourth clock cycle CLK4.

[0064] In this embodiment, reference Figure 2 As shown, the output circuit 103 may further include a first selector 106 and a second selector 107, the control end of the first selector 106 receives the first selection signal SEL0, the first input end of the first selector 106 is connected to the positive phase output end of the second-stage trigger 1012, the second input end of the first selector 106 is connected to the positive phase output end of the trigger of the N-1th stage, the control end of the second selector 106 receives the second selection signal SEL1, the first input end of the second selector 107 is connected to the positive phase output end of the second-stage trigger 1012, the second input end of the second selector 107 is connected to the positive phase output end of the trigger of the Mth stage, and M is a positive integer greater than 2 and less than N-1. The first selector 106 and the second selector 107 can control the number of triggers used in the trigger circuit 101 under the control of the first selection signal SEL0 and the second selection signal SEL1, thereby adjusting the delay period of the initial command signal CMD to generate the target command signal ODT CMD corresponding to the burst length mode.

[0065] Specifically, when the first selection signal SEL0 received by the first selector 106 is a high-level signal, the first selector 106 can connect the positive phase output terminal of the second-stage trigger 1012 and the trigger input terminal of the N-th stage trigger; when the first selection signal SEL0 received by the first selector 106 is a low-level signal, the first selector 106 can connect the positive phase output terminal of the N-1-th stage trigger and the trigger input terminal of the N-th stage trigger. Similarly, when the second selection signal SEL1 received by the second selector 107 is a high-level signal, the second selector 107 can connect the positive phase output terminal of the second-stage trigger 1012 and the trigger input terminal of the M+1-th stage; when the second selection signal SEL1 received by the second selector 107 is a low-level signal, the second selector 107 can connect the positive phase output terminal of the M-th stage trigger and the trigger input terminal of the M+1-th stage trigger.

[0066] For example, refer to Figure 2 As shown, N is 9, then when the first selection signal SEL0 received by the first selector 106 is a high level signal, the first selector 106 can connect the positive phase output terminal of the second-stage flip-flop 1012 and the trigger input terminal of the ninth-stage flip-flop 1019, and when the first selection signal SEL1 received by the first selector 106 is a low level signal, the first selector 106 can connect the positive phase output terminal of the eighth-stage flip-flop 1018 and the trigger input terminal of the ninth-stage flip-flop 1019. M is 6, when the second selection signal SEL1 received by the second selector 107 is a high level signal, the second selector 107 can connect the positive phase output terminal of the second-stage flip-flop 1012 and the trigger input terminal of the seventh-stage flip-flop 1017, and when the second selection signal SEL1 received by the second selector 107 is a low level signal, the second selector 107 can connect the positive phase output terminal of the sixth-stage flip-flop 1016 and the trigger input terminal of the seventh-stage flip-flop 1017.

[0067] Corresponding to different burst length modes, when the selection circuit receives the coding information corresponding to the first burst length mode BL8, the generated first selection signal SEL0 is a high level signal, and the first output circuit generates the target command signal ODT_CMD with an effective level length of two CLK clock cycles. When the selection circuit receives the coding information corresponding to the second burst length mode BL16, the generated first selection signal SEL0 is a low level signal, the second selection signal SEL1 is a high level signal, and the first output circuit generates the target command signal ODT_CMD with an effective level length of four CLK clock cycles. When the selection circuit receives the coding information corresponding to the third burst length mode BL32, the generated first selection signal SEL0 is a low level signal, the second selection signal SEL1 is a low level signal, and the first output circuit generates the target command signal ODT_CMD with an effective level length of 8 clock cycles.

[0068] In the third burst length mode BL32, according to the DRAM industry standard, the trigger circuit will receive two consecutive CMD commands, separated by 8 clock cycles. CMD_delay is the output signal of the positive phase output terminal of the first-stage trigger, which is delayed by T1 time compared with the received initial command signal. CMD_shift is the output signal of the positive phase output terminal of the eighth-stage trigger, which is delayed by T2+8CLK time compared with the received initial command signal. The second initial command signal sent adjacently is delayed by 8CLK time compared with the first initial command signal, that is, the second initial command signal will not have a corresponding target command signal output. Figure 3 shown.

[0069] In other embodiments, reference Figure 4 As shown, the output circuit 103 includes a first output circuit 110, and the first output circuit 110 is configured to receive a first command signal CMD1 and a first sub-command signal, and generate an intermediate command signal. The effective level length of the intermediate command is twice that of the first command signal CMD1, and the first sub-command signal is obtained by delaying the first command signal CMD1 by one cycle of the target clock signal CLK.

[0070] In this embodiment, reference Figure 4 As shown, the first output circuit 110 includes a first NAND gate 111, a second NAND gate 112, a third NAND gate 113 and a fourth NAND gate 114. The first input terminal of the first NAND gate 111 receives the first command signal, the second input terminal of the first NAND gate 111 receives the first sub-command signal, and the output terminal of the first NAND gate 111 outputs the first intermediate command signal CMD11. For example, the first input terminal of the first NAND gate 111 is connected to the positive phase output terminal of the first-stage trigger 1011, the second input terminal of the first NAND gate 111 is connected to the positive phase output terminal of the second-stage trigger 1012, and the output terminal of the first NAND gate 111 outputs the first intermediate command signal CMD11. It can be understood that the first command signal Q2 output by the second-stage trigger 1012 can be used as the first sub-command signal. Reference Figure 5 As shown, when the first command signal Q1 output by the first-stage trigger 1011 is valid in the second clock cycle CLK2, and the first command signal Q2 output by the second-stage trigger 1012 is valid in the third clock cycle CLK3, the first intermediate command signal CMD11 is valid in the second clock cycle CLK2 and the third clock cycle CLK3 (the first intermediate command signal CMD11 is valid at a high level), that is, it is valid in two clock cycles 2CLK.

[0071] The first input terminal of the second NAND gate 112 can receive the first command signal, the second input terminal of the second NAND gate 112 can receive the first sub-command signal, and the output terminal of the second NAND gate 112 outputs the second intermediate command signal CMD12. For example, the first input terminal of the second NAND gate 112 is connected to the positive phase output terminal of the third-stage flip-flop 1013, the second input terminal of the second NAND gate 112 is connected to the positive phase output terminal of the fourth-stage flip-flop 1014, and the output terminal of the second NAND gate 112 outputs the second intermediate command signal CMD12. The first command signal Q4 output by the fourth-stage flip-flop 1014 can be used as the first sub-command signal. Figure 5 As shown, when the first command signal Q3 output by the third-stage trigger 1013 is valid within the fourth clock cycle CLK4, and the first command signal Q4 output by the fourth-stage trigger 1014 is valid within the fifth clock cycle CLK5, the second intermediate command signal CMD12 is valid within the fourth clock cycle CLK4 and the fifth clock cycle CLK5 (the second intermediate command signal CMD12 is valid at a high level), that is, it is valid within two clock cycles 2CLK.

[0072] The first input terminal of the third NAND gate 113 receives the first command signal, the second input terminal of the third NAND gate 113 receives the first sub-command signal, and the output terminal of the third NAND gate 113 outputs the third intermediate command signal CMD13. For example, the first input terminal of the third NAND gate 113 is connected to the positive phase output terminal of the fifth-stage flip-flop 1015, the second input terminal of the third NAND gate 113 is connected to the positive phase output terminal of the sixth-stage flip-flop 1016, and the output terminal of the third NAND gate 113 outputs the third intermediate command signal CMD13. The first command signal Q6 output by the sixth-stage flip-flop 1016 can be used as the first sub-command signal. Figure 5 As shown, when the first command signal Q5 output by the fifth-stage trigger 1015 is valid within the sixth clock cycle CLK6, and the first command signal Q6 output by the sixth-stage trigger 1016 is valid within the seventh clock cycle CLK7, the third intermediate command signal CMD13 is valid within the sixth clock cycle CLK6 and the seventh clock cycle CLK7 (the third intermediate command signal CMD13 is valid at a high level), that is, it is valid within two clock cycles 2CLK.

[0073] The first input terminal of the fourth NAND gate 114 receives the first command signal, the second input terminal of the fourth NAND gate 114 receives the first sub-command signal, and the output terminal of the fourth NAND gate 114 outputs the fourth intermediate command signal CMD14. For example, the first input terminal of the fourth NAND gate 114 is connected to the positive phase output terminal of the seventh-stage flip-flop 1017, the second input terminal of the fourth NAND gate 114 is connected to the positive phase output terminal of the eighth-stage flip-flop 1018, and the output terminal of the fourth NAND gate 114 outputs the fourth intermediate command signal CMD14. The first command signal Q8 output by the eighth-stage flip-flop 1018 can be used as the first sub-command signal. When the first command signal Q7 output by the seventh-level trigger 1017 is valid in the eighth clock cycle CLK8 and the first command signal Q8 output by the eighth-level trigger 1018 is valid in the ninth clock cycle CLK9, the fourth intermediate command signal CMD14 is valid in the eighth clock cycle CLK8 and the ninth clock cycle CLK9 (the fourth intermediate command signal CMD14 is valid at a high level), that is, it is valid in two clock cycles 2CLK.

[0074] In some embodiments, the output circuit 103 may further include a second output circuit 120, which is configured to receive an intermediate command signal and generate a second command signal in response to the first selection signal and / or the second selection signal. If the received first selection signal or the second selection signal is valid, the second command signal is an inverted signal of the intermediate command signal.

[0075] In this embodiment, reference Figure 4 As shown, the second output circuit 120 includes a fifth NAND gate 121, a sixth NAND gate 122, a seventh NAND gate 123 and an eighth NAND gate 124. The first input terminal and the second input terminal of the fifth NAND gate 121 are connected to the output terminal of the first NAND gate 111, and the output terminal of the fifth NAND gate 121 outputs the fifth intermediate command signal ODT CMD11, which is an inverted signal of the first intermediate command signal CMD11. Figure 5 As shown, the fifth intermediate command signal ODT CMD11 is valid in the second clock cycle CLK2 and the third clock cycle CLK3 (the fifth intermediate command signal ODT CMD11 is valid at a low level).

[0076] The first input terminal of the sixth NAND gate 122 is connected to the output terminal of the second NAND gate 112, the second input terminal of the sixth NAND gate 122 receives the first selection signal SEL0, and the output terminal of the sixth NAND gate 122 outputs the sixth intermediate command signal ODTCMD12. If the first selection signal is valid, the sixth intermediate command signal ODT CMD12 is the inverted signal CMD12 of the second intermediate command signal. Figure 5As shown, the sixth intermediate command signal ODT CMD12 is valid during the fourth clock cycle CLK4 and the fifth clock cycle CLK5 (the sixth intermediate command signal ODT CMD12 is valid at a low level).

[0077] The first input terminal of the seventh NAND gate 123 is connected to the output terminal of the third NAND gate 113, the second input terminal of the seventh NAND gate 123 receives the second selection signal SEL1, and the output terminal of the seventh NAND gate 123 outputs the seventh intermediate command signal ODTCMD13. If the second selection signal is valid, the seventh intermediate command signal ODT CMD13 is an inverted signal of the third intermediate command signal CMD13. Figure 5 As shown, the seventh intermediate command signal ODT CMD13 is valid during the sixth clock cycle CLK6 and the seventh clock cycle CLK7 (the seventh intermediate command signal ODT CMD13 is valid at a low level).

[0078] The first input terminal of the eighth NAND gate 124 is connected to the output terminal of the fourth NAND gate 114, the second input terminal of the eighth NAND gate 124 receives the second selection signal SEL1, and the output terminal of the eighth NAND gate 124 outputs the eighth intermediate command signal ODTCMD14. If the second selection signal is valid, the eighth intermediate command signal ODT CMD14 is an inverted signal of the fourth intermediate command signal CMD14. Figure 5 As shown, the eighth intermediate command signal ODT CMD14 is valid during the eighth clock cycle CLK8 and the ninth clock cycle CLK9 (the eighth intermediate command signal ODT CMD14 is valid at a low level).

[0079] In some embodiments, reference Figure 4 As shown, the output circuit 103 may further include a third output circuit 130 , and the third output circuit 130 is configured to receive the second command signal and generate a target command signal ODT CMD.

[0080] In this embodiment, the third output circuit 130 includes a ninth NAND gate 131, a tenth NAND gate 132 and a first NOR gate 133. A first input terminal of the ninth NAND gate 131 is connected to the output terminal of the fifth NAND gate 121, a second input terminal of the ninth NAND gate 131 is connected to the output terminal of the sixth NAND gate 122, and the output terminal of the ninth NAND gate 131 outputs the ninth intermediate command signal CMD21. A first input terminal of the tenth NAND gate 132 is connected to the output terminal of the seventh NAND gate 123, a second input terminal of the tenth NAND gate 132 is connected to the output terminal of the eighth NAND gate 124, and the output terminal of the tenth NAND gate 132 outputs the tenth intermediate command signal CMD22. A first input terminal of the first NOR gate 133 is connected to the output terminal of the ninth NAND gate 131, a second input terminal of the first NOR gate 133 is connected to the output terminal of the tenth NAND gate 132, and the output terminal of the first NOR gate 133 outputs the target command signal ODT CMD. Reference Figure 5 As shown, the ninth intermediate command signal CMD21 is valid from the second clock cycle CLK2 to the fifth clock cycle CLK5 (the ninth intermediate command signal CMD21 is valid at a high level), that is, valid within four clock cycles 4CLK. The tenth intermediate command signal CMD22 is valid from the sixth clock cycle CLK6 to the ninth clock cycle CLK9 (the tenth intermediate command signal ODTCMD22 is valid at a high level), that is, valid within four clock cycles 4CLK. The target command signal ODT CMD3 output by the first NOR gate 133 is valid from the second clock cycle CLK2 to the ninth clock cycle CLK9 (the target command signal ODT CMD3 corresponding to the third burst length mode is valid at a low level), that is, valid within eight clock cycles 8CLK.

[0081] Therefore, combined with Figure 4 and Figure 5As shown, when the first selection signal and the second selection signal received by the second output circuit 120 are invalid, the target command signal output by the third output circuit 130 is the target command signal corresponding to the first burst length mode BL8, which is also the fifth intermediate command signal ODT CMD11, which is valid in the second clock cycle CLK2 and the third clock cycle CLK3. When the first selection signal received by the second output circuit 120 is valid and the second selection signal is invalid, the target command signal output by the third output circuit 130 is the target command signal corresponding to the second burst length mode BL16, which is also the inverted signal ODT CMD21 of the ninth intermediate command signal CMD21, which is valid in the second clock cycle CLK2 to the fifth clock cycle CLK5. When both the first selection signal and the second selection signal received by the second output circuit 120 are valid, the target command signal output by the third output circuit 130 is the target command signal corresponding to the third burst length mode BL32, that is, ODT CMD3, which is valid in the second clock cycle CLK2 to the ninth clock cycle CLK9.

[0082] In other embodiments, the trigger circuit 101 may include a first trigger, a clock input terminal of the first trigger serving as a clock input terminal of the trigger circuit 101 to receive a target clock signal CLK, a trigger input terminal of the first trigger serving as a trigger input terminal of the trigger circuit 101 to receive an initial command signal CMD, and a positive phase output terminal of the first trigger serving as an output terminal of the trigger circuit 101 to output a first command signal CMD1.

[0083] The output circuit 103 can be configured to output the first sub-target command signal as the target command signal if the first selection signal is invalid and the second selection signal is invalid; output the second sub-target command signal as the target command signal if the first selection signal is valid and the second selection signal is invalid; and output the third sub-target command signal as the target command signal if the first selection signal is valid and the second selection signal is valid.

[0084] refer to Figure 6As shown, the output circuit 103 may include a second flip-flop 1022, a third flip-flop 1023, and a fourth flip-flop 1024. The clock input terminal of the second flip-flop 1022 receives the first command signal CMD1, the trigger input terminal of the second flip-flop 1022 is connected to the negative phase output terminal, and the positive phase output terminal of the second flip-flop 1022 outputs the first sub-target command signal Out1. The clock input terminal of the third flip-flop 1023 is connected to the positive phase output terminal of the second flip-flop 1022, the trigger input terminal of the third flip-flop 1023 is connected to the negative phase output terminal, the control terminal of the third flip-flop 1023 receives the first selection signal, and the positive phase output terminal of the third flip-flop 1023 outputs the second sub-target command signal Out2. The clock input terminal of the fourth flip-flop 1024 is connected to the positive phase output terminal of the third flip-flop 1023, the trigger input terminal of the fourth flip-flop 1024 is connected to the negative phase output terminal, the control terminal of the fourth flip-flop 1024 receives the second selection signal, and the positive phase output terminal of the fourth flip-flop 1024 outputs the third sub-target command signal Out3. The first sub-target command signal Out1 is the target command signal corresponding to the first burst length mode BL8, the second sub-target command signal Out2 is the target command signal corresponding to the second burst length mode BL16, and the third sub-target command signal Out3 is the target command signal corresponding to the third burst length mode BL32, thereby generating target command signals corresponding to different burst length modes.

[0085] In some embodiments, reference Figure 7 As shown, the output circuit may further include a gating circuit 201, which may be configured to receive the initial clock signal CLK0, and in response to the received first gating signal CLK_Gating, generate a target clock signal corresponding to the first gating signal CLK_Gating. The gating circuit 201 can generate a target clock signal CLK according to the first gating signal CLK_Gating and the initial clock signal CLK0, and the target clock signal CLK will output the initial clock signal CLK0 only when the first gating signal CLK_Gating is valid, thereby achieving power saving.

[0086] In this embodiment, reference Figure 6 As shown, the gating circuit 201 may include an eleventh NAND gate 202 and a second NAND gate 203. The first input terminal of the eleventh NAND gate 202 receives the initial clock signal CLK0, and the second input terminal of the eleventh NAND gate 202 receives the first gating signal CLK_Gating. If the first gating signal CLK_Gating is valid, it triggers the output of the intermediate clock signal. The input terminal of the second NAND gate 203 is connected to the output terminal of the eleventh NAND gate 202, receives the intermediate clock signal, and outputs the target clock signal CLK.

[0087] The signal generating circuit provided in the embodiment of the present application is described in detail above. The trigger circuit in the signal generating circuit receives the target clock signal and generates a first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives the encoding signal of the mode register to generate a first selection signal and a second selection signal, and the encoding signal corresponds to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first selection signal and the second selection signal, and the effective level length of the target command signal corresponds to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and target command signals with different effective level lengths control the ODT to open at different times, thereby effectively controlling the opening time of the ODT.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal generating circuit, characterized in that: include: a trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal; A selection circuit is configured to receive a coding signal of a mode register and generate a first selection signal and a second selection signal, wherein the coding signal corresponds to different burst length modes; an output circuit configured to receive the first command signal and generate a target command signal in response to the received first selection signal and the second selection signal, wherein the effective level length of the target command signal corresponds to the burst length mode; Wherein, the trigger circuit comprises: N cascaded triggers; The clock input terminal of each stage of the trigger receives the target clock signal, the trigger input terminal of the first stage of the trigger receives the initial command signal, the positive phase output terminal of the previous stage of the trigger is connected to the trigger input terminal of the next stage of the trigger, and the positive phase output terminal of each stage of the trigger outputs the first command signal; The output circuit includes: a first output circuit configured to receive the first command signal and a first sub-command signal, generate an intermediate command signal, the effective level length of the intermediate command signal is twice that of the first command signal, and the first sub-command signal is obtained by delaying the first command signal by a period of a target clock signal; The output circuit further includes: a second output circuit configured to receive the intermediate command signal and generate a second command signal in response to the first selection signal and / or the second selection signal; If the received first selection signal or the second selection signal is valid, the second command signal is an inverted signal of the intermediate command signal.

2. The signal generating circuit according to claim 1, characterized in that: The output circuit further includes: a third output circuit configured to receive the second command signal and generate a target command signal.

3. The signal generating circuit according to claim 2, characterized in that: The first output circuit includes a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate; The first input end of the first NAND gate is connected to the positive phase output end of the first stage trigger, the second input end of the first NAND gate is connected to the positive phase output end of the second stage trigger, and the output end of the first NAND gate outputs the first intermediate command signal; The first input terminal of the second NAND gate is connected to the positive phase output terminal of the third stage trigger, the second input terminal of the second NAND gate is connected to the positive phase output terminal of the fourth stage trigger, and the output terminal of the second NAND gate outputs the second intermediate command signal; The first input terminal of the third NAND gate is connected to the positive phase output terminal of the fifth stage trigger, the second input terminal of the third NAND gate is connected to the positive phase output terminal of the sixth stage trigger, and the output terminal of the third NAND gate outputs the third intermediate command signal; The first input terminal of the fourth NAND gate is connected to the positive phase output terminal of the seventh stage trigger, the second input terminal of the fourth NAND gate is connected to the positive phase output terminal of the eighth stage trigger, and the output terminal of the fourth NAND gate outputs a fourth intermediate command signal.

4. The signal generating circuit according to claim 3, characterized in that: The second output circuit includes a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; The first input terminal and the second input terminal of the fifth NAND gate are connected to the output terminal of the first NAND gate, and the output terminal of the fifth NAND gate outputs a fifth intermediate command signal, which is an inverted signal of the first intermediate command signal; The first input terminal of the sixth NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the sixth NAND gate receives the first selection signal, and the output terminal of the sixth NAND gate outputs a sixth intermediate command signal. If the first selection signal is valid, the sixth intermediate command signal is an inverted signal of the second intermediate command signal; The first input end of the seventh NAND gate is connected to the output end of the third NAND gate, the second input end of the seventh NAND gate receives the second selection signal, and the output end of the seventh NAND gate outputs a seventh intermediate command signal. If the second selection signal is valid, the seventh intermediate command signal is an inverted signal of the third intermediate command signal; The first input end of the eighth NAND gate is connected to the output end of the fourth NAND gate, the second input end of the eighth NAND gate receives the second selection signal, and the output end of the eighth NAND gate outputs an eighth intermediate command signal. If the second selection signal is valid, the eighth intermediate command signal is an inverted signal of the fourth intermediate command signal.

5. The signal generating circuit according to claim 4, characterized in that: The third output circuit includes a ninth NAND gate, a tenth NAND gate, and a first NOR gate; The first input terminal of the ninth NAND gate is connected to the output terminal of the fifth NAND gate, the second input terminal of the ninth NAND gate is connected to the output terminal of the sixth NAND gate, and the output terminal of the ninth NAND gate outputs a ninth intermediate command signal; The first input terminal of the tenth NAND gate is connected to the output terminal of the seventh NAND gate, the second input terminal of the tenth NAND gate is connected to the output terminal of the eighth NAND gate, and the output terminal of the tenth NAND gate outputs a tenth intermediate command signal; The first input end of the first NOR gate is connected to the output end of the ninth NAND gate, the second input end of the first NOR gate is connected to the output end of the tenth NAND gate, and the output end of the first NOR gate outputs the target command signal.

6. The signal generating circuit according to claim 1, characterized in that: The invention also includes a gating circuit configured to receive an initial clock signal and generate a target clock signal corresponding to the first gating signal in response to the received first gating signal.

7. The signal generating circuit according to claim 6, characterized in that: The gating circuit includes an eleventh NAND gate, a first input terminal of the eleventh NAND gate receives an initial clock signal, and a second input terminal receives a first gating signal. If the first gating signal is valid, the target clock signal is triggered to be output.

8. A signal generating circuit, characterized in that: include: a trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal; A selection circuit is configured to receive a coding signal of a mode register and generate a first selection signal and a second selection signal, wherein the coding signal corresponds to different burst length modes; an output circuit configured to receive the first command signal and generate a target command signal in response to the received first selection signal and the second selection signal, wherein the effective level length of the target command signal corresponds to the burst length mode; Wherein, the trigger circuit comprises: N cascaded triggers; The clock input terminal of each stage of the trigger receives the target clock signal, the trigger input terminal of the first stage of the trigger receives the initial command signal, the positive phase output terminal of the previous stage of the trigger is connected to the trigger input terminal of the next stage of the trigger, and the positive phase output terminal of each stage of the trigger outputs the first command signal; The output circuit includes a first SR latch, a first selector and a second selector, the S input terminal of the first SR latch is connected to the positive phase output terminal of the first stage trigger, the R input terminal is connected to the positive phase output terminal of the Nth stage trigger, and the Q output terminal outputs the target command signal; The control end of the first selector receives a first selection signal, the first input end of the first selector is connected to the positive phase output end of the trigger of the second stage, and the second input end of the first selector is connected to the positive phase output end of the trigger of the N-1th stage; The control end of the second selector receives a second selection signal, the first input end of the second selector is connected to the positive phase output end of the second stage trigger, the second input end of the second selector is connected to the positive phase output end of the Mth stage trigger, <M<N-1。 9. A signal generating circuit, characterized in that: include: a trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal; A selection circuit is configured to receive a coding signal of a mode register and generate a first selection signal and a second selection signal, wherein the coding signal corresponds to different burst length modes; an output circuit configured to receive the first command signal and generate a target command signal in response to the received first selection signal and the second selection signal, wherein the effective level length of the target command signal corresponds to the burst length mode; The trigger circuit includes a first trigger, a clock input terminal of the first trigger receives a target clock signal, a trigger input terminal of the first trigger receives an initial command signal, and a positive phase output terminal of the first trigger outputs the first command signal; The output circuit comprises: a second trigger, a third trigger, and a fourth trigger; The clock input terminal of the second trigger receives the first command signal, the trigger input terminal of the second trigger is connected to the negative phase output terminal, and the positive phase output terminal of the second trigger outputs the first sub-target command signal; The clock input terminal of the third trigger is connected to the positive phase output terminal of the second trigger, the trigger input terminal of the third trigger is connected to the negative phase output terminal, the control terminal of the third trigger receives the first selection signal, and the positive phase output terminal of the third trigger outputs the second sub-target command signal; The clock input terminal of the fourth trigger is connected to the positive phase output terminal of the third trigger, the trigger input terminal of the fourth trigger is connected to the negative phase output terminal, the control terminal of the fourth trigger receives the second selection signal, and the positive phase output terminal of the fourth trigger outputs the third sub-target command signal; If the first selection signal is invalid, the second selection signal is invalid, the first sub-target command signal is output as the target command signal; If the first selection signal is valid and the second selection signal is invalid, the second sub-target command signal is output as the target command signal; If the first selection signal is valid and the second selection signal is valid, the third sub-target command signal is output as the target command signal.

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