A high isolation on-chip transceiver switch

Abstract

This invention proposes a high-isolation on-chip transceiver switch, comprising a primary coupling line, a first-stage coupling line, and a second-stage coupling line, a matching capacitor, a first transistor and a second transistor, a first gate bias resistor and a second gate bias resistor, a first substrate bias resistor and a second substrate bias resistor, a first control voltage and a second control voltage, a first resistor, a second resistor, a third resistor, and a fourth resistor, and a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. When the first control voltage is a positive power supply voltage and the second control voltage is a negative power supply voltage, port one and port two are connected, and port one and port three are turned off, and vice versa. This invention designs a coupling cancellation structure, using capacitors and resistors to construct a signal cancellation path to cancel the coupling signals between secondary stages. This invention significantly improves the isolation between port two and port three while maintaining a small area of ​​the coupled-line transceiver switch, solving the key problem of low isolation in coupled-line transceiver switches.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-isolation on-chip transceiver switch. Background Technology

[0002] Benefiting from advancements in silicon-based technology, silicon holds immense potential in terahertz communication and imaging systems. For time-division duplex systems, the transceiver switch is a crucial module, used to switch between transmit and receive modes and share a single antenna array to achieve bidirectional signal paths, thereby reducing system area. With the development and application of these systems, higher demands are being placed on the performance of the transceiver switch, such as its integration density, insertion loss, isolation, and linearity.

[0003] Currently, integrated on-chip transceiver switch topologies mainly fall into two categories: one is based on various circuit structures using quarter-wavelength transmission lines; the other is based on coupled-line structures. While quarter-wavelength line switches offer excellent performance and are relatively mature, they occupy a large chip area. Coupled-line transceiver switches, although offering a significant area advantage, suffer from lower isolation due to unavoidable coupling between secondary windings. Even by increasing transistor size and sacrificing insertion loss to improve isolation, the upper limit of isolation for coupled-line switches remains limited. Summary of the Invention

[0004] Technical problem: To address the issue of low isolation in the aforementioned coupled-line transceiver switches, a high-isolation on-chip transceiver switch is proposed, which significantly improves isolation without introducing large insertion losses.

[0005] Technical Solution: To solve the above problems, this invention proposes a high-isolation on-chip transceiver switch. The switch includes an input module, an output module, and a coupling cancellation module. The input module includes a primary coupling line and a matching capacitor. The matching capacitor is connected in parallel with the primary coupling line, with one end of the parallel connection connected to port 1 and the other end grounded. Mutual inductance is formed between the input module and the output module through the coupling line.

[0006] The output module includes a first-stage coupling line, a second-stage coupling line, a first transistor, and a second transistor. The two ends of the first-stage coupling line are connected to port two and the source and drain of the first transistor. The gate of the first transistor is connected to a first gate bias resistor, and the substrate is connected to a first substrate bias resistor. The other ends of the first gate bias resistor and the first substrate bias resistor are connected together and connected to a first control voltage. The two ends of the second-stage coupling line are connected to port three and the source and drain of the second transistor. The gate of the second transistor is connected to a second gate bias resistor, and the substrate is connected to a second substrate bias resistor. The other ends of the second gate bias resistor and the second substrate bias resistor are connected together and connected to a second control voltage.

[0007] The coupling cancellation module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is connected in parallel with the first resistor, the second capacitor is connected in parallel with the second resistor, the inner end of the parallel connection of the first capacitor and the first resistor is connected to the drain of the first transistor, the inner end of the parallel connection of the second capacitor and the second resistor is connected to the drain of the second transistor, and the outer end of the parallel connection of the first capacitor and the first resistor is connected to the outer end of the parallel connection of the second capacitor and the second resistor.

[0008] The third capacitor and the third resistor are connected in parallel, the fourth capacitor and the fourth resistor are connected in parallel, the inner terminal of the third capacitor and the third resistor connected in parallel is connected to the source of the first transistor, the inner terminal of the fourth capacitor and the fourth resistor connected in parallel is connected to the source of the second transistor, and the outer terminal of the third capacitor and the third resistor connected in parallel is connected to the outer terminal of the fourth capacitor and the fourth resistor connected in parallel.

[0009] The primary coupling line, the first-level coupling line, and the second-level coupling line are all implemented using metal lines of integrated circuit technology, and are the coupling structure of the top layer metal. Other connection lines are connected using the second-to-top layer metal.

[0010] The first transistor and the second transistor are identical. The gate length is determined by the manufacturing process. The maximum gate width is selected so that the insertion loss of the transistor is not higher than 0.3dB, and the minimum gate width is selected so that the isolation of the transistor is not less than 7dB.

[0011] The first gate bias resistor, the second gate bias resistor, the first substrate bias resistor, and the second substrate bias resistor are the same, with resistance values ​​between 6K ohms and 20K ohms.

[0012] The first control voltage and the second control voltage are selected between a positive power supply voltage and a negative power supply voltage.

[0013] The first, second, third, and fourth resistors are identical, as are the first, second, third, and fourth capacitors. The resistors and capacitors adjust the amplitude and phase of the coupling cancellation path signal, canceling the coupling signal between secondary windings, so that the switching isolation is greater than 50dB.

[0014] The first-stage coupling line and the second-stage coupling line are the same, and the spacing between them is the same as that between them and the primary coupling line. The matching capacitor is used. The length, width, and spacing of the primary coupling line, the first-stage coupling line, and the second-stage coupling line are not fixed, so that the switch return loss is higher than 15dB.

[0015] For the circuit described above, when the first control voltage is a negative power supply voltage and the second control voltage is a positive power supply voltage, port 1 and port 2 are connected, and port 1 and port 3 are disconnected; when the first control voltage is a positive power supply voltage and the second control voltage is a negative power supply voltage, port 1 and port 2 are disconnected, and port 1 and port 3 are connected.

[0016] Beneficial effects: Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0017] The advantages of this invention lie in providing a novel high-isolation on-chip transceiver switch. On one hand, using a coupled-line transceiver switch structure effectively reduces the chip area; on the other hand, introducing a coupling cancellation path effectively improves the isolation between port two and port three. When the switch is operating normally, if signals from port one to port two are conducting, the signal coupled from port two to isolated port three cancels out the signal transmitted from port two to port three via the coupling cancellation path, achieving high isolation. Compared to traditional coupled-line switches that increase transistor size to achieve limited isolation and incur significant additional insertion loss, this solution can sacrifice some insertion loss to achieve ideal complete isolation. This invention solves the problems of low isolation between low-noise amplifiers (LNAs) and power amplifiers (PAs), and the large chip area of ​​traditional on-chip RF switches. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of the high isolation on-chip transceiver switch in this invention;

[0019] Figure 2 This is a schematic diagram of the traditional coupling line structure and coupling cancellation module connection of the high isolation on-chip transceiver switch in this invention;

[0020] Figure 3 This invention provides a comparison of insertion loss performance between a high-isolation on-chip transceiver switch and an uncoupled cancellation path.

[0021] Figure 4 This invention presents a comparison of the isolation performance of a high-isolation on-chip transceiver switch and an uncoupled cancellation path.

[0022] Figure 1 The following components are present: primary coupling line L1, first stage coupling line L2, second stage coupling line L3, matching capacitor Cp, first transistor M1, second transistor M2, first gate bias resistor Rg1, second gate bias resistor Rg2, first substrate bias resistor Rb1, second substrate bias resistor Rb2, first control voltage Vc1, second control voltage Vc2, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first capacitor C1, second capacitor C2, third capacitor C3, and fourth capacitor C4. Detailed Implementation

[0023] The present invention will be further explained below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0024] This invention proposes a high-isolation on-chip transceiver switch, which includes an input module, an isolation enhancement module, and an output module. The input module includes a primary coupling line L1 and a matching capacitor Cp. One end of the matching capacitor Cp is connected to port P1 and one end of the primary coupling line L1, while the other end of the matching capacitor Cp is grounded, and the other end of the primary coupling line L1 is grounded. The input module and the output module form mutual inductance through the coupling line.

[0025] The output module includes a first-stage coupling line L2, a second-stage coupling line L3, a first transistor M1, and a second transistor M2. The first-stage coupling line L2 is connected at both ends to port P2 and the source and drain of the first transistor M1. The gate of the first transistor M1 is connected to a first gate bias resistor Rg1, and its substrate is connected to a first substrate bias resistor Rb1. The other ends of the first gate bias resistor Rg1 and the first substrate bias resistor Rb1 are connected to a first control voltage Vc1. The second-stage coupling line L3 is connected at both ends to port P3 and the source and drain of the second transistor M2. The gate of the second transistor M2 is connected to a second gate bias resistor Rg2, and its substrate is connected to a second substrate bias resistor Rb2. The other ends of the second gate bias resistor Rg2 and the second substrate bias resistor Rb2 are connected to a second control voltage Vc2.

[0026] The coupling cancellation module consists of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. One end of the first capacitor C1 is connected to one end of the first resistor R1, and simultaneously to one end of the second capacitor C2 and the second resistor R2. The other end of the first capacitor C1 is connected to the drain of the first transistor. The other end of the second capacitor C2 and the second resistor R2 is connected to the drain of the second transistor. One end of the third capacitor C3 is connected to one end of the third resistor R3, and simultaneously to one end of the fourth capacitor C4 and the fourth resistor R4. The other end of the fourth capacitor C4 and the fourth resistor R4 is connected to the source of the first transistor. The other end of the fourth capacitor C4 and the fourth resistor R4 is connected to the source of the second transistor.

[0027] When the first control voltage Vc1 is a negative power supply voltage (-VDD) and the second control voltage Vc2 is a positive power supply voltage (VDD), ports P1 and P2 are connected, while ports P1 and P3 are disconnected. Transistor M1 operates in the off state, and transistor M2 operates in the on state. At this time, the primary coupling line L1 and the matching capacitor Cp, the primary coupling line L2 and the off-state transistor M1 together form a coupled resonant cavity, realizing signal transmission from port P1 to port P2. The on-state transistor M2 forms a short circuit, turning off port P3. Port P2 couples the signal to port P3 on one hand, and on the other hand, adjusts the signal amplitude and phase through the parallel path of the capacitor and resistor, canceling the coupled signal at port P3, forming a high-isolation transceiver switch. Conversely, when the first control voltage Vc1 is a positive power supply voltage (VDD) and the second control voltage Vc2 is a negative power supply voltage (-VDD), ports P1 and P3 are connected, while ports P1 and P2 are disconnected.

[0028] Based on the above working principle, this embodiment designs and simulates the above circuit using 40nm CMOS technology, verifying the practicality of the present invention.

[0029] like Figure 2 The diagram shows the traditional coupling line structure and coupling cancellation module connection in the aforementioned high-isolation on-chip transceiver switch. Matching capacitor Cp, transistors M1 and M2 are not shown. The network area is 0.105mm × 0.075mm = 0.007875mm². 2 .

[0030] Figure 3 and Figure 4 The figures show a comparison of the insertion loss and isolation of the high-isolation on-chip transceiver switch in this invention with that without a coupling cancellation path. It can be seen that at a working frequency of 140GHz, although the insertion loss increases slightly by 1.3dB after introducing coupling cancellation, the isolation is significantly improved by 34dB, reaching 52dB. Even if a conventional coupled-line structure increases transistor size and sacrifices insertion loss to improve isolation, it cannot reach this level.

[0031] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-isolation on-chip transceiver switch, comprising: The switch comprises an input module, an output module and a coupling cancellation module; the input module comprises a primary coupling line (L1) and a matching capacitor (Cp); the matching capacitor (Cp) is connected in parallel with the primary coupling line (L1), one end of the parallel connection is connected with a port one (P1), and the other end is grounded; the input module and the output module are connected through a coupling line to form mutual inductance; The output module comprises a first secondary coupling line (L2), a second secondary coupling line (L3), a first transistor (M1) and a second transistor (M2); two ends of the first secondary coupling line (L2) are connected with a port two (P2), a source electrode and a drain electrode of the first transistor (M1), a gate electrode of the first transistor (M1) is connected with a first gate bias resistor (Rg1), a substrate is connected with a first substrate bias resistor (Rb1), the other end of the first gate bias resistor (Rg1) and the first substrate bias resistor (Rb1) is connected, and a first control voltage (Vc1) is connected; two ends in the middle of the second secondary coupling line (L3) are connected with a port three (P3), a source electrode and a drain electrode of the second transistor (M2), a gate electrode of the second transistor (M2) is connected with a second gate bias resistor (Rg2), a substrate is connected with a second substrate bias resistor (Rb2), the other end of the second gate bias resistor (Rg2) and the second substrate bias resistor (Rb2) is connected, and a second control voltage (Vc2) is connected; The coupling cancellation module comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3) and a fourth capacitor (C4), wherein, The first capacitor (C1) is connected in parallel with the first resistor (R1), the second capacitor (C2) is connected in parallel with the second resistor (R2), the inner end of the parallel connection of the first capacitor (C1) and the first resistor (R1) is connected with the drain electrode of the first transistor (M1), the inner end of the parallel connection of the second capacitor (C2) and the second resistor (R2) is connected with the drain electrode of the second transistor (M2), the outer end of the parallel connection of the first capacitor (C1) and the first resistor (R1) is connected with the outer end of the parallel connection of the second capacitor (C2) and the second resistor (R2); The third capacitor (C3) is connected in parallel with the third resistor (R3), the fourth capacitor (C4) is connected in parallel with the fourth resistor (R4), the inner end of the parallel connection of the third capacitor (C3) and the third resistor (R1) is connected with the source electrode of the first transistor (M1), the inner end of the parallel connection of the fourth capacitor (C4) and the fourth resistor (R4) is connected with the source electrode of the second transistor (M2), and the outer end of the parallel connection of the third capacitor (C3) and the third resistor (R3) is connected with the outer end of the parallel connection of the fourth capacitor (C4) and the fourth resistor (R4).

2. A high-isolation on-chip transceiver switch according to claim 1, wherein, The primary coupling line (L1), the first secondary coupling line (L2) and the second secondary coupling line (L3) are realized by metal lines of an integrated circuit process, and are coupling structures of the topmost metal, and other connection lines are connected by the next topmost metal.

3. The high-isolation on-chip transceiver switch of claim 1, wherein, The first transistor (M1) and the second transistor (M2) are the same, the gate length is a process, the maximum gate width is selected to make the insertion loss of the transistor not higher than 0.3 dB, and the minimum gate width is selected to make the isolation degree of the transistor not less than 7 dB.

4. The high-isolation on-chip transceiver switch of claim 1, wherein, The first gate bias resistor (Rg1), the second gate bias resistor (Rg2), the first substrate bias resistor (Rb1) and the second substrate bias resistor (Rb2) are the same, and the resistance value is between 6K ohms and 20K ohms.

5. The high-isolation on-chip transceiver switch of claim 1, wherein, The first control voltage (Vc1) and the second control voltage (Vc2) are selected between the positive supply voltage (VDD) and the negative supply voltage (-VDD).

6. A high-isolation on-chip transceiver switch as defined in claim 1, wherein, The first resistor (R1), the second resistor (R2), the third resistor (R3) and the fourth resistor (R4) are the same, the first capacitor (C1), the second capacitor (C2), the third capacitor (C3) and the fourth capacitor (C4) are the same, the resistance and the capacitor adjust the amplitude and the phase of the coupling cancellation path signal, cancel the secondary inter-coupling signal, and the switch isolation is greater than 50dB.

7. A high-isolation on-chip transceiver switch as claimed in claim 2, characterized in that, The first secondary coupling line (L2) and the second secondary coupling line (L3) are the same, the spacing between the primary coupling line (L1) is the same, the matching capacitor (Cp) is matched, the length, width and spacing of the primary coupling line (L1), the first secondary coupling line (L2) and the second secondary coupling line (L3) are not fixed, and the switch return loss is higher than 15dB.

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