High frequency circuit and communication device

Abstract

A high-frequency circuit and a communication device capable of attenuating harmonic components under differential amplification are provided. The high-frequency circuit includes a differential amplification circuit (16). The differential amplification circuit (16) includes a first amplification element (161), a second amplification element (162), a first wiring (R1), a second wiring (R2), and a series circuit (165). The first amplification element (161) has a first input terminal (161a) and a first output terminal (161b). The second amplification element (162) has a second input terminal (162a) and a second output terminal (162b). The first wiring (R1) is connected to the first output terminal (161b). The second wiring (R2) is connected to the second output terminal (162b). The series circuit (165) is connected between the first wiring (R1) and the second wiring (R2). The series circuit (165) includes a first inductor (e.g., an inductor Lc1), a second inductor (e.g., an inductor Lc2), and a capacitor (C1).

Description

Technical Field

[0001] This invention generally relates to a high-frequency circuit and a communication device, and more specifically, to a high-frequency circuit and a communication device having a differential amplifier circuit. Background Technology

[0002] Previously, a power amplifier module was known that converts a single-ended signal into a pair of differential signals and amplifies them (see Patent Document 1).

[0003] Patent Document 1's power amplification module includes a first transformer, a first amplification circuit, a second amplification circuit, and a second transformer. Regarding the first transformer, a single-ended signal is converted into a pair of differential signals using the first transformer. The first amplification circuit amplifies the power of one of the differential signals. The second amplification circuit amplifies the power of the other of the differential signals. The second transformer uses the signals amplified by the first amplification circuit and the signals amplified by the second amplification circuit to generate and output a single-ended signal.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-28108 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In power amplifier modules (high-frequency circuits) that perform differential amplification as described in Patent Document 1, harmonic components are not considered at all.

[0009] The present invention was made in view of the above-mentioned problems, and its object is to provide a high-frequency circuit and communication device that can attenuate harmonic components under differential amplification.

[0010] Solution for solving the problem

[0011] One aspect of the present invention relates to a high-frequency circuit comprising a differential amplifier circuit. The differential amplifier circuit includes a first amplifying element, a second amplifying element, a first wiring, a second wiring, and a series circuit. The first amplifying element has a first input terminal and a first output terminal. The second amplifying element has a second input terminal and a second output terminal. The first wiring is connected to the first output terminal. The second wiring is connected to the second output terminal. The series circuit is connected between the first wiring and the second wiring. The series circuit includes a first inductor, a second inductor, and a capacitor.

[0012] One aspect of the present invention relates to a communication device comprising the high-frequency circuit and a signal processing circuit connected to the high-frequency circuit.

[0013] The effects of the invention

[0014] According to the present invention, harmonic components under differential amplification can be attenuated. Attached Figure Description

[0015] Figure 1 This is a circuit diagram illustrating the structure of a communication device having a high-frequency circuit according to one embodiment.

[0016] Figure 2 This is a circuit diagram illustrating the structure of the differential amplifier circuit in the same high-frequency circuit.

[0017] Figure 3 This is a diagram illustrating the frequency characteristics of the same high-frequency circuit.

[0018] Figure 4 (A) is a diagram illustrating the frequency characteristics of the high-frequency circuit described above, which is obtained by having a series circuit. Figure 4 (B) is a Smith chart illustrating the phase of the harmonic components in the same high-frequency circuit.

[0019] Figure 5 This diagram illustrates the frequency characteristics of the high-frequency circuit described above, which incorporates both series circuitry and series resonant circuitry.

[0020] Figure 6 This is a top view illustrating a structural example of multiple inductors in a series circuit as described above.

[0021] Figure 7 (A) and Figure 7 (B) is a top view illustrating a structural example of each layer in which multiple inductors of the series circuit described above are configured.

[0022] Figure 8 This is a top view illustrating a structural example of the multiple inductors included in the series circuit of Modified Example 1 according to the embodiment.

[0023] Figure 9 (A) Figure 9 (C) is a diagram showing the configuration relationship in the high-frequency circuit of the modified example 5 according to the embodiment. Detailed Implementation

[0024] The following implementation methods, etc., are referenced Figures 6-9 (C) are all schematic diagrams. The size ratios and thickness ratios of the structural elements in the diagrams may not reflect the actual size ratios.

[0025] (Implementation Method)

[0026] Next, use Figures 1 to 7 (B) will be used to explain the high-frequency module 1 and the communication device 500 equipped with the high-frequency module 1 in the embodiment.

[0027] (1) High-frequency module

[0028] like Figure 1 As shown, the high-frequency module 1 involved in the embodiment includes a high-frequency circuit 10 and an antenna terminal 20.

[0029] The high-frequency module 1 involved in this embodiment is used, for example, in a communication device 500 that supports multiple modes / multi-bands. Figure 1 As shown, the communication device 500 includes a high-frequency module 1, a signal processing circuit 2, and an antenna 3. The communication device 500 is, for example, a portable telephone (e.g., a smartphone), but is not limited to this; it could also be a wearable terminal (e.g., a smartwatch). The high-frequency module 1 is, for example, a module capable of supporting 4G (fourth-generation mobile communication) standards, 5G (fifth-generation mobile communication) standards, etc. The 4G standard is, for example, the 3GPP (Third Generation Partnership Project) LTE (Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio).

[0030] The high-frequency module 1 involved in this embodiment performs communication in the mid-frequency band. In this embodiment, when communicating using 4G, the mid-frequency band defined in 4G is used, for example, Band4 (transmit band 1710MHz-1755MHz, receive band 2110MHz-2155MHz). When communicating using 5G, the mid-frequency band defined in 5G is used, for example, n1 (band 1920-1980).

[0031] (2) Structural elements of the high-frequency module

[0032] The structural elements of the high-frequency module 1 according to the embodiment will now be described with reference to the accompanying drawings.

[0033] As described above, the high-frequency module 1 includes a high-frequency circuit 10 and an antenna terminal 20. The high-frequency module 1 also includes a mounting substrate 300 (see reference 1). Figure 6 ).

[0034] The mounting substrate 300 has a main surface 301 (see reference). Figure 6The circuit components of the high-frequency circuit 10 are mounted on the main surface 301 of the mounting substrate 300. Here, "circuit components mounted on the main surface 301 of the mounting substrate 300" includes: the circuit components being disposed on the mounting substrate 300 (mechanically connected to the mounting substrate 300); and the circuit components being electrically connected to the mounting substrate 300 (a suitable conductor portion). Therefore, in the high-frequency module 1, each of the plurality of circuit components is disposed on the main surface 301 of the mounting substrate 300. The plurality of circuit components are not limited to electronic components mounted on the mounting substrate 300, but may also include circuit elements disposed within the mounting substrate 300.

[0035] The mounting substrate 300 is, for example, a printed circuit board, an LTCC (Low Temperature Co-fired Ceramics) substrate, an HTCC (High Temperature Co-fired Ceramics) substrate, or a resin multilayer substrate. Here, the mounting substrate 300 is, for example, a multilayer substrate including multiple dielectric layers and multiple conductive layers. The multiple dielectric layers and multiple conductive layers are stacked in the thickness direction of the mounting substrate 300. The multiple conductive layers are formed in a predetermined pattern determined for each layer. Each conductive layer includes one or more conductor portions in a plane orthogonal to the thickness direction of the mounting substrate 300. The material of each conductive layer is, for example, copper. The multiple conductive layers include a ground layer. In the high-frequency module 1, one or more ground terminals included in the multiple external connection terminals are electrically connected to the ground layer via conductive paths provided by the mounting substrate 300.

[0036] The mounting substrate 300 is not limited to printed circuit boards or LTCC substrates, but can also be a wiring structure. The wiring structure can be, for example, a multilayer structure. A multilayer structure includes at least one insulating layer and at least one conductive layer. The insulating layer is formed in a predetermined pattern. If there are multiple insulating layers, the multiple insulating layers are formed in a predetermined pattern determined for each layer. The conductive layer is formed in a predetermined pattern different from the predetermined pattern of the insulating layer. If there are multiple conductive layers, the multiple conductive layers are formed in a predetermined pattern determined for each layer. The conductive layer may also include one or more rewiring portions. The wiring structure can also be, for example, an interposer. The interposer can be an interposer using a silicon substrate, or it can be a substrate composed of multiple layers.

[0037] Additionally, the main surface 301 of the mounting substrate 300 may also have fine irregularities, recesses, or protrusions. When viewed from the thickness direction of the mounting substrate 300, the mounting substrate 300 is rectangular in shape, but it is not limited to this; for example, it may also be square in shape.

[0038] like Figure 1 As shown, antenna terminal 20 is electrically connected to antenna 3.

[0039] like Figure 1 As shown, the high-frequency circuit 10 includes a switch 11, a first matching circuit 12, a second matching circuit 13, a transmitting filter 14, a receiving filter 15, a differential amplifier circuit 16, a third matching circuit 17, and a low-noise amplifier 18.

[0040] Switch 11 is a switch that switches the connection destination connected to antenna terminal 20. For example... Figure 1 As shown, switch 11 has a common terminal 111 and multiple (two in the example) select terminals 112 and 113. Switch 11, under the control of signal processing circuit 2, selects at least one of select terminals 112 and 113 as the connection destination of the common terminal 111. The common terminal 111 is electrically connected to antenna terminal 20. That is, the common terminal 111 is electrically connected to antenna 3 via antenna terminal 20. Furthermore, the common terminal 111 is not limited to direct connection to antenna 3. A filter or coupler may also be provided between the common terminal 111 and antenna terminal 20. Select terminal 112 is electrically connected to first matching circuit 12. Select terminal 113 is electrically connected to second matching circuit 13. Switch 11 is configured to connect antenna terminal 20 to at least one of the first matching circuit 12 and second matching circuit 13 under the control of signal processing circuit 2.

[0041] The first matching circuit 12 achieves impedance matching between the transmitting filter 14 and the antenna terminal 20. The first matching circuit 12 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0042] The second matching circuit 13 achieves impedance matching between the receiving filter 15 and the antenna terminal 20. The second matching circuit 13 is composed of, for example, a single inductor, but is not limited thereto; for example, it may also include multiple inductors and multiple capacitors.

[0043] Regarding the transmitting filter 14, it may be an elastic wave filter, where each of the multiple series-arm resonators and multiple parallel-arm resonators is an elastic wave resonator. The elastic wave filter may be, for example, a SAW (Surface Acoustic Wave) filter utilizing surface acoustic waves. However, the transmitting filter 14 is not limited to a SAW filter. Besides being a SAW filter, the transmitting filter 14 may also be a BAW (Bulk Acoustic Wave) filter. Alternatively, the transmitting filter 14 may be constructed from an FBAR (Film Bulk Acoustic Resonator) or the like. Furthermore, the transmitting filter 14 may also be constructed from an LC resonant circuit or the like.

[0044] Transmit filter 14 allows high-frequency signals (transmitted signals) transmitted from antenna 3 to pass through. For example, transmit filter 14 allows transmitted signals within a frequency band that falls within the mid-to-high frequency range to pass through. In this embodiment, transmit filter 14 allows transmitted signals within a communication frequency band specified in 4G to pass through as transmitted signals within that band. For example, this is Band 4 specified in 4G. That is, the transmitted signal is a signal within a frequency band of 1710MHz-1755MHz.

[0045] Regarding the receiving filter 15, it may be an elastic wave filter, where each of the multiple series-arm resonators and multiple parallel-arm resonators is an elastic wave resonator. An elastic wave filter may be, for example, a SAW filter utilizing surface acoustic waves. However, the receiving filter 15 is not limited to a SAW filter. Besides being a SAW filter, the receiving filter 15 may also be a BAW filter, for example. Alternatively, the receiving filter 15 may be constructed using an FBAR, etc. Furthermore, the receiving filter 15 may also be constructed using an LC resonant circuit, etc.

[0046] The receiving filter 15 allows the high-frequency signal (received signal) received by the antenna 3 to pass through. For example, the receiving filter 15 allows received signals within a mid-to-high frequency band to pass through. In this embodiment, the receiving filter 15 allows transmission signals within a communication band specified in 4G to pass through as transmission signals within that band. Here, the communication band is, for example, Band 4 specified in 4G. That is, the received signal is a signal within a frequency band of 2110MHz-2155MHz.

[0047] The differential amplifier circuit 16 differentially amplifies the signal (transmit signal) received from the signal processing circuit 2, attenuating the harmonic components (second harmonic component, third harmonic component, etc.). The detailed structure of the differential amplifier circuit 16 will be described later.

[0048] The third matching circuit 17 achieves impedance matching between the receiving filter 15 and the low-noise amplifier 18. The third matching circuit 17 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0049] The low-noise amplifier 18 amplifies the received signal. The input terminal of the low-noise amplifier 18 is electrically connected to the receiving filter 15. The output terminal of the low-noise amplifier 18 is electrically connected to the signal processing circuit 2. That is, the received signal received by the antenna 3 is input to the low-noise amplifier 18 via the receiving filter 15. The amplified received signal is then output from the low-noise amplifier 18 to the signal processing circuit 2.

[0050] (3) Communication device

[0051] like Figure 1As shown, the communication device 500 according to this embodiment includes a high-frequency module 1, a signal processing circuit 2, and an antenna 3. The signal processing circuit 2 performs signal processing on the signal passing through the high-frequency module 1. The signal processing circuit 2 includes a baseband signal processing circuit 201 and an RF signal processing circuit 202.

[0052] like Figure 1 As shown, the baseband signal processing circuit 201 is, for example, a BBIC (Baseband Integrated Circuit), electrically connected to the RF signal processing circuit 202. The baseband signal processing circuit 201 generates I-phase and Q-phase signals based on the baseband signal. After performing IQ modulation processing by combining the I-phase and Q-phase signals, the baseband signal processing circuit 201 outputs a transmit signal. At this time, the transmit signal is generated as a modulated signal obtained by amplitude modulation of a carrier signal of a specified frequency with a period longer than the period of the carrier signal.

[0053] like Figure 1 As shown, the RF signal processing circuit 202 is, for example, an RFIC (Radio Frequency Integrated Circuit), disposed between the high-frequency module 1 and the baseband signal processing circuit 201. The RF signal processing circuit 202 has the function of processing the transmitted signal from the baseband signal processing circuit 201 and the function of processing the received signal received using the antenna 3. The RF signal processing circuit 202 is a multi-band processing circuit capable of generating and amplifying transmitted signals from multiple communication frequency bands.

[0054] Furthermore, in the communication device 500, the baseband signal processing circuit 201 is not an essential structural element.

[0055] (4) Differential amplifier circuit

[0056] The differential amplifier circuit 16 is included in the high-frequency circuit 10. For example... Figure 2 As shown, the differential amplifier circuit 16 includes a differential amplifier 16A, a series circuit 165, an output matching circuit 166, and a series resonant circuit 167. Figure 2 As shown, the differential amplifier 16A includes a first amplifying element 161, a second amplifying element 162, a third amplifying element 163, an interstage balun circuit 164, a first wiring R1, and a second wiring R2. The differential amplifier 16A is constructed from a single chip. That is, the first amplifying element 161, the second amplifying element 162, the third amplifying element 163, and the interstage balun circuit 164 are monolithically integrated.

[0057] The third amplifying element 163 has input and output terminals. The input terminal of the third amplifying element 163 is connected to the RF signal processing circuit 202 of the signal processing circuit 2 (see reference). Figure 1 Electrical connection. The output terminal of the third amplifying element 163 is electrically connected to the interstage balun circuit 164. The third amplifying element 163 amplifies the high-frequency signal (transmit signal) output from the RF signal processing circuit 202 of the signal processing circuit 2 and outputs it to the interstage balun circuit 164. A voltage Vcc1 is applied to the output terminal of the third amplifying element 163. That is, the transmit signal output from the signal processing circuit 2 is amplified by the third amplifying element 163 when a voltage Vcc1 is applied to the third amplifying element 163.

[0058] The interstage balun circuit 164 includes an unbalanced terminal 164a and a pair of balanced terminals 164b and 164c. The unbalanced terminal 164a is electrically connected to the output terminal of the third amplifying element 163. That is, the unbalanced terminal 164a is electrically connected to the signal processing circuit 2 via the third amplifying element 163. The balanced terminal 164b is electrically connected to the first amplifying element 161, and the balanced terminal 164c is electrically connected to the second amplifying element 162.

[0059] The interstage balun circuit 164 also includes a primary-side coil L10 and a secondary-side coil L11. One end of the primary-side coil L10 is electrically connected to the unbalanced terminal 164a. The other end of the primary-side coil L10 is connected to ground. One end of the secondary-side coil L11 is electrically connected to the balanced terminal 164b, and the other end of the secondary-side coil L11 is electrically connected to the balanced terminal 164c. Furthermore, the primary-side coil L10 and the secondary-side coil L11 may also be formed from a conductor pattern portion.

[0060] At the unbalanced terminal 164a, a high-frequency signal (transmit signal) amplified by the third amplifying element 163 is input as a signal output from the RF signal processing circuit 202. The interstage balun circuit 164 performs unbalanced-balanced conversion on the signal input at the unbalanced terminal 164a, outputting one of the two signals with inverted phases (two signals with phases offset by 180 degrees) to the first amplifying element 161, and outputting the other signal to the second amplifying element 162.

[0061] The first amplifying element 161 and the second amplifying element 162 include, for example, an HBT (Heterojunction Bipolar Transistor) as a bipolar transistor.

[0062] The first amplifying element 161 has a first input terminal 161a and a first output terminal 161b. The first input terminal 161a of the first amplifying element 161 is electrically connected to the balanced terminal 164b of the interstage balun circuit 164. The first output terminal 161b of the first amplifying element 161 is electrically connected to the output matching circuit 166 via a first wiring R1. The first amplifying element 161 amplifies the signal output from the balanced terminal 164b and outputs it to the output matching circuit 166.

[0063] The second amplifying element 162 has a second input terminal 162a and a second output terminal 162b. The second input terminal 162a of the second amplifying element 162 is electrically connected to the balanced terminal 164c of the interstage balun circuit 164. The second output terminal 162b of the second amplifying element 162 is electrically connected to the output matching circuit 166 via the second wiring R2. The second amplifying element 162 amplifies the signal output from the balanced terminal 164c and outputs it to the output matching circuit 166.

[0064] The first wiring R1 is formed by a conductor pattern. One end of the first wiring R1 is electrically connected to the first output terminal 161b of the first amplifying element 161. The other end of the first wiring R1 is electrically connected to the output matching circuit 166.

[0065] The second wiring R2 is formed by a conductor pattern. One end of the second wiring R2 is electrically connected to the second output terminal 162b of the second amplifying element 162. The other end of the second wiring R2 is electrically connected to the output matching circuit 166.

[0066] A series circuit 165 is electrically connected between the first wiring R1 and the second wiring R2. The series circuit 165 includes an inductor Lc1 (first inductor), an inductor Lc2 (second inductor), and a capacitor C1 (first capacitor). The capacitor C1 is, for example, a surface-mount capacitor. Inductors Lc1 and Lc2 are formed from a conductor pattern. The inductance value of inductor Lc1 is the same as the inductance value of inductor Lc2. For example, inductors Lc1 and Lc2 are mounted (configured) in a linearly symmetrical manner with respect to a predetermined axis. This allows the inductance value of inductor Lc1 to be the same as the inductance value of inductor Lc2. Here, "the inductance value of inductor Lc1 is the same as the inductance value of inductor Lc2" includes not only the case where the inductance values ​​of inductor Lc1 and inductor Lc2 are completely identical, but also the case where, based on the inductance value of inductor Lc1, the inductance value of inductor Lc2 is within ±20%.

[0067] One end of inductor Lc1 is electrically connected to the first wiring R1. The other end of inductor Lc1 is connected to one end of capacitor C1. The other end of capacitor C1 is electrically connected to one end of inductor Lc2. The other end of inductor Lc2 is electrically connected to the second wiring R2. The series circuit 165 is not connected to ground.

[0068] The series circuit 165 is a series resonant circuit with the above-described structure, which attenuates odd-order harmonic components of the transmitted signal frequency, such as the third harmonic component. The series circuit 165 attenuates harmonic components between a first value (three times the lower limit of the communication frequency band to which the transmitted signal belongs) and a second value (three times the upper limit of the communication frequency band). For example, the series circuit 165 attenuates harmonic components three times the center frequency of the communication frequency band. That is, the series circuit 165 attenuates harmonic components three times the frequency of the transmitted signal in the signal output from the first amplifying element 161. Furthermore, the series circuit 165 attenuates harmonic components three times the frequency of the transmitted signal in the signal output from the second amplifying element 162. In other words, the series circuit 165 can also be described as a bypass circuit that bypasses harmonic components passing through the first wiring R1 and the second wiring R2 to the series circuit 165. And, in other words, the series circuit 165 attenuates harmonic components passing through the first wiring R1 and the second wiring R2, and therefore can also be described as an attenuation circuit.

[0069] The output matching circuit 166 is a so-called balun circuit. The output matching circuit 166 achieves impedance matching between the differential amplifier 16A and the transmitting filter 14. The output matching circuit 166 includes a capacitor C2 and multiple (four in the example) inductors L1, L2, L3, and L4, forming the balun circuit. The output matching circuit 166 also includes an unbalanced terminal 166c and a pair of balanced terminals 166a and 166b. The inductors L1, L2, L3, and L4 are formed by a conductor pattern. Alternatively, the inductors L1, L2, L3, and L4 can also be surface-mount inductors, etc.

[0070] The balanced terminal 166a is electrically connected to the first output terminal 161b of the first amplifying element 161 via the first wiring R1. The balanced terminal 166b is electrically connected to the second output terminal 162b of the second amplifying element 162 via the second wiring R2. The unbalanced terminal 166c is electrically connected to the series resonant circuit 167 and the transmitting filter 14.

[0071] Inductors L1 and L2 are connected in series. One end of inductor L1 is connected to ground. The other end of inductor L1 is connected to one end of inductor L2. The other end of inductor L2 is connected to the unbalanced terminal 166c. Inductors L3 and L4 are connected in series. One end of inductor L3 is connected to the balanced terminal 166a. The other end of inductor L3 is connected to one end of inductor L4. The other end of inductor L4 is connected to the balanced terminal 166b. One end of capacitor C2 is connected to the point between inductors L3 and L4 (e.g., the midpoint). The other end of capacitor C2 is connected to ground.

[0072] In the output matching circuit 166, the signals output from the first amplifying element 161 and the signals output from the second amplifying element, maintaining a phase reversal, undergo impedance transformation. As a result, the output impedance of the differential amplifier 16A is impedance matched to the input impedance of the transmit filter 14. The impedance-matched transmit signal is then input to the transmit filter 14.

[0073] One end of the series resonant circuit 167 is electrically connected to the unbalanced terminal 166c, and the other end is connected to ground. The series resonant circuit 167 includes a capacitor C3 (a second capacitor) and an inductor Lc3. The inductor Lc3 is formed from a conductor pattern. One end of the capacitor C3 is electrically connected to the unbalanced terminal 166c. The other end of the capacitor C3 is electrically connected to one end of the inductor Lc3. The other end of the inductor Lc3 is connected to ground. Alternatively, the inductor Lc3 can also be a surface-mount inductor, etc.

[0074] The series resonant circuit 167 attenuates even-order harmonic components of the transmitted signal's frequency, such as the second harmonic component. The series resonant circuit 167 attenuates harmonic components between a third value (twice the lower limit of the communication band to which the transmitted signal belongs) and a fourth value (twice the upper limit of the communication band). For example, the series resonant circuit 167 attenuates harmonic components twice the center frequency of the communication band, using the center frequency as a reference. That is, the series resonant circuit 167 attenuates harmonic components twice the frequency of the transmitted signal in the signal output from the output matching circuit 166.

[0075] like Figure 2As shown, the differential amplifier circuit 16 also includes multiple (two in the example) inductors La1 (third inductor) and La2 (fourth inductor). Inductors La1 and La2 are formed from conductor pattern portions. The inductance value of inductor La1 is the same as the inductance value of inductor La2. For example, inductors La1 and La2 are mounted (configured) in a linearly symmetrical manner with respect to a predetermined axis. This allows the inductance value of inductor La1 to be the same as the inductance value of inductor La2. Here, "the inductance value of inductor La1 is the same as the inductance value of inductor La2" includes not only the case where the inductance values ​​of inductors La1 and La2 are completely identical, but also the case where, based on the inductance value of one of inductors La1 (e.g., inductor La1), the inductance value of the other (e.g., inductor La2) is within a range of ±20%.

[0076] Inductor La1 is connected between the first output terminal 161b and the first wiring R1. Inductor La2 is connected between the second output terminal 162b and the second wiring R2. Inductors La1 and La2 adjust the phase of the harmonic components (the third harmonic component, which is three times the frequency of the transmitted signal). Specifically, inductors La1 and La2 adjust the phase of the harmonic components toward the open circuit direction.

[0077] (5) Effect

[0078] As described above, the high-frequency circuit 10 according to the embodiment includes a differential amplifier circuit 16. The differential amplifier circuit 16 includes a first amplifying element 161, a second amplifying element 162, a first wiring R1, a second wiring R2, and a series circuit 165. The first amplifying element 161 has a first input terminal 161a and a first output terminal 161b. The second amplifying element 162 has a second input terminal 162a and a second output terminal 162b. The first wiring R1 is connected to the first output terminal 161b. The second wiring R2 is connected to the second output terminal 162b. The series circuit 165 is connected between the first wiring R1 and the second wiring R2. The series circuit 165 includes a first inductor (inductor Lc1), a second inductor (inductor Lc2), and a capacitor C1.

[0079] According to this structure, when the series circuit 165 is configured as a series resonant circuit, the harmonic components associated with the transmitted signal under differential amplification, such as the third harmonic component of the frequency of the transmitted signal, can be attenuated.

[0080] Here, Figure 3 The frequency characteristics of a high-frequency circuit 10 having a series resonant circuit 165 and a high-frequency circuit without a series resonant circuit are shown. Figure 3The frequency band f0 shown is the frequency band to which the transmitted signal frequency belongs. Figure 3 The frequency band f1 shown is three times the frequency band f0. That is, frequency band f1 includes the third order of the transmitted signal frequency. The solid line represents the frequency characteristic G1 in the high-frequency circuit 10 equipped with the series resonant circuit 165. The dashed line represents the frequency characteristic G2 of the high-frequency circuit without the series resonant circuit. Furthermore, in Figure 3 The text does not mention the second harmonic component of the transmitted signal frequency.

[0081] According to frequency characteristic G1, in the high-frequency circuit 10 of the embodiment, the signal does not attenuate in frequency band f0, but attenuates in frequency band f1. On the other hand, according to frequency characteristic G2, in a high-frequency circuit without a series resonant circuit, the signal does not attenuate in either frequency band f0 or frequency band f1.

[0082] Therefore, compared with high-frequency circuits that do not have series resonant circuits, the high-frequency circuit 10 of the embodiment can perform good communication.

[0083] Additionally, a series circuit 165 is connected between the first wiring R1 and the second wiring R2. Compared to the case where a circuit that attenuates harmonic components (resonant circuit) is provided in the wiring, the high-frequency circuit 10 of this embodiment can reduce the loss of transmitted signals caused by the resonant circuit.

[0084] Furthermore, the high-frequency circuit 10 in this embodiment also includes a third inductor (inductor La1) and a fourth inductor (inductor La2). The third inductor is connected between the first output terminal 161b and the first wiring R1. The fourth inductor is connected between the second output terminal 162b and the second wiring R2.

[0085] According to this structure, the phase of the third harmonic component of the transmitted signal frequency can be adjusted towards the open circuit direction.

[0086] Here, Figure 4 (A) shows the frequency characteristics of a high-frequency circuit 10 (high-frequency circuit 10 of the embodiment) having a series circuit 165, a third inductor and a fourth inductor, and the frequency characteristics of a high-frequency circuit without a third inductor and a fourth inductor. Figure 4 (A) shows the frequency characteristics of the high-frequency circuit 10 of the embodiment and the frequency characteristics of the high-frequency circuit without the third and fourth inductors (the high-frequency circuit of the comparative example). Here, the high-frequency circuit of the comparative example includes a resonant circuit that attenuates the third harmonic component of the frequency of the transmitted signal. Figure 4 (A) is a graph representing the frequency response of band f1. Furthermore, in Figure 4 In (A), the second harmonic component of the frequency of the transmitted signal is not mentioned.

[0087] in addition, Figure 4 (B) shows a Smith chart of the phase of the third harmonic component of the frequency of the transmitted signal of the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example.

[0088] Figure 4 ZA1, as shown in (B), represents the phase of the third frequency of the transmitted signal in the high-frequency circuit 10 of the embodiment. Figure 4 ZA2 shown in (B) represents the phase of the third frequency of the transmitted signal in the high-frequency circuit of the comparative example.

[0089] according to Figure 4 As can be seen from (A), the frequency characteristics are approximately the same in the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example. That is, both the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example attenuate the third harmonic component of the frequency of the transmitted signal.

[0090] On the other hand, according to Figure 4 As can be seen from (B), compared to the phase of the third harmonic component of the frequency of the transmitted signal in the high-frequency circuit of the comparative example, the phase of the third harmonic component of the frequency of the transmitted signal in the high-frequency circuit 10 of the embodiment is located on the open-circuit side. That is, by providing a third inductor and a fourth inductor, the high-frequency circuit can adjust the phase of the third harmonic component of the frequency of the transmitted signal toward the open-circuit direction.

[0091] Furthermore, the differential amplifier circuit 16 of the high-frequency circuit 10 in this embodiment includes a series resonant circuit 167. One end of the series resonant circuit 167 is connected to the unbalanced terminal 166c. The series resonant circuit 167 includes a capacitor C2 and an inductor Lc3, and the capacitor C2 is different from the capacitor C1 of the series circuit 165.

[0092] According to this structure, it is possible to attenuate the harmonic components associated with the transmitted signal under differential amplification, such as the second harmonic component of the frequency of the transmitted signal.

[0093] Here, Figure 5 The frequency characteristics of a high-frequency circuit 10 (hereinafter referred to as high-frequency circuit 10) having a series circuit 165 and a series resonant circuit 167 are shown, as well as the frequency characteristics of a high-frequency circuit without a series resonant circuit (another comparative example of a high-frequency circuit). Figure 5 The frequency band f0 shown is the frequency band to which the transmitted signal frequency belongs. Figure 5 The frequency band f1 shown is three times the frequency band f0. That is, frequency band f1 contains three times the frequency of the transmitted signal. Figure 5The frequency band f2 shown is twice the frequency band f0. That is, frequency band f2 contains twice the frequency of the transmitted signal. The solid line represents the frequency characteristic G11 in the high-frequency circuit 10. The dashed line represents the frequency characteristic G12 of the high-frequency circuit of another comparative example.

[0094] According to frequency characteristic G11, in the high-frequency circuit 10, the signal does not attenuate in frequency band f0, but attenuates in frequency bands f1 and f2. On the other hand, according to frequency characteristic G12, in the high-frequency circuit of another comparative example, the signal does not attenuate in any of the frequency bands f0, f1, and f2.

[0095] Therefore, compared with the high-frequency circuit of another comparative example, the high-frequency circuit 10 is able to transmit well.

[0096] (6) Specific examples

[0097] Here, use Figures 6-7 (B) will be used to illustrate a specific example of the construction of inductors Lc1, Lc2, La1, and La2.

[0098] like Figure 6 and Figure 7 As shown in (A), the first output terminal 161b, the second output terminal 162b, inductors Lc1 and Lc2, and capacitor C1 of the differential amplifier 16A are mounted on the main surface 301 of the mounting substrate 300. Inductors Lc1 and Lc2 are arranged as conductor patterns on the main surface 301 of the mounting substrate 300. Figure 7 As shown in (B), inductors La1 and La2 are disposed as conductor pattern portions in the dielectric layer 302 inside the mounting substrate 300.

[0099] The first output terminal 161b is electrically connected to inductor La1 via passage B1. The second output terminal 162b is electrically connected to inductor La2 via passage B2. Inductor La1 and inductor Lc1 are electrically connected via passage B11. Inductor La2 and inductor Lc2 are electrically connected via passage B12.

[0100] Viewed from the thickness direction of the mounting substrate 300, inductors Lc1 and Lc2 are linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1. By configuring inductors Lc1 and Lc2 to be linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1, the difference between the impedance at the first output terminal 161b and the impedance at the second output terminal 162b can be minimized. That is, the inductance value of inductor Lc1 can be made the same as that of inductor Lc2.

[0101] Viewed from the thickness direction of the mounting substrate 300, inductors La1 and La2 are linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1. By configuring inductors La1 and La2 to be linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1, the difference between the impedance at the first output terminal 161b and the impedance at the second output terminal 162b can be minimized. It is also possible to make the inductance value of inductor La1 the same as that of inductor La2.

[0102] Furthermore, in this embodiment, inductors Lc1 and Lc2 are configured to be disposed on the main surface 301 of the mounting substrate 300, but this configuration is not limited to this structure. Inductors Lc1 and Lc2 may also be disposed as conductor pattern portions within the dielectric layer inside the mounting substrate 300. Alternatively, a chip inductor may be mounted on the mounting substrate 300 as inductor Lc1. Similarly, a chip inductor may be mounted on the mounting substrate 300 as inductor Lc2.

[0103] The structure is configured such that inductors La1 and La2 are disposed as conductor patterns within the dielectric layer 302 inside the mounting substrate 300, but this configuration is not limited to this structure. Inductors La1 and La2 may also be disposed as conductor patterns on the main surface 301. Alternatively, a chip inductor may be mounted on the mounting substrate 300 as inductor La1. Similarly, a chip inductor may be mounted on the mounting substrate 300 as inductor La2.

[0104] In this embodiment, the first output terminal 161b and the second output terminal 162b are arranged on the side of the differential amplifier 16A that faces each other in the thickness direction of the mounting substrate 300, closer to the mounting substrate 300. However, this structure is not limited to this one. Alternatively, the first output terminal 161b and the second output terminal 162b may be arranged on the side of the differential amplifier 16A that faces each other in the thickness direction of the mounting substrate 300, away from the mounting substrate 300. In this case, the inductors La1 and La2 may also be configured by wire bonding.

[0105] (7) Variation

[0106] The following describes variations of the implementation method.

[0107] (7.1) Variation Example 1

[0108] Inductors La1 and La2 are not essential structural elements of the high-frequency circuit 10. As mentioned above, even if the high-frequency circuit 10 does not have inductors La1 and La2, such as Figure 4As shown in (A), as long as the high-frequency circuit 10 has the series circuit 165, the harmonic components associated with the transmitted signal can be attenuated.

[0109] use Figure 8 To illustrate the construction of inductors Lc1 and Lc2 in Modified Example 1.

[0110] like Figure 8 As shown, the first output terminal 161b, the second output terminal 162b, inductors Lc1 and Lc2, and capacitor C1 of the differential amplifier 16A are mounted on the main surface 301 of the mounting substrate 300. Inductors Lc1 and Lc2 are arranged as conductor pattern portions on the main surface 301 of the mounting substrate 300.

[0111] The first output terminal 161b is electrically connected to inductor Lc1. The second output terminal 162b is electrically connected to inductor Lc2.

[0112] Viewed from the thickness direction of the mounting substrate 300, inductors Lc1 and Lc2 are linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1. By configuring inductors Lc1 and Lc2 to be linearly symmetrical with respect to an axis passing through the center of capacitor C1 and along direction D1, the difference between the impedance at the first output terminal 161b and the impedance at the second output terminal 162b can be minimized. That is, the inductance value of inductor Lc1 can be made the same as that of inductor Lc2.

[0113] Furthermore, in Modification 1, inductors Lc1 and Lc2 are configured to be disposed on the main surface 301 of the mounting substrate 300, but this configuration is not limited to this structure. Inductors Lc1 and Lc2 may also be disposed as conductor pattern portions within the dielectric layer inside the mounting substrate 300. Alternatively, a chip inductor may be mounted on the mounting substrate 300 as inductor Lc1. Similarly, a chip inductor may be mounted on the mounting substrate 300 as inductor Lc2.

[0114] In Modification 1, the first output terminal 161b and the second output terminal 162b are arranged on the side of the differential amplifier 16A closest to the mounting substrate 300, one of two faces facing each other in the thickness direction of the mounting substrate 300. However, this configuration is not limited to this one. Alternatively, the first output terminal 161b and the second output terminal 162b may be arranged on the side of the differential amplifier 16A furthest from the mounting substrate 300, one of two faces facing each other in the thickness direction of the mounting substrate 300. In this case, the inductors La1 and La2 may also be configured by wire bonding.

[0115] (7.2) Variation Example 2

[0116] The circuit installed between the third amplifying element 163 and the first amplifying element 161 and the second amplifying element 162 is not limited to the interstage balun circuit 164. Between the third amplifying element 163 and the first amplifying element 161 and the second amplifying element 162, any circuit that generates two signals with opposite phases based on a single signal is acceptable.

[0117] (7.3) Variation Example 3

[0118] The high-frequency circuit 10 is assumed to be used in communication in the mid-frequency band, but it is not limited to this. The high-frequency circuit 10 can also be used in communication in the low-frequency band, and it can also be used in communication in the high-frequency band. Alternatively, the high-frequency circuit 10 can also be used in communication in the ultra-high frequency band.

[0119] (7.4) Variation Example 4

[0120] The transmitting filter 14 is a structure that allows signals from one communication frequency band to pass through, but it is not limited to this structure. The transmitting filter 14 can also be configured to allow signals from multiple communication frequency bands to pass through.

[0121] In Variation 4, the series circuit 165 attenuates the high-frequency signal between a first value, which is three times the smallest of the lower limits of the multiple communication frequency bands, and a second value, which is three times the largest of the upper limits of the multiple communication frequency bands.

[0122] (7.5) Variation Example 5

[0123] (7.5.1) First viewpoint

[0124] use Figure 9 (A) Figure 9 (C) will be used to illustrate a variation from the viewpoint of the mounting substrate 300 viewed from the arrangement direction D1 (direction D1). Here, the arrangement direction D1 is the direction in which the output matching circuit 166 and the differential amplifier 16A are arranged when viewed from above in the thickness direction of the mounting substrate 300.

[0125] Alternatively, capacitor C1 can be configured on mounting substrate 300 in such a way that when viewed from the arrangement direction D1, the first portion of capacitor C1, differential amplifier 16A, and output matching circuit 166 included in series circuit 165, a first portion of capacitor C1 overlaps with output matching circuit 166, and a second portion of capacitor C1 overlaps with differential amplifier 16A.

[0126] For example, such as Figure 9 (A) Figure 9As shown in (C), the mounting substrate 300 is a multilayer substrate, including a first layer 300a, a second layer 300b and a third layer 300c.

[0127] The first layer 300a has a main surface 301. On the first layer 300a, a differential amplifier 16A, capacitor C1 of series circuit 165, inductors Lc1 and Lc2, and inductor L2 of output matching circuit 166 are configured (see reference). Figure 9 (A)). Inductors Lc1, Lc2 and L2 are respectively configured as conductor pattern portions. The second layer 300b is the lower layer of the first layer 300a, and is equivalent to the dielectric layer 302 mentioned above. In the second layer 300b, inductors La1 and La2 of the series circuit 165 and inductors L3 and L4 of the output matching circuit 166 are configured (see reference). Figure 9 (B)). Inductors La1, La2 and inductors L3, L4 are respectively configured as conductor pattern sections. The third layer 300c is the lower layer of the second layer 300b. In the third layer 300c, inductor L1 of the output matching circuit 166 is configured (refer to...). Figure 9 (C)). Inductor L1 is configured as a conductor pattern portion. The stacking direction of the first layer 300a, the second layer 300b, and the third layer 300c is the thickness direction of the mounting substrate 300.

[0128] The first layer 300a, the second layer 300b, and the third layer 300c are stacked, thereby electrically connecting inductor L2 and inductor L1 via passage B20. Furthermore, the first layer 300a, the second layer 300b, and the third layer 300c are stacked, thereby electrically connecting inductor Lc2, inductor L4, and inductor La2 via passage B21. Additionally, the first layer 300a, the second layer 300b, and the third layer 300c are stacked, thereby electrically connecting inductor Lc1, inductor L3, and inductor La1 via passage B22. The first output terminal 161b is electrically connected to inductor La1 via passage B1. The second output terminal 162b is electrically connected to inductor La2 via passage B2.

[0129] At this point, when viewed from the arrangement direction D1, at least a portion (the second portion) of capacitor C1 overlaps with differential amplifier 16A (see reference). Figure 9 (A)).

[0130] Furthermore, when viewed from the arrangement direction D1, at least a portion (the first portion) of capacitor C1 overlaps with the output matching circuit 166. Specifically, when viewed from the arrangement direction D1, at least a portion (the first portion) of capacitor C1 overlaps with the inductor L2 of the output matching circuit 166. That is, when viewed from the arrangement direction D1, at least a portion (the first portion) of capacitor C1 is disposed between the two outer edges L2a and L2b, which are the outer edges of inductor L2 and extend along the arrangement direction D1.

[0131] Alternatively, when viewed from the arrangement direction D1, the first part of capacitor C1 may be located between inductors L3 and L4 of the output matching circuit 166. That is, when viewed from the arrangement direction D1, the first part of capacitor C1 may be positioned between the outer edge L3a of inductor L3 and the outer edge L4a of inductor L4. Alternatively, when viewed from the arrangement direction D1, the first part of capacitor C1 may overlap with inductor L1 of the output matching circuit 166. That is, when viewed from the arrangement direction D1, the first part of capacitor C1 may be positioned between the two outer edges L1a and L1b that extend along the arrangement direction D1 and serve as the outer edges of inductor L1.

[0132] Alternatively, when viewed from the arrangement direction D1, capacitor C1 may overlap with at least one of the output matching circuit 166 and the differential amplifier 16A. Under the first viewpoint of Modification 5, as... Figure 9 As shown in (A), when viewing the mounting substrate 300 from the arrangement direction D1, the capacitor C1 overlaps with both the output matching circuit 166 and the differential amplifier 16A.

[0133] Alternatively, the output matching circuit 166, capacitor C1, and differential amplifier 16A can be configured such that, when viewed from the thickness direction of the mounting substrate 300, the center P2 of capacitor C1 is aligned along the arrangement direction D1 with the center P1 of output matching circuit 166 and the center P3 of differential amplifier 16A, respectively. Here, when viewed from the thickness direction of the mounting substrate 300, the center P2 of capacitor C1 is aligned along the arrangement direction D1 with the center P1 of output matching circuit 166 and the center P3 of differential amplifier 16A. More specifically, when viewed from the thickness direction of the mounting substrate 300, the center P2 of capacitor C1, the center P1 of output matching circuit 166, and the center P3 of differential amplifier 16A are located on a straight line H1 along the arrangement direction D1. Here, the center P1 of output matching circuit 166 refers to the center of the rectangular region of output matching circuit 166. Similarly, the center P2 of capacitor C1 refers to the center of the rectangular region of capacitor C1. Furthermore, the center P3 of the differential amplifier 16A refers to the center of the rectangular region of the differential amplifier 16A.

[0134] Under the first viewpoint of Modification 5, capacitor C1 can be positioned on the mounting substrate 300 in such a way that, when viewed from the arrangement direction D1, at least a portion of capacitor C1 overlaps with the output matching circuit 166, and at least a portion of capacitor C1 overlaps with the differential amplifier 16A. Therefore, the arrangement order of the output matching circuit 166, the series circuit 165, and the differential amplifier 16A in the arrangement direction D1 is not specified. That is, in Figure 9 (A) Figure 9 In (C), capacitor C1, i.e., series circuit 165, is a structure arranged in the arrangement direction D1 between differential amplifier 16A and output matching circuit 166, but is not limited to this structure. Alternatively, output matching circuit 166 can be arranged in the arrangement direction D1 between series circuit 165 and differential amplifier 16A. Or, differential amplifier 16A can be arranged in the arrangement direction D1 between series circuit 165 and output matching circuit 166.

[0135] According to the first point of view in Modification 5, capacitor C1 is arranged on mounting substrate 300 in such a way that, when viewed from the arrangement direction D1, at least a portion of capacitor C1 overlaps with output matching circuit 166, and at least a portion of capacitor C1 overlaps with differential amplifier 16A. With this structure, a balance can be achieved between differential amplifier 16A and capacitor C1, and between inductors La1 and Lc1, and La2 and Lc2. That is, the lengths of inductors La1 and Lc1, and La2 and Lc2, between differential amplifier 16A and capacitor C1, can be made the same. Thus, a balance can be achieved between the combined inductance (coupling amount) of inductors La1 and Lc1 and the combined inductance (coupling amount) of inductors La2 and Lc1. As a result, stabilization of operation during communication can be achieved. Here, the lengths of inductors La1 and Lc1 are from the first output terminal 161b to the capacitor C1. The lengths of inductors La2 and Lc2 are from the second output terminal 162b to the capacitor C1.

[0136] In the first viewpoint of Modification 5, each inductor in the output matching circuit 166, from L1 to L4, has a structure formed by a conductor pattern portion, but is not limited to this structure. Each inductor in L1 to L4 may also be formed by a chip inductor. Alternatively, the output matching circuit 166 may also be formed by a single chip.

[0137] (7.5.2) Second viewpoint

[0138] This section describes a variation from the perspective of a direction D2 that is orthogonal to both the thickness direction and the arrangement direction D1 of the mounting substrate 300. The arrangement direction D1 is the direction in which the output matching circuit 166 and the differential amplifier 16A are arranged.

[0139] Alternatively, when viewed from direction D2, between the outer edge 1601 of the differential amplifier 16A along direction D2, which is farther from the output matching circuit 166, and the outer edge P101 of the output matching circuit 166 along direction D2, which is farther from the differential amplifier 16A, the capacitor C1 included in the series circuit 165 is disposed on the mounting substrate 300 (refer to...). Figure 9 (A) Here, the outer edge P101 is the side of the smallest rectangle P10 surrounding the inductor L2 that is furthest from the output matching circuit 166 along the direction D2.

[0140] Alternatively, regarding capacitor C1, when viewed from direction D2, capacitor C1 can be disposed on the mounting substrate 300 between the outer edge of the side furthest from the output matching circuit 166 among the two sides of the smallest rectangle surrounding inductors L3 and L4 along direction D2 and the outer edge P101 of the differential amplifier 16A. Alternatively, when viewing the mounting substrate 300 from direction D2, capacitor C1 can also be disposed on the mounting substrate 300 between the outer edge of the side furthest from the output matching circuit 166 among the two sides of the smallest rectangle surrounding inductor L1 along direction D2 and the outer edge P101 of the differential amplifier 16A.

[0141] In the second viewpoint of Modification 5, when viewed from the thickness direction of the mounting substrate 300, capacitor C1 is disposed between the output matching circuit 166 and the differential amplifier 16A (see reference). Figure 9 (A) In this case, when viewed from direction D2, capacitor C1 is disposed between the outer edge 1601 of differential amplifier 16A and the outer edge P101 of output matching circuit 166, and capacitor C1 is configured not to overlap with either differential amplifier 16A or output matching circuit 166. That is, when viewed from direction D2, capacitor C1 is disposed between the outer edge of differential amplifier 16A along direction D2 that is closer to output matching circuit 166 and the outer edge of output matching circuit 166 along direction D2 that is closer to differential amplifier 16A.

[0142] In the second viewpoint of Modification 5, capacitor C1 only needs to be positioned between the outer edge of the output matching circuit 166 furthest from the differential amplifier 16A (e.g., outer edge P101) and the outer edge 1601 of the differential amplifier 16A, which is located along the second direction when viewed from direction D2. Therefore, the arrangement relationship of capacitor C1, output matching circuit 166, and differential amplifier 16A when viewed from the mounting substrate 300 in the arrangement direction D1 is not specified. That is, in the second viewpoint of Modification 5, it is not necessary for at least a portion of capacitor C1 to overlap with the output matching circuit 166 when viewed from the arrangement direction D1. Furthermore, in the second viewpoint of Modification 5, it is also not necessary for at least a portion of capacitor C1 to overlap with the differential amplifier 16A.

[0143] According to the second viewpoint of Modification 5, when viewed from direction D2, capacitor C1 is positioned between the outer edge 1601 of the differential amplifier 16A and the outer edge P101 of the output matching circuit 166. Therefore, compared to the case where capacitor C1 is positioned on the opposite side of the differential amplifier 16A relative to the outer edge P101 of the output matching circuit 166, the lengths of inductors La1 and La2, as well as the lengths of inductors Lc1 and Lc2, can be shortened. That is, the path length between the first output terminal 161b and capacitor C1, and the path length between the second output terminal 162b and capacitor C1, can be shortened. Consequently, the inductance values ​​of inductors La1 and La2 can be reduced. Furthermore, the inductance values ​​of inductors Lc1 and Lc2 can be reduced. As a result, the error between the impedance value and the impedance design of the high-frequency circuit 10 can be minimized.

[0144] In the second viewpoint of Modification 5, each inductor in the output matching circuit 166, from L1 to L4, has a structure formed by a conductor pattern portion, but is not limited to this structure. Similar to the first viewpoint of Modification 5, each inductor in L1 to L4 can also be formed by a chip inductor. Alternatively, the output matching circuit 166 can also be monolithically processed.

[0145] (Summarize)

[0146] As described above, the high-frequency circuit (10) of the first embodiment includes a differential amplifier circuit (16). The differential amplifier circuit (16) includes a first amplifying element (161), a second amplifying element (162), a first wiring (R1), a second wiring (R2), and a series circuit (165). The first amplifying element (161) has a first input terminal (161a) and a first output terminal (161b). The second amplifying element (162) has a second input terminal (162a) and a second output terminal (162b). The first wiring (R1) is connected to the first output terminal (161b). The second wiring (R2) is connected to the second output terminal (162b). The series circuit (165) is connected between the first wiring (R1) and the second wiring (R2). The series circuit (165) includes a first inductor (e.g., inductor Lc1), a second inductor (e.g., inductor Lc2), and a capacitor (C1).

[0147] According to this structure, when the series circuit (165) is set as a series resonant circuit, the harmonic components associated with the transmitted signal under differential amplification, such as the odd-order (e.g., 3rd) harmonic components of the frequency of the transmitted signal, can be attenuated.

[0148] In the second type of high-frequency circuit (10), compared with the first type, the differential amplifier circuit (16) further includes a third inductor (e.g., inductor La1) and a fourth inductor (e.g., inductor La2). The third inductor is connected between the first output terminal (161b) and the first wiring (R1). The fourth inductor is connected between the second output terminal (162b) and the second wiring (R2).

[0149] According to this structure, the phase of harmonic components, such as odd-order (e.g., 3rd) harmonic components of the frequency of the transmitted signal, can be adjusted.

[0150] In the third-mode high-frequency circuit (10), regarding the second mode, the inductance value of the third inductor is the same as that of the fourth inductor.

[0151] According to this structure, the difference between the impedance at the first output terminal (161b) and the impedance at the second output terminal (162b) can be made small.

[0152] In the high-frequency circuit (10) of the fourth mode, the inductance value of the first inductor is the same as that of the second inductor for any of the first to third modes.

[0153] According to this structure, the difference between the impedance at the first output terminal (161b) and the impedance at the second output terminal (162b) can be made small.

[0154] In the high-frequency circuit (10) of the fifth mode, the capacitor (C1) is a plate capacitor for any of the first to fourth modes.

[0155] Based on this structure, the Q value of the capacitor (C1) can be improved. Therefore, the attenuation of harmonic components can be enhanced. Furthermore, an improvement in insertion loss can be expected.

[0156] In the high-frequency circuit (10) of the sixth mode, for any of the first to fifth modes, the differential amplifier circuit (16) further includes a balun circuit (e.g., an output matching circuit 166). The balun circuit has an unbalanced terminal (166c) and a pair of balanced terminals (166a, 166b), which are connected to a first wiring (R1) and a second wiring (R2), respectively.

[0157] Based on this structure, for example, it is possible to output a signal that attenuates the odd-order harmonic components under differential amplification.

[0158] In the high-frequency circuit (10) of the seventh embodiment, the differential amplifier circuit (16) of the sixth embodiment further includes a series resonant circuit (167). One end of the series resonant circuit (167) is connected to the unbalanced terminal (166c). The series resonant circuit (167) includes an inductor (Lc3) and a second capacitor (e.g., capacitor C2), which is different from the first capacitor formed by the capacitor (C1) of the series circuit (165).

[0159] According to this structure, when the series resonant circuit (167) is set as a resonant circuit, the harmonic components associated with the transmitted signal under differential amplification, such as the even-order (e.g., 2nd) harmonic components of the frequency of the transmitted signal, can be attenuated.

[0160] Regarding any of the first to seventh methods, the high-frequency circuit (10) of the eighth method further includes a mounting substrate (300). The differential amplifier circuit (16) includes a differential amplifier (16A) and an output matching circuit (166). The differential amplifier (16A) includes a first amplifying element (161) and a second amplifying element (162). The mounting substrate (300) is configured with a capacitor (C) included in a series circuit (165), the differential amplifier (16A), and the output matching circuit (166). The output matching circuit (166) is connected to a first output terminal (161b) and a second output terminal (162b). When viewed from the arrangement direction (D1) of the output matching circuit (166) and the differential amplifier (16A), a first portion of the capacitor (C1) included in the series circuit (165) overlaps with the output matching circuit (166), and a second portion of the capacitor (C1) overlaps with the differential amplifier (16A).

[0161] According to this structure, the balance between the lengths from the first output terminal (161b) to the capacitor (C1) and the lengths from the second output terminal (162b) to the capacitor (C1) can be adjusted. As a result, the operation during communication can be stabilized.

[0162] In the high-frequency circuit (10) of the ninth mode, regarding the eighth mode, when viewed from the above arrangement direction (D1), the capacitor (C1) overlaps with at least one of the output matching circuit (166) and the differential amplifier (16A).

[0163] This structure enables further stabilization of actions during communication.

[0164] In the high-frequency circuit (10) of the tenth mode, regarding the eighth or ninth mode, when viewed from the thickness direction of the mounting substrate (300), the center (P2) of the capacitor (C1) and the center of at least one of the output matching circuit (166) and the differential amplifier (16A) are arranged along the arrangement direction (D1).

[0165] According to this structure, the length from the first output terminal (161b) to the capacitor (C1) can be made the same as the length from the second output terminal (162b) to the capacitor (C1). As a result, the operation during communication can be stabilized.

[0166] Regarding any of the first to tenth embodiments, the high-frequency circuit (10) of the eleventh embodiment further includes a mounting substrate (300). The differential amplifier circuit (16) includes a differential amplifier (16A) and an output matching circuit (166). The differential amplifier (16A) includes a first amplifying element (161) and a second amplifying element (162). The output matching circuit (166) is connected to a first output terminal (161b) and a second output terminal (162b). The mounting substrate (300) is configured with a capacitor (C1) included in the series circuit (165), the differential amplifier (16A), and the output matching circuit (166). When viewed from a second direction (e.g., direction D2) orthogonal to both the thickness direction and the first direction of the mounting substrate (300), a capacitor (C1) included in the series circuit (165) is disposed on the mounting substrate (300) between the outer edge (P101) of the output matching circuit (166) far from the differential amplifier (16A) and the outer edge (1601) of the differential amplifier (16A) far from the output matching circuit (166) along the second direction, wherein the first direction is the arrangement direction (D1) of the output matching circuit (166) and the differential amplifier (16A).

[0167] According to this structure, the path length between the first output terminal (161b) and the capacitor (C1) and the path length between the second output terminal (162b) and the capacitor (C1) can be shortened. That is, the inductance value on the path between the first output terminal (161b) and the capacitor (C1) and the path between the second output terminal (162b) and the capacitor (C1) can be reduced. As a result, the error between the impedance value and the impedance design of the high-frequency circuit (10) can be reduced.

[0168] In the high-frequency circuit (10) of the twelfth mode, regarding the eleventh mode, when the mounting substrate (300) is viewed from the thickness direction of the mounting substrate (300), the capacitor (C1) is disposed between the output matching circuit (166) and the differential amplifier (16A).

[0169] According to this structure, the result is that the error between the impedance value and the impedance design of the high-frequency circuit (10) can be further reduced.

[0170] The communication device (500) of the thirteenth mode includes: a high-frequency circuit (10) of any one of the first to twelfth modes; and a signal processing circuit (2) connected to the high-frequency circuit (10).

[0171] According to this structure, it is possible to attenuate the harmonic components associated with the transmitted signal under differential amplification, such as the odd-order (e.g., 3rd) harmonic components of the frequency of the transmitted signal.

[0172] Explanation of reference numerals in the attached figures

[0173] 1: High-frequency module; 2: Signal processing circuit; 3: Antenna; 10: High-frequency circuit; 11: Switch; 12: First matching circuit; 13: Second matching circuit; 14: Transmit filter; 15: Receive filter; 16: Differential amplifier circuit; 16A: Differential amplifier; 17: Third matching circuit; 18: Low-noise amplifier; 20: Antenna terminal; 111: Common terminal; 112: Selection terminal; 113: Selection terminal; 161: First amplifying element; 161a: First input terminal; 161b: 162: First output terminal; 162: Second amplifying element; 162a: Second input terminal; 162b: Second output terminal; 163: Third amplifying element; 164: Interstage balun circuit; 164a: Unbalanced terminal; 164b, 164c: Balanced terminals; 165: Series circuit; 166: Output matching circuit (balun circuit); 166a, 166b: Balanced terminals; 166c: Unbalanced terminal; 167: Series resonant circuit; 201: Baseband signal processor 202: RF signal processing circuit; 300: Mounting substrate; 300a: First layer; 300b: Second layer; 300c: Third layer; 301: Main surface; 302: Dielectric layer; 500: Communication device; 1601, L1a, L1b, L2a, L2b, L3a, L4a, P101: Outer edge; B1, B2, B11, B12, B20, B21, B22: Path; C1: Capacitor (first capacitor); C2: Capacitor; C3: Capacitor (second capacitor) D1: Arrangement direction (direction, first direction); D2: Direction (second direction); H1: Straight line; L1, L2, L3, L4: Inductors; L10: Primary side coil; L11: Secondary side coil; Lc1: Inductor (first inductor); Lc2: Inductor (second inductor); Lc3: Inductor; La1: Inductor (third inductor); La2: Inductor (fourth inductor); P1, P2, P3: Center; P10: Rectangle; R1: First wiring; R2: Second wiring.

Claims

1. A high-frequency circuit, wherein, Equipped with a differential amplifier circuit, The differential amplifier circuit includes: The first amplifying element has a first input terminal and a first output terminal; The second amplifying element has a second input terminal and a second output terminal; The first wiring is connected to the first output terminal; The second wiring is connected to the second output terminal; A series circuit, which is connected between the first wiring and the second wiring; A third inductor is connected between the first output terminal and the first wiring; and A fourth inductor is connected between the second output terminal and the second wiring. The series circuit includes a first inductor, a second inductor, and a capacitor. The high-frequency circuit also includes a mounting substrate. The differential amplifier circuit includes: A differential amplifier, comprising the first amplifying element and the second amplifying element; and An output matching circuit is connected to the first output terminal and the second output terminal. The differential amplifier, the output matching circuit, and the capacitor included in the series circuit are disposed on the mounting substrate. When viewed from the arrangement direction of the output matching circuit and the differential amplifier, a first portion of the capacitor included in the series circuit overlaps with the output matching circuit, and a second portion of the capacitor overlaps with the differential amplifier. The third inductor and the fourth inductor are disposed as conductor pattern portions in the dielectric layer inside the mounting substrate. When viewed from the thickness direction of the mounting substrate, the third inductor and the fourth inductor are arranged linearly symmetrically with respect to an axis passing through the center of the capacitor and along the arrangement direction of the output matching circuit and the differential amplifier.

2. The high-frequency circuit according to claim 1, wherein, The inductance value of the third inductor is the same as that of the fourth inductor.

3. The high-frequency circuit according to claim 1 or 2, wherein, The inductance value of the first inductor is the same as the inductance value of the second inductor.

4. The high-frequency circuit according to claim 1 or 2, wherein, The capacitor is a surface-mount capacitor.

5. The high-frequency circuit according to claim 1 or 2, wherein, The differential amplifier circuit further includes a balun circuit, which has an unbalanced terminal and a pair of balanced terminals, the pair of balanced terminals being connected to the first wiring and the second wiring respectively.

6. The high-frequency circuit according to claim 5, wherein, The differential amplifier circuit also includes a series resonant circuit with one end connected to the unbalanced terminal. The series resonant circuit includes a second capacitor and an inductor, the second capacitor being different from the first capacitor formed by the capacitors in the series circuit.

7. The high-frequency circuit according to claim 1, wherein, When viewed from the arrangement direction, the capacitor overlaps with at least one of the output matching circuit and the differential amplifier.

8. The high-frequency circuit according to claim 1 or 7, wherein, When viewed from the thickness direction of the mounting substrate, the center of the capacitor is aligned with the center of at least one of the output matching circuit and the differential amplifier along the arrangement direction.

9. The high-frequency circuit according to claim 1 or 2, wherein, Viewed from a second direction orthogonal to both the thickness direction of the mounting substrate and the first direction, the capacitor included in the series circuit is disposed on the mounting substrate between the outer edge of the output matching circuit along the second direction that is farthest from the differential amplifier and the outer edge of the differential amplifier along the second direction that is farthest from the output matching circuit. The first direction is the arrangement direction of the output matching circuit and the differential amplifier.

10. The high-frequency circuit according to claim 9, wherein, When viewed from the thickness direction of the mounting substrate, the capacitor is positioned between the output matching circuit and the differential amplifier.

11. A communication device comprising: The high-frequency circuit according to any one of claims 1 to 10; and A signal processing circuit, which is connected to the high-frequency circuit.

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