Symbol and timing recovery apparatus and related methods

Abstract

An example device (102) includes a feed forward equalizer (FFE) (122) having an FFE output, a summer circuit (124) having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output, a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second summer input, and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

Description

TECHNICAL FIELD

[0001] This description generally relates to symbol and timing recovery, and more particularly to symbol and timing recovery devices and related methods. BACKGROUND

[0002] Some wireless and wired receivers, such as Ethernet physical layers (PHYs), perform symbol and timing recovery techniques to facilitate communication between devices. Some Ethernet PHYs are oversampled systems that use robust clock synchronization techniques to achieve robust timing loop synchronization performance, which is a parameter associated with improved link-up time and bit error rate (BER) performance. Some such Ethernet PHYs utilize a one-sample-per-symbol system architecture to reduce cost in terms of area and power. Some such Ethernet PHYs do not have robust timing loop synchronization performance. SUMMARY

[0003] For symbol and timing recovery devices and related methods, one example device includes a feed forward equalizer (FFE) having an FFE output; a summer circuit having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output; a multiplexer (MUX) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output; a decision feedback equalizer (DFE) having a DFE output coupled to the second summer input; and a timing error detector (TED) having a first TED input coupled to the MUX output. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 is a block diagram of an example implementation of a communication system that utilizes a digital signal processor (DSP) that includes a timing error detector (TED) that can implement symbol and timing recovery techniques.

[0005] Figure 2 is a block diagram of an example implementation of a TED of Figure 1

[0006] Figure 3 is an example pseudo code that can be executed by a DSP of Figure 1 and / or a TED of Figure 1 and / or 2 to perform a first example symbol and timing recovery technique.

[0007] Figure 4 is an example pseudo code that can be executed by a DSP of Figure 1 and / or a TED of Figure 1 ​The TED execution of 2 and / or 2 is used to execute the second instance symbol and the second timing diagram and instance pseudocode of the timing recovery technique.

[0008] Figure 5 It is possible to be Figure 1 DSP and / or Figure 1 The TED execution of 2 and / or 2 is used to execute the third timing diagram and instance pseudocode of the third instance symbol and timed recovery technique.

[0009] Figure 6 It is a first graph containing the first instance waveform of the first instance frequency-locking operation used to depict different symbols and timing recovery techniques.

[0010] Figure 7 It is a second graph containing a second instance waveform used to depict the instance frequency-locking operation of different symbols and timing recovery techniques.

[0011] Figure 8 yes Figure 1 A block diagram of another implementation scheme for a communication system.

[0012] Figure 9 yes Figure 8 The graph shows the inter-symbol interference of the DSP instance operation.

[0013] Figure 10 yes Figure 8 The time loop convergence curve of the DSP instance operation.

[0014] Figure 11 yes Figure 8 The timing error of the DSP instance operation relative to the gain is plotted.

[0015] Figure 12 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, which are configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices are used to perform the symbol and timing recovery techniques described herein.

[0016] Figure 13 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, which are configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices to perform Figure 3 The first symbol and timed recovery technology.

[0017] Figure 14 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, wherein the machine-readable instructions are executable and / or the hardware is configured to implement...Figure 1 an example DSP and / or (more generally) an example Ethernet PHY device to perform Figure 4 a second symbol and timing recovery technique.

[0018] Figure 15 is a flowchart representing an example process that can be performed using machine-readable instructions and / or hardware configured to implement Figure 1 an example DSP and / or (more generally) an example Ethernet PHY device to perform Figure 5 a third symbol and timing recovery technique.

[0019] The same reference numerals or other reference designators in the drawings and the specification indicate functional and / or structural analogous elements. DETAILED DESCRIPTION

[0020] Digital communication systems can utilize modulation techniques such as pulse amplitude modulation (PAM) to communicate data between devices, such as communication devices. PAM utilizes symbols to enable data communication. A symbol can refer to a waveform that represents one or more bits. For example, a symbol can be one or more pulses of a pulse train, and one (or more) of the one or more pulses (i.e., the symbol) can be mapped to one or more data bits.

[0021] The transmitted or received symbols utilized in PAM techniques represent different possible levels based on the amplitude of the transmitted or received pulses. Different PAM techniques exist and are identified based on a modulation level identifier (e.g., PAM3, PAM5, PAM16, etc.). For example, PAM3 can utilize symbols that represent one of three levels: -1, 0, or +1. In some such examples, the value -1 is assigned and / or otherwise corresponds to a first amplitude (or voltage), the value 0 is assigned and / or otherwise corresponds to a second amplitude (or voltage), and the value +1 is assigned and / or otherwise corresponds to a third amplitude (or voltage). In some such examples, the third amplitude is greater than the second amplitude, and the second amplitude is greater than the first amplitude.

[0022] Some digital communication systems can operate based on an Ethernet communication protocol. For example, an Ethernet PHY device is a transceiver that receives and / or transmits data according to an Ethernet communication protocol. Some digital communication systems utilize a Mueller-Muller (M&M) timing synchronization technique to enable symbol and timing recovery of received data. For example, a first Ethernet PHY device can transmit data by placing symbols on a communication channel at a fixed and known symbol rate, and a second Ethernet PHY device can receive data by detecting a sequence of symbols to reconstruct the transmitted data. The second Ethernet PHY device can utilize the M&M timing synchronization technique to reconstruct the transmitted data.

[0023] M&M techniques rely on inter-symbol interference (ISI) present at the output of an analog-to-digital converter (ADC) in a digital communication system. ISI is a form of signal distortion in which one symbol interferes with a subsequent symbol. M&M techniques balance the ISI of the post-cursor symbol (P+1) and pre-cursor symbol (P-1) to the same level to achieve timing synchronization. M&M techniques seek to achieve timing synchronization to the optimal eye opening point of an eye diagram, which can be generated by superimposing different portions of a waveform representing different symbols. However, M&M technique-based digital communication systems achieve lock (e.g., loop lock, timing loop lock, etc.) based on ISI. For communication channels with low ISI, M&M technique-based digital communication systems can experience an unstable link-up for a significant period of time until lock is achieved, which reduces the efficiency and / or performance of such systems.

[0024] Examples described herein include a communication device, such as a transceiver (e.g., an Ethernet PHY device), that performs improved symbol and timing recovery techniques. In some described examples, a communication device can perform improved symbol and timing recovery techniques to achieve faster loop lock performance independent of channel length or ISI distribution. For example, a communication device can perform a first symbol and timing recovery technique described herein to utilize PAM symbol transitions to determine a timing error. The communication device can use the timing error to generate a timing error signal, which can be incorporated into a timing lock loop for synchronization purposes. In response to the timing error signal, the communication device can adjust a sampling rate, phase (e.g., timing phase), etc. of a clock (e.g., a clock signal, a sampling clock, etc.) of an ADC of the communication device.

[0025] In some described examples, a communication device can perform a second symbol and timing recovery technique to interpolate adjacent samples, which can be used to generate an approximate differential sample. As used herein, interpolation refers to constructing new data points based on a range of a set of discrete known data points. For example, a communication device can use a transition between sampled PAM symbols to determine a new sample (e.g., a differentiator output), which can be used to determine a timing error and a corresponding timing error signal. In some such examples, the communication device can identify the transition as a peak symbol point transition or a valley symbol point transition to enable interpolation.

[0026] In some described examples, a communication device can perform a third symbol and timing recovery technique to interpolate samples to mid-value or midpoint values of sampled PAM symbols to compare transitions between sampled PAM symbols to expected mid-value or midpoint values. For example, a communication device can use a transition between PAM symbols to determine a direction of a timing error and a corresponding timing error signal to enable interpolation.

[0027] Figure 1 is a block diagram of an example communication system (e.g., a digital communication system) 100 that includes an example digital signal processor (DSP) 102. In some examples, the DSP 102 and / or (more generally) the communication system 100 can be an Ethernet PHY device. The communication system 100 includes an example high pass filter (HPF) 104, an example low pass filter (LPF) 106, an example analog-to-digital converter (ADC) 108, and an example phase interpolator circuit 110. In some examples, the LPF 106 can be an amplifier, such as a programmable gain amplifier or a variable gain amplifier. The HPF 104 is coupled to a communication channel (e.g., an Ethernet cable) to receive an example receive (RX) input 112. For example, the RX input 112 can be an analog communication signal based on an Ethernet communication protocol.

[0028] The DSP 102 includes an example DC cancellation circuit 114 (e.g., for direct current voltage and / or direct current current cancellation), an example coded automatic gain controller (CAGC) 116, an example digital automatic gain controller (DAGC) 118, an example de- equalizer (identified by DEQ) 120 (e.g., a de-equalizer circuit), an example feed forward equalizer (FFE) 122, an example adder circuit 124, an example multiplexer 126, an example slicer circuit (e.g., a data slicer circuit) 128, an example decision feedback equalizer (DFE) 130, an example gain loop circuit 132, an example mean squared error circuit 134, an example timing error detector (TED) 136 (e.g., a TED circuit), an example loop filter 138, an example numerically controlled oscillator (NCO) 140, and an example sequencer circuit 142. Alternatively, the DSP 102 can include fewer or more hardware components than depicted in this example. For example, although the HPF 104, the LPF 106, the ADC 108, and the phase interpolator circuit 110 are depicted as separate from the DSP 102, in some examples at least one of the HPF 104, the LPF 106, the ADC 108, or the phase interpolator circuit 110 can be included in the DSP 102. In this example, the DSP 102 and / or (more generally) the communication system 100 implements a phase-locked loop (PLL) 144 (e.g., a phase-locked loop circuit). The PLL 144 includes the phase interpolator circuit 110, the loop filter 138, and the NCO 140. Alternatively, the PLL 144 can include fewer or more hardware components than depicted in this example. Figure 1 For example, although the HPF 104, the LPF 106, the ADC 108, and the phase interpolator circuit 110 are depicted as separate from the DSP 102, in some examples at least one of the HPF 104, the LPF 106, the ADC 108, or the phase interpolator circuit 110 can be included in the DSP 102. In this example, the DSP 102 and / or (more generally) the communication system 100 implements a phase-locked loop (PLL) 144 (e.g., a phase-locked loop circuit). The PLL 144 includes the phase interpolator circuit 110, the loop filter 138, and the NCO 140. Alternatively, the PLL 144 can include fewer or more hardware components than depicted in this example. Figure 1 For example, although the HPF 104, the LPF 106, the ADC 108, and the phase interpolator circuit 110 are depicted as separate from the DSP 102, in some examples at least one of the HPF 104, the LPF 106, the ADC 108, or the phase interpolator circuit 110 can be included in the DSP 102. In this example, the DSP 102 and / or (more generally) the communication system 100 implements a phase-locked loop (PLL) 144 (e.g., a phase-locked loop circuit). The PLL 144 includes the phase interpolator circuit 110, the loop filter 138, and the NCO 140. Alternatively, the PLL 144 can include fewer or more hardware components than depicted in this example.

[0029] In some examples, the communication system 100 implements a clock and data recovery (CDR) circuit 146. The CDR circuit 146 includes the HPF 104, the LPF 106, the ADC 108, the phase interpolator circuit 110, the PLL 144, the CAGC 116, the DAGC 118, the DEQ 120, the FFE 122, the adder circuit 124, the multiplexer 126, the slicer circuit 128, the DFE 130, the gain loop circuit 132, the mean squared error circuit 134, the TED 136, the loop filter 138, the NCO 140, and the sequencer circuit 142. Figure 1In the illustrated example, an input of the HPF 104 is coupled to a terminal adapted to receive the RX input 112. An output of the HPF 104 is coupled to an input of the LPF 106. An output of the LPF 106 is coupled to an input (e.g., an ADC input) of the ADC 108. An output (e.g., an ADC output) of the ADC 108 is coupled to an input of the DC removal circuit 114, an input of the CAGC 116, and / or (more generally) an input of the DSP 102. An output of the CAGC 116 is coupled to circuitry external to the DSP 102. An output of the DC removal circuit 114 is coupled to an input of the DAGC 118. An output of the DAGC 118 is coupled to an input of the DEQ 120. An output of the DEQ 120 is coupled to an input (e.g., an FFE input) of the FFE 122. An output (e.g., an FFE output) of the FFE 122 is coupled to an input (e.g., an adder input, an adder circuit input, etc.) of the adder circuit 124 and a second input of the multiplexer 126. An output (e.g., an adder output, an adder circuit output, etc.) of the adder circuit 124 is coupled to a first input of the multiplexer 126, an input of the slicer circuit 128, an input of the DFE 130, an input of the gain loop circuit 132, and an input of the MSE 134 circuit. An output of the multiplexer 126 is coupled to an input (e.g., a TED input) of the TED 136. Alternatively, the DSP 102 can not include the multiplexer 126. For example, an output of the FFE 122 and / or the adder circuit 124 can be coupled to the input of the TED 136.

[0030] Outputs (e.g., slicer outputs) of the slicer circuit 128 are coupled to circuitry external to the DSP 102. For example, the outputs of the slicer circuit 128 can be coupled to a memory (and / or a memory controller) to store decisions (e.g., data slicing decisions) in the memory, which can be accessible by one or more processors. The outputs of the slicer circuit 128 are coupled to inputs (e.g., DFE inputs) of the DFE 130, inputs of the gain loop circuit 132, inputs of the MSE circuit 134, and inputs of the TED 136. Outputs (e.g., DFE outputs) of the DFE 130 are coupled to inputs of the summer circuit 124. Outputs of the gain loop circuit 132 are coupled to inputs of the DAGC 118. Outputs (e.g., TED outputs) of the TED 136 are coupled to inputs (e.g., loop filter inputs) of the loop filter 138 and / or (more generally) inputs (e.g., PLL inputs) of the PLL 144. Outputs (e.g., loop filter outputs) of the loop filter 138 are coupled to inputs (e.g., NCO inputs) of the NCO 140. Outputs (e.g., NCO outputs) of the NCO 140 are coupled to inputs (e.g., phase detector inputs, phase interpolator inputs, etc.) of the phase interpolator circuit 110. Outputs (e.g., phase detector outputs, phase interpolator outputs, etc.) of the phase interpolator circuit 110 and / or (more generally) outputs (e.g., PLL outputs) of the PLL 144 are coupled to inputs of the ADC 108.

[0031] The DSP 102 and / or (more generally) the communication system 100 can perform the example symbol and timing recovery techniques described herein. In an example operation, the HPF 104, which can be implemented as a digital filter or an analog filter, for example, receives and / or otherwise obtains the RX input 112. For example, the HPF 104 can receive the RX input 112 from another device, such as a communication device, an Ethernet PHY device, etc. The HPF 104 attenuates frequencies of the RX input 112 that are below a first cutoff frequency of the HPF 104. The HPF 104 passes frequencies of the RX input 112 that are above the first cutoff frequency to the LPF 106, which can be implemented as a digital filter or an analog filter, for example. The LPF 106 attenuates frequencies of the RX input 112 that are greater than a second cutoff frequency of the LPF 106 and passes frequencies of the RX input 112 that are below the second cutoff frequency to the ADC 108. In alternative embodiments, a RF sampling ADC, such as a delay-based ADC, can be connected directly to the RX input 112 and filtering can be done using a digital filter after the RX input 112 is converted from analog to digital. The ADC 108 converts the filtered RX input 112 to a digital signal. In this example, the ADC 108 samples the RX input 112 at a sampling rate of about one sample per second (e.g., sampling one symbol per sample). Alternatively, the ADC 108 can sample the RX input 112 at any other sampling rate. The CAGC 116 amplifies the digital signal to output an amplified digital signal. For example, the CAGC 116 can determine a power of the digitized signal and adjust an analog gain accordingly (e.g., by changing an attenuation or gain of the HPF 104 or the LPF 106) to bring the digitized signal to a desired level at an input of the ADC 108, thereby increasing and / or otherwise maximizing a signal-to-noise ratio (SNR). The DC removal circuit 114 can be one or more filters to remove DC bias from an output of the ADC 108. The DAGC 118 can produce an output to the DEQ 120 based on a multiplication (or product) of an output from the DC removal circuit 114 and an output from the gain loop circuit 132. For example, the DAGC 118 can amplify the digital signal to a predetermined level at an input of the slicer circuit 128. The DEQ 120 can include one or more filters to filter an output from the DAGC 118.

[0032] In example operations, FFE 122 equalizes a communication channel of communication system 100. FFE 122 recovers data from RX input 112. For example, FFE 122 can generate a first example symbol 146 (identified by x(n)) based on output from DEQ 120. Adder circuit 124 can generate a second example symbol 148 (identified by y(n)) based on a difference in values of first symbol 146 and output of DFE 130. For example, FFE 122 can generate first symbol 146 as an uncorrected symbol, and adder circuit 124 can generate second symbol 148 as a corrected symbol.

[0033] In example operations, DFE 130 can predict, identify, and / or otherwise determine a noise level of a communication channel based on previous samples (e.g., previous values of first symbol 146 and / or second symbol 148). For example, DFE 130 can output a noise error (e.g., a noise error signal) to adder circuit 124 to correct second symbol 148, and thereby generate a DFE-corrected symbol. Advantageously, adder circuit 124 can subtract the predicted noise level output from DFE 130 from first symbol 146. Slicer circuit 128 performs slicing on second symbol 148 using one or more thresholds (e.g., one or more threshold values). For example, slicer circuit 128 can generate a first output (also referred to as a decision, a data decision, a symbol decision, etc.) in response to determining that an amplitude of second symbol 148 is greater than a first threshold, a second output in response to determining that the amplitude is greater than a second threshold, etc. In some such examples, slicer circuit 128 can generate a third example symbol 150 based on the determinations For example, slicer circuit 128 can generate third symbol 150 to have one of PAM levels (e.g., levels -1, 0, +1 of PAM3).

[0034] In example operations, the gain loop circuit 132 can output a gain (e.g., a voltage, a signal, etc. representative of a gain value) to the DA GC 118 to adjust and / or otherwise modify an input to the DEQ 120. For example, the gain loop circuit 132 can output a gain based on the second symbol 148 and / or the third symbol 150. The MSE circuit 134 can output an MSE (e.g., a voltage, a signal, etc. representative of an MSE). For example, the MSE circuit 134 can determine a difference between an input to the slicer circuit 128 and an output of the slicer circuit 128 to determine a noise associated with the DSP 102, e.g., a noise of a communication channel processed by the DSP 102. In some such examples, the MSE circuit 134 can determine whether a desired SNR of the input to the slicer circuit 128 satisfies a threshold (e.g., an SNR threshold, a noise energy threshold, etc.). For example, in response to the SNR of the input to the slicer circuit 128 being less than the threshold, the sequencer circuit 142 can advance to a subsequent state. In some examples, in response to the SNR of the input to the slicer circuit 128 being greater than the threshold, the sequencer circuit 142 can revert to a previous state to enable re-convergence of timing lock. In some examples, the threshold can be user-defined (e.g., preprogrammed, configured, etc. prior to the DSP 102 processing a communication channel). In some examples, the threshold can be dynamically adjusted by the sequencer circuit 142. For example, the sequencer circuit 142 can adjust the threshold based on a historical SNR of the DSP (e.g., an SNR of the DSP 102 over one or more previous clock cycles).

[0035] In example operations, the multiplexer 126 selects whether to output the first symbol 146 or the second symbol 148 to the TED 136. In some examples, an input (e.g., a control or select input) of the multiplexer 126 is coupled to an output (e.g., a sequencer output) of the sequencer circuit 142. In some examples, the sequencer circuit 142 can be a logic circuit, machine-readable instructions, a hardware-implemented state machine, a processing circuit, and / or any other combination thereof. For example, the sequencer circuit 142 can be one or more analog and / or digital circuits. In some examples, in response to determining that the PLL 144 has not achieved timing lock, the sequencer circuit 142 can instruct the multiplexer 126 to select the first symbol 146. In some examples, in response to determining that the PLL 144 has achieved timing lock (e.g., timing loop lock), the sequencer circuit 142 can instruct the multiplexer 126 to select the second symbol 148. In some examples, the TED 136 can determine a first timing error based on an uncorrected symbol (e.g., the first symbol 146) before the PLL 144 achieves timing lock, and determine a second timing error based on a corrected symbol (e.g., the second symbol 148) in response to the PLL 144 achieving timing lock. Advantageously, after the PLL 144 achieves timing lock, the output from the DFE 130 converges to a steady state or stable value. In response to the convergence of the output of the DFE 130, the TED 136 can be switched to use the DFE-corrected symbol (or partially corrected DFE symbol) to achieve improved noise variance (e.g., lower noise variance).

[0036] In example operations, the TED 136 outputs a timing error (e.g., a voltage, a timing error signal, etc.) based on the first symbol 146, the second symbol 148, and / or the third symbol 150. For example, the TED 136 can output the timing error by utilizing one or more of the symbols and the timing recovery techniques described herein. In some examples, an input (e.g., a control input, a select input, etc.) of the TED 136 is coupled to an output of the sequencer circuit 142. For example, the sequencer circuit 142 can instruct the TED 136 to use the first symbol 146, the second symbol 148, and / or the third symbol 150 to generate the timing error. The loop filter 138 can filter the timing error and provide the filtered timing error to the NCO 140.

[0037] In some instances, NCO 140 may be an accumulator (e.g., a digital phase accumulator). For example, the accumulator may increment or decrement the accumulator value from an initial value (e.g., 0 or zero) and generate an instance control signal 152 (identified by phase rise / fall) in response to the accumulator value satisfying a threshold. In some instances, NCO 140 may generate control signal 152 to increase or decrease the phase of the clock that samples the RX input 112 by the ADC 108. In some instances, phase interpolator circuit 110 may be a phase detector. For example, phase interpolator circuit 110 may detect the phase of control signal 152 and, based on the detected phase of control signal 152, instruct ADC 108 to increase the phase of a clock that may be a portion of the clock of ADC 108. In some instances, phase interpolator circuit 110 may instruct ADC 108 to decrease the phase of the clock based on control signal 152.

[0038] Figure 2 This is a block diagram of an example of TED 200. In some instances, TED 200 can be implemented. Figure 1 The TED 136. The TED200 includes an instance multiplexer 202 and an instance latch 204. The latch 204 is a D flip-flop. Alternatively, the latch 204 can be a set-reset (SR) flip-flop, a JK flip-flop, or a T flip-flop. In some instances, the first input (identified by x(n-1)) and the second input (identified by -x(n-1)) of the multiplexer 202 can be coupled to Figure 1 The output of the multiplexer 126 (e.g., multiplexer output, MUX output, etc.). For example, x(n-1) and -x(n-1) can be the previous symbols. In some such instances, x(n-1) can be... Figure 1 The previous value of the first symbol 146, the previous value of the second symbol 148, etc. The third input of multiplexer 202 (e.g., multiplexer input, MUX input, etc.) is coupled to the output of latch 204 (e.g., latch output), such that the input of multiplexer 202 can be the previous output of multiplexer 202. In some instances, the control or selection input of multiplexer 202 (e.g., MUX control input) (identified by mux_sel) is coupled to... Figure 1 The output of sequencer circuit 142. The output of multiplexer 202 is coupled to the input of latch (e.g., latch input). The clock input of latch 204 can be adapted to receive a clock signal, which can be obtained from... Figure 1 The sequencer circuit 142 outputs. The output of multiplexer 202 (identified by ted(n)) is coupled to... Figure 1 The input of the loop filter 138 and / or (more generally) the input of the PLL 144.

[0039] In example operations, when the TED 200 does not detect a timing error, the TED 200 outputs a “0” as an example timing error 206 (identified by ted(n)). If the TED 200 detects a timing error, the TED 200 outputs a timing error 206 for the ADC 108 to sample on the left or right side of a desired sampling point. Accordingly, the TED 200 outputs a timing error 206 with a direction (e.g., whether to sample on the left or right side of a desired sampling point).

[0040] The TED 200 of the illustrated example can perform one or more symbol and timing recovery techniques to generate the timing error 206. For example, the timing error 206 can represent a time difference between a previously detected symbol and a currently detected symbol. When a -1, 0, +1 symbol transition (e.g., ) of the RX input 112 is detected, the TED 200 can instruct the multiplexer 202 to select 1. For example, the multiplexer 202 can output a positive value of the previously detected symbol. When a +1, 0, -1 symbol transition (e.g., ) of the RX input 112 is detected, the TED 200 can instruct the multiplexer 202 to select 2. For example, the multiplexer 202 can output a negative value of the previously detected symbol. In other cases, the TED 200 can instruct the multiplexer 202 to select 0. Alternatively, the TED 200 can use any other logic than the examples depicted in Figure 2 to control the multiplexer 202.

[0041] Figure 3 A first timing diagram 300 is depicted that corresponds to example operations of the TED 200 of Figure 2 , the TED 136 of Figure 1 , and / or (more generally) the DSP 102 of Figure 1 . Figure 3 The first example pseudocode 302 and the second example pseudocode 304 are further depicted in Figure 2 , the TED 136 of Figure 1 , and / or (more generally) the DSP 102 of Figure 1 . In some examples, the first pseudocode 302 and / or the second pseudocode 304 can be implemented by the DSP 102 to perform a first symbol and timing recovery technique. For example, the first symbol and timing recovery technique can be a constellation-based TED technique.

[0042] The first timing diagram 300 includes an example analog signal waveform 306 and an example pulse waveform 308. In some examples, the analog signal waveform 306 can be the RX input 112 of Figure 1 . In some examples, the pulse waveform 308 can be the ADC 108 ofFigure 1 The output of slicer circuit 128. For example, pulse waveform 308 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0043] In the example operation, Figure 1 TED 136 and / or Figure 2 The TED 200 can implement the first pseudocode 302 to determine the timing error (ted(n)). For example, the sequencer circuit 142 can determine... Figure 1 The current decision of the slicer circuit 128 (e.g., the current slicer decision). It's +1, the first previous slicer decision. It is 0, and the second previous slicer decision It is -1. In response to the determination that a sign transition of -1, 0, or +1 has been detected, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 1, causing the multiplexer 202 to select x(n-1). For example, the sequencer circuit 142 can select the input of TED 200. In some such instances, the sequencer circuit 142 can select either the first symbol 146 or the second symbol 148 based on the state of the sequencer circuit 142 (e.g., the sequencer state). Figure 1 TED 136 and / or Figure 2 The TED 200. Advantageously, the sequencer circuit 142 can select the first symbol 146 before the PLL 146 achieves timing lock, and select the second symbol 148 after the PLL 146 achieves timing lock to reduce noise after timing lock is achieved. Advantageously, the sequencer circuit 142 can instruct TED 136 and / or TED 200 to use the second symbol 148 after timing lock to reduce noise caused by ISI. In some instances, the timing error can be determined based on an example of the following equation (1):

[0044] Equation (1)

[0045] For example, in response to the determination of a positive or negative slope, the TED 200 can determine that the current timing error is the same as the previous slicer input. The TED 200 can determine a positive slope based on the sign transitions of -1, 0, and +1 (e.g., negative one, zero, and positive one values). The TED 200 can determine a negative slope based on the sign transitions of +1, 0, and -1 (e.g., positive one, zero, and negative one values). For example, x(n-1) can represent the timing error generated by the TED 200 in response to detecting a positive slope based on the sign transitions of -1, 0, and +1. Advantageously, Figure 1The PLL 144 can adjust the phase of the ADC 108 based on the timing error x(n-1) to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being described by reference numeral 310.

[0046] In the illustrated example, sequencer circuit 142 determines the current slicer decision of slicer circuit 128. It is -1, the first previous slicer decision. It is 0, and the second previous slicer decision It is +1. In response to the determination that a sign transition of +1, 0, or -1 has been detected, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 2, causing the multiplexer 202 to select -x(n-1). For example, the timing error can be determined based on an instance of equation (1) above. In some such instances, -x(n-1) can be the negative of the timing error generated by TED 200 in response to the detection of a negative slope based on the +1, 0, -1 sign transition. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on -x(n-1) to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being described by reference number 312.

[0047] In some instances, when the symbol transition referenced above is not detected, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 0, causing the multiplexer 202 to output a value of 0 when executing the first pseudocode 302. In some instances, TED 200 can be used when the symbol transition referenced above is not detected. Figure 2 The multiplexer 202's mux_sel produces a value of 0, causing the multiplexer 202 to output the previously generated timing error (identified by ted(n-1)) when executing the second pseudocode 304. Advantageously, in some such instances, maintaining the previous timing error value improves... Figure 1 TED136 and / or Figure 1 The gain of the TED 200, and will improve Figure 1 The locking capability of the PLL 144 (e.g., by locking faster). Advantageously, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 can determine timing errors by executing the first pseudocode 302 and / or the second pseudocode 304 using PAM sign transitions.

[0048] Figure 4Depicting the corresponding Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The second timing diagram 400 for the instance operation of DSP 102. Figure 4 The text further describes the first instance pseudocode 402 and the second instance pseudocode 404, which can be derived from... Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 is used to execute this. In some instances, the first pseudocode 402 and / or the second pseudocode 404 can be implemented by the DSP 102 to perform a second symbol and timing recovery technique. For example, the second symbol and timing recovery technique could be a pseudo maximum likelihood (ML) technique. In some such instances, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 can perform pseudo-ML techniques to interpolate samples to determine approximate difference samples based on an example of equation (2) below:

[0049] Equation (2)

[0050] In the example of equation (2) above, ted ML (n) is possible from Figure 1 TED 136 and / or Figure 2 The timing error generated by the TED 200. In the example of equation (2) above, x(n) is the currently uncorrected sign (e.g., Figure 1 The first symbol 146), and It is the derivative of the currently uncorrected sign. For example, in response to the detection of a peak sign point transition (e.g., a -1, +1, -1 sign point transition) or a valley sign point transition (e.g., a +1, -1, +1 sign point transition), the timing error is 0 because the derivative at the peak or valley sign point transition is 0. In other cases, the derivative is non-zero, which makes the timing error non-zero, and thus the TED 200 can indicate the direction of the timing error.

[0051] The second timing diagram 400 depicts an example analog signal waveform 406 and an example pulse waveform 408. In some instances, the analog signal waveform 406 may be... Figure 1 The RX input is 112. In some instances, the pulse waveform 408 can be... Figure 1 The output of slicer circuit 128. For example, pulse waveform 408 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0052] In example operations, Figure 1 TED 136 and / or Figure 2 TED 200 can implement the first pseudocode 402 to determine a timing error (ted pML (n)) for the current timing error approximation. For example, the sequencer circuit 142 can determine Figure 1 the current slicer decision of the slicer circuit 128 of the TED 136 and / or the first previous slicer decision is +1, and the second previous slicer decision is -1. In response to detecting a peak sign point transition based on the -1, +1, -1 sign transitions, the TED 136 and / or the TED 200 can generate the timing error based on examples of the following equation (3):

[0053] ted pML (n) = x(n - 1) * [x L (n - 1) - x E (n - 1)], equation (3)

[0054] In the example of the above equation (3), the difference between x L (n - 1) and x E (n - 1) is an approximation of the x(n - 1) derivative, and thus is the differentiator output. Alternatively, one or more filters can be used to determine the differentiator output. In some examples, x L may represent a first timing error approximation of the analog signal waveform 406 at the first example point 410, and x E may represent a second timing error approximation of the analog signal waveform 406 at the second example point 412. The differentiator outputs x L and x E may be determined based on examples of the following equations (4) and (5) included in the second pseudocode 404:

[0055] x L (n) = x(n) + μ[x(n + 1) - x(n)], equation (4)

[0056] x E (n) = x(n - 1) + μ[x(n) - x(n - 1)], equation (5)

[0057] In the example of the above equation (4), the value of μ can be controlled to determine an interpolation rate of the sign. In example operations, Figure 1 the sequencer circuit 142 of the TED 136 and / or Figure 1 the current slicer decision of the slicer circuit 128 of the TED 136 and / or the first previous slicer decision It is -1, and the second previous slicer decision It is +1. In response to the detection of a valley sign point transition based on the -1, +1, -1 sign transition, TED 136 and / or TED 200 can generate a timing error based on an instance of the following equation (6):

[0058] ted pML (n)=-1*{x(n-1)*[x L (n-1)-x E (n-1)]}, Equation (6)

[0059] In some instances, TED 136 and / or TED 200 can determine that neither peak sign point transitions nor valley sign point transitions are detected. In some such instances, when executing the second pseudocode 402, TED 136 and / or TED 200 can output the previously generated timing error (by TED). pML (n-1) recognition). Advantageously, in some such instances, maintaining the previous timing error value improves the gain of TED 136 and / or TED 200, and improves... Figure 1 The locking capability of the PLL 144 (e.g., by locking faster). Advantageously, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP102 can determine timing errors by executing the first pseudocode 302 and / or the second pseudocode 304 using PAM symbol transitions.

[0060] Figure 5 Depicting the corresponding Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The third timing diagram 500 for the instance operation of DSP 102. Figure 5 The example pseudocode 502 is further described, which can be derived from... Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1The DSP 102 is used to execute this. In some instances, the DSP 102 can utilize pseudocode 502 to execute a third symbol and timing recovery technique. For example, the third symbol and timing recovery technique could be the intermediate symbol TED technique. In some such instances, TED 136 and / or TED 200 can utilize pseudocode 502 to interpolate samples to the middle or midpoint of a symbol and compare the interpolation with the expected midpoint. Under these conditions, the comparison can be based on the PAM symbol transition. Alternatively, one or more filters can be used to determine the midpoint.

[0061] The third timing diagram 500 depicts an example analog signal waveform 504 and an example pulse waveform 506. In some instances, the analog signal waveform 504 may be... Figure 1 The RX input is 112. In some instances, the pulse waveform 506 can be... Figure 1 The output of slicer circuit 128. For example, pulse waveform 506 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0062] In the example operation, Figure 1 TED 136 and / or Figure 2 The TED 200 can execute pseudocode 502 to determine timing error (TED). midsym (n)). For example, sequencer circuit 142 can determine Figure 1 The current slicer decision of slicer circuit 128 It is +1, and the previous slicer decision. It is -1. For example, sequencer circuit 142 can determine the sign transition pair based on -1, +1. Figure 1 The third symbol 150 is a prediction or estimate of +1 that can indicate... Figure 1 The second symbol 148 is at the 0 symbol. Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the first instance symbol position 508. In response to identifying the first symbol position 508, TED 136 and / or TED 200 can determine the second symbol 148 based on x. midsym The difference between x and 0 produces a timing error, which is then used to determine the timing error as x. midsym In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being represented by the first symbol position 508.

[0063] In some instances, the sequencer circuit 142 can determine Figure 1the current slicer decision of the slicer circuit 128 of the TED 136 is -1, and the previous slicer decision is +1. For example, the sequencer circuit 142 can determine that a prediction or estimation that the third symbol 150 of the pair Figure 1 is -1 based on the +1, -1 symbol transition can indicate that the second symbol 148 of the pair Figure 1 is at a 0 symbol. Under these conditions, the TED 136 and / or the TED 200 can determine that the second symbol 148 is located at a second instance symbol location 510. In response to identifying the second symbol location 510, the TED 136 and / or the TED 200 can generate a timing error based on the difference between x midsym and 0, and thereby determine the timing error to be -x midsym In some examples, the timing error signal can be a waveform having an amplitude (e.g., voltage) representative of the timing error. Advantageously, Figure 1 the PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample a subsequent symbol of the RX input 112 at a correct phase, the symbol represented by the second symbol location 510.

[0064] In an example operation, the sequencer circuit 142 can determine that Figure 1 the current slicer decision of the slicer circuit 128 of the TED 136 is +1, and the previous slicer decision is 0. In response to detecting a 0, +1 symbol transition based on the determination, the TED 136 and / or the TED 200 generates a timing error based on the difference between x midsym and a coefficient of 0.5. Alternatively, the coefficient can be any other value. Under these conditions, the TED 136 and / or the TED 200 can determine that a prediction or estimation that the third symbol 150 of the pair Figure 1 is +1 based on the 0, +1 symbol transition can indicate that the second symbol 148 of the pair Figure 1 is in between (e.g., is a mid-symbol, is between the first symbol 0 and the second symbol +1, etc.). Under these conditions, the TED 136 and / or the TED 200 can determine that the second symbol 148 is located at a third instance symbol location 512. In this example, the third symbol location 512 is a mid-symbol location. In response to identifying the third symbol location 512, the TED 136 and / or the TED 200 can determine the timing error to be (x midsym - 0.5). In some examples, the timing error signal can be a waveform having an amplitude (e.g., voltage) representative of the timing error. Advantageously, Figure 1The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112, which are 0 symbols, in the correct phase.

[0065] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 It is 0, and the previous slicer decision It is +1. In response to the determination that a +1 or 0 sign transition was detected, TED 136 and / or TED 200 are based on x midsym A negative difference between the coefficient and 0.5 introduces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the +1, 0 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of 0 that can indicate Figure 1 The second symbol 148 is located between symbols (e.g., between a mid-symbol or intermediate symbol, between the first symbol +1 and the second symbol 0, etc.). Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the fourth instance symbol position 514. In this instance, the fourth symbol position 514 is an intermediate symbol position. In response to identifying the fourth symbol position 514, TED 136 and / or TED 200 can determine the timing error as -(x midsym -0.5). In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being the +1 symbols preceding the fourth symbol position 514.

[0066] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 It is -1, and the previous slicer decision It is 0. In response to the detection of a 0, -1 sign transition based on the determination, TED136 and / or TED 200 are based on x midsym The negative sum between the coefficient 0.5 and the coefficient 0.5 produces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the 0, -1 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of -1 that can indicate Figure 6the second symbol 148 is between symbols (e.g., is a mid-symbol, is between the first symbol -1 and the second symbol 0, etc.). Under these conditions, the TED 136 and / or the TED 200 can determine that the second symbol 148 is located at a sixth example symbol position 518. In this example, the sixth symbol position 518 is a mid-symbol position. In response to identifying the sixth symbol position 518, the TED 136 and / or the TED 200 can generate a timing error based on a negative sum of x midsym and a coefficient of 0.5, and thereby determine the timing error to be -(x midsym + 0.5). In some examples, the timing error signal can be a waveform having an amplitude (e.g., a voltage) representative of the timing error. Advantageously, Figure 1 the PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample a subsequent symbol of the RX input 112 at a correct phase, which can be the 0 symbol before the fifth symbol position 516.

[0067] In an example operation, the sequencer circuit 142 can determine Figure 2 the current slicer decision of the slicer circuit 128 of the symbol is 0, and the previous slicer decision is -1. In response to detecting a -1, 0 symbol transition based on the determination, the TED 136 and / or the TED 200 generates a timing error based on a negative sum of x midsym and a coefficient of 0.5. Alternatively, the coefficient can be any other value. Under these conditions, the TED 136 and / or the TED 200 can determine that the prediction or estimate of the third symbol 150 of the symbol Figure 3 being 0 can indicate Figure 1 the second symbol 148 is between symbols (e.g., is a mid-symbol, is between the first symbol -1 and the second symbol 0, etc.). Under these conditions, the TED 136 and / or the TED 200 can determine that the second symbol 148 is located at a sixth example symbol position 518. In this example, the sixth symbol position 518 is a mid-symbol position. In response to identifying the sixth symbol position 518, the TED 136 and / or the TED 200 can generate a timing error based on a negative sum of x midsym and a coefficient of 0.5, and thereby determine the timing error to be -(x midsym + 0.5). In some examples, the timing error signal can be a waveform having an amplitude (e.g., a voltage) representative of the timing error. Advantageously, Figure 2The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being -1 symbols before the sixth symbol position 518.

[0068] Figure 4 This is a graph 600 containing example waveforms 602, 604, 606, and 608 used to depict example frequency-locking operations associated with different symbols and timing recovery techniques. The x-axis (for graph 600) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. Waveforms 602, 604, 606, and 608 include a first example waveform 602 generated based on the Müller-Muller (MM) TED technique, a second example waveform 604 generated based on the constellation-based TED technique, a third example waveform 606 generated based on the pseudo-ML TED technique, and a fourth example waveform 608 generated based on the intermediate symbol TED technique. For example, the second waveform 604 can respond to... Figure 1 TED 136 and / or Figure 2 TED 200 Executive Figure 5 The first pseudocode 302 and / or the second pseudocode 304 are used to generate it. In some instances, the third waveform 606 can be generated in response to... Figure 1 TED 136 and / or Figure 1 TED 200 Executive Figure 1 The first pseudocode 402 and / or the second pseudocode 404 are used to generate it. In some instances, the fourth waveform 608 can be generated in response to... Figure 7 TED 136 and / or Figure 1 TED 200 Executive Figure 2 It is generated by pseudocode 502.

[0069] Figure 600 depicts the frequency locking operation (e.g., implementing) of different waveforms 602, 604, 606, and 608 relative to a certain number of detected symbols. Figure 3 (PLL 144's timing lockout, timing loop lockout, etc.). For example, different waveforms 602, 604, 606, and 608 can respond to the timing loop frequency accumulator (e.g., Figure 1 Locking is achieved when the value of NCO 140 satisfies an instance threshold (e.g., the value of a lock threshold) 610. In some instances, threshold 610 can be user-defined (e.g., in...). Figure 2 Before the DSP 102 processes the communication channel, it is pre-programmed, configured, etc. In some instances, the threshold 610 can be dynamically adjusted by the sequencer circuit 142. For example, the sequencer circuit 142 can adjust the threshold 610 based on the DSP's historical SNR (e.g., the SNR of DSP 102 in one or more previous clock cycles).

[0070] In some instances, the graph 600 can depict frequency lock operation for relatively short communication channels (e.g., cables of 0.5 meters, 1.0 meter, etc. length), which presents a challenging case because short communication channels have low ISI. Advantageously, in the illustrated instance, the constellation-based TED technique and the pseudo-ML TED technique have improved frequency lock operation in low ISI instances as compared to the MM-TED technique. Advantageously, in some instances, the constellation-based TED technique and the pseudo-ML TED technique have improved frequency lock operation as compared to the MM-TED technique that is independent of and / or otherwise does not account for channel length or ISI present in the channel.

[0071] Figure 4 is a graph 700 that includes example waveforms 702, 704, 706, 708 to depict example frequency lock operation related to different symbol and timing recovery techniques. The x-axis (for graph 700) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. The waveforms 702, 704, 706, 708 include a first example waveform 702 generated based on a Mueller-Muller (MM) TED technique, a second example waveform 704 generated based on a constellation-based TED technique, a third example waveform 706 generated based on a pseudo-ML TED technique, and a fourth example waveform 708 generated based on a pseudo-ML TED technique with a differentiator filter. For example, the second waveform 704 can be generated in response to Figure 1 the TED 136 of FIG. 1 and / or Figure 2 the TED 200 of FIG. 2 executing Figure 4 the first pseudo-code 302 and / or the second pseudo-code 304 of FIG. 3. In some instances, the third waveform 706 can be generated in response to Figure 4 the TED 136 of FIG. 1 and / or Figure 1 the TED 200 of FIG. 2 executing Figure 1 the first pseudo-code 402 and / or the second pseudo-code 404 of FIG. 4. In some instances, the fourth waveform 708 can be generated in response to Figure 8 the TED 136 of FIG. 1 and / or Figure 1 the TED 200 of FIG. 2 executing the first pseudo-code 402 and / or one or more filters to generate a differentiator output, as described above in connection with Figure 1 In some such instances, the one or more filters can implement the second pseudo-code 404 of FIG. 4 to generate the differentiator output. Figure 8

[0072] The graph 700 depicts frequency lock operation of the different waveforms 702, 704, 706, 708 with respect to a number of detected symbols (e.g., achieving Figure 1 ​(PLL 144's timing lockout, timing loop lockout, etc.). For example, different waveforms 702, 704, 706, and 708 can respond to the timing loop frequency accumulator (e.g., Figure 1 Locking is achieved when the value of NCO 140 satisfies the instance threshold (e.g., the value of the locking threshold) 710. In some instances, Figure 700 may depict frequency locking operation for relatively short communication channels (e.g., cables of lengths such as 0.5 meters and 1.0 meters), which presents challenging conditions due to low ISI. Advantageously, in the illustrated examples, in low ISI instances, constellation-based TED technology, pseudo-ML TED technology, and pseudo-ML TED technology with differential filters offer improved frequency locking operation compared to MM-TED technology. Advantageously, in some instances, constellation-based TED technology, pseudo-ML TED technology, and pseudo-ML TED technology with differential filters offer improved frequency locking operation compared to MM-TED technology, which is independent of and / or otherwise disregards channel length or the ISI present in the channel.

[0073] Figure 8 This is a block diagram of an example communication system (e.g., a digital communication system) 800 that includes an example digital signal processor (DSP) 802. In some examples, the DSP 802 and / or (more generally) the communication system 800 may be an Ethernet PHY device. The communication system 800 includes... Figure 1 The circuit includes RX input 112, HPF 104, LPF 106, ADC 108, and phase interpolator circuit 110.

[0074] DSP 802 includes Figure 3 The circuits include DC cancellation circuit 114, CAGC 116, DAGC 118, DEQ 120, FFE 122, adder circuit 124, slicer circuit 128, DFE 130, gain loop circuit 132, MSE circuit 134, loop filter 138, NCO 140, and PLL 144. Figure 4 The text further describes Figure 5 The first symbol 146, the second symbol 148, and the third symbol 150, as well as the control signal 152. The DSP 802 includes additional instances of the TED 804 and the sequencer circuit 806.

[0075] In some instances, the DSP 802, the TED 804, the sequencer circuit 806, and / or (more generally) the communication system 800 performs the M&M timing synchronization technique to adjust the phase of the ADC 108. For example, the operation of the DSP 802 can implement timing lock depending on the ISI of the channel of the communication system 800. In some such instances, the DSP 802 can utilize the M&M timing synchronization technique to balance the post-cursor ISI (P+1) and the pre-cursor ISI (P-1) to implement lock. In some instances, the DSP 802 can utilize the M&M timing synchronization technique to utilize a DFE-corrected symbol (e.g., the second symbol 148) to implement timing lock. By using the M&M timing synchronization technique, the timing loop of the PLL 144 and the output from the DFE 130 must converge together, which can result in longer lock times, or in some instances, can result in instability of the timing loop. In some such instances, the timing loop controlled by the PLL 144 can not converge in systems with low ISI.

[0076] Advantageously, in low ISI systems, the DSP 102 and / or (more generally) Figure 9 the communication system 100 can implement faster timing lock than the DSP 802 of Figure 8 and, thereby, can implement a reduced instance of timing loop instability. Advantageously, the DSP 102 and / or (more generally) Figure 1 the communication system 100 can perform at least one of the first symbol and timing recovery techniques (e.g., the constellation-based TED technique) depicted in Figure 8 the second symbol and timing recovery techniques (e.g., the pseudo-ML TED technique) depicted in Figure 8 or the third symbol and timing recovery techniques (e.g., the mid-symbol TED technique) depicted in Figure 1 .

[0077] Figure 1 is a plot 900 of inter-symbol interference (ISI) associated with example operations of the DSP 802 of Figure 1 The plot 900 has an x-axis of symbols and a y-axis of channel impulse responses. The plot 900 depicts example ISI behavior that occurs when the symbol 11 is sampled at different channel lengths (e.g., a channel length of 0.5 meters and a channel length of 24 meters). For example, the channel impulse responses of symbols other than the symbol 11 depicted in the plot 900 represent the ISI of the communication channel implemented by the communication system 100. Figure 2

[0078] ​As depicted by graph 900, longer channel lengths have improved channel impulse responses compared to shorter channel lengths. As such, DSP 802 can have reduced performance at low ISI levels. For example, there can be reduced ISI in a communication channel having a shorter channel length, and increased ISI in a communication channel having a longer channel length. In graph 900, the ISI is smaller at a channel length of 0.5, and a TED (e.g., TED 804 of Figure 10 using conventional M&M timing synchronization techniques can have difficulty detecting symbols with low ISI (e.g., difficulty detecting symbol 11 in graph 900), as conventional M&M timing synchronization techniques rely on higher ISI levels to achieve detectability. Advantageously, DSP 102 of Figure 8 and / or (more generally) Figure 1 communication system 100 of Figure 7 have improved performance at low ISI levels that is independent of channel length. For example, Figure 8 TED 136 of Figure 11 TED 200 can implement one or more of the symbol and timing recovery techniques described herein that demonstrate improved detectability of symbols at shorter channel lengths, and thereby overcome the deficiencies of conventional M&M timing synchronization techniques at low ISI levels.

[0079] Figure 8 is a graph 1000 of time loop convergence associated with example operations of DSP 802 of Figure 8 The x-axis (for graph 1000) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. Graph 1000 depicts a first time loop convergence for a 0.5 meter channel length (e.g., a cable having a length of 0.5 meters), and a second time loop convergence for a 21 meter channel length (e.g., a cable having a length of 21 meters). As depicted by graph 1000, DSP 802 does not achieve time loop convergence at lower channel lengths. Advantageously, Figure 1 DSP 102 of Figure 1 and / or 8 is depicted in the examples illustrated, and DSP 102 thereby achieves improved performance compared to DSP 802 of Figures 12-15

[0080] Figure 1 is a graph 1100 of time loop convergence associated with example operations of DSP 102 of Figures 12-15 ​The timing error versus gain associated with an example operation of the DSP 802 is plotted in graph 1100. Graph 1100 has an x-axis for the timing error in symbols and a y-axis for the TED S curve. Graph 1100 depicts a first gain relative to the timing error in symbols for a first channel length of 0.5 meters and a second gain relative to the timing error in symbols for a second channel length of 21 meters. As plotted in graph 1100, a longer channel length has an improved gain response compared to a shorter channel length. Thus, the DSP 802 may have reduced performance at shorter channel lengths because the DSP 800 relies on a higher ISI level to achieve symbol detectability. Advantageously, with Figure 1 Compared to the DSP802, Figures 12-15 The DSP 102 and / or (more generally) Figure 12 The communication system 100 has improved performance over shorter channel lengths because its symbol detectability performance is independent of the ISI level, whereas conventional M&M timing synchronization technology is not independent of the ISI level, but instead relies on the ISI level to achieve symbol detectability.

[0081] Figure 12 The demonstration showed that the configuration can be used for implementation. Figure 12 TED 136, sequencer circuit 142, DSP 102, communication system device 100 and / or Figure 13 The flowchart describes the instance hardware logic, instance machine-readable instructions (e.g., hardware-readable instructions), instance hardware-implemented state machine, and / or any combination thereof executed by the TED 200 instance process. The instance machine-readable instructions may be one or more executable programs or portions thereof, which are intended to be executed by a programmable processor (e.g., a programmable microprocessor), programmable controller, GPU, DSP, ASIC, PLD, and / or FPLD. The program may be a software embodiment stored on a non-transitory computer-readable storage medium (e.g., electrically erasable programmable read-only memory (EEPROM), non-volatile memory, volatile memory, etc.), but the entire program and / or portions thereof may alternatively be executed by any other device (e.g., a programmable device) and / or embodied in firmware or dedicated hardware. Furthermore, although referenced... Figure 13 The illustrated flowchart describes an example program, but alternative implementations can be used. Figure 3 TED 136, sequencer circuit 142, DSP 102, communication system device 100 and / or Figure 3TED 200 many other methods and / or techniques. For example, the order of execution of the blocks can be changed, and / or some of these blocks described can be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks can be implemented by one or more hardware circuit(s) (e.g., discrete and / or integrated analog and / or digital circuitry, field programmable logic arrays (FPGAs), application-specific integrated circuits (ASICs), comparators, operational amplifiers (op-amps), logic circuits, etc.) structured to perform the corresponding operations without executing software or firmware.

[0082] The machine-readable instructions described herein can be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein can be stored as data suitable for creating, manufacturing, and / or producing machine-executable instructions (e.g., portions of instructions, code, representations of code, etc.). For example, the machine-readable instructions can be segmented and stored on one or more storage devices. The machine-readable instructions can require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decrypting, decompressing, unpacking, distributing, re-allocating, compiling, etc. in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions can be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, where the portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement, for example, the programs described herein.

[0083] The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: assembly language, C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0084] As described above, Figure 13Example processes of the present disclosure can be implemented using executable instructions stored on non-transitory computer and / or machine readable media such as, for example, flash memory, read-only memory, cache memory, random access memory, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, temporarily, and / or for caching and / or buffering). As used herein, the terms non-transitory computer readable medium, non-transitory machine readable medium, and / or non-transitory hardware readable medium are expressly defined to include any type of computer readable storage device and / or storage disk and to exclude propagating signals and transmission media.

[0085] Figure 13 is a flowchart representation of an example process 1200 that can be executed to perform the symbol and timing recovery techniques described herein. Figure 14 Example process 1200 begins at block 1202, where communication system 100 obtains a receiver (RX) input signal at a wired receiver. For example, HPF 104 can receive RX input 112 from a terminal of a wired receiver, such as a receiver of an Ethernet PHY device.

[0086] At block 1204, communication system 100 samples the RX input signal and converts it to a digital input signal. For example, ADC 108 can sample RX input 112 at a sampling rate of one sample per second, which can be used to recover one symbol per second. In some such examples, ADC 108 samples RX input 112 to convert RX input 112 to a digital input signal.

[0087] At block 1206, communication system 100 adjusts an amplitude of the digital input signal to produce a scaled digital input signal. For example, CAGC 116 can adjust an amplitude of an output from ADC 108.

[0088] At block 1208, communication system 100 adjusts a gain of the scaled digital input signal to produce an output signal. For example, DAGC 118 can adjust a gain of an output from DC removal circuit 114 with an output from gain loop circuit 132.

[0089] At block 1210, the communication system 100 generates a decision feedback equalizer (DFE) output based on the one or more decisions associated with the previous symbol. For example, the slicer circuit 128 can generate the third symbol 150 based on the first symbol 146 and / or the second symbol 148. In some such examples, the DFE 130 can generate a noise error signal, which the summer circuit 124 can use to generate a DFE-corrected symbol.

[0090] At block 1212, the communication system 100 determines whether timing loop lock is achieved. For example, the sequencer circuit 142 can determine that the PLL 144 achieves lock in response to the value of the accumulator of the NCO 140 satisfying a threshold (e.g., a lock threshold, a timing lock, or a timing loop lock threshold, etc.). If, at block 1212, the communication system 100 determines that timing loop lock is not achieved, then control proceeds to block 1218 to generate a timing error based on the un-DFE-corrected symbol. For example, the TED 136 can generate a timing error (e.g., a timing error signal) based on the first symbol 146. In response to generating the timing error at block 1218 based on the un-DFE-corrected symbol, the communication system 100 adjusts the phase of the sampling operation based on the timing error at block 1220. For example, the NCO 140 can generate the control signal 152 based on the timing error from the TED 136. In some such examples, the phase interpolator circuit 110 can adjust the phase of the ADC 108 to control the timing of the sampling of the RX input 112 by the ADC 108.

[0091] If, at block 1212, the communication system 100 determines that timing loop lock is achieved, then at block 1214, the communication system 100 switches to the DFE-corrected symbol. For example, in response to the PLL 144 achieving lock, the sequencer circuit 142 can instruct the multiplexer 126 to switch from providing the un-DFE-corrected symbol (e.g., the first symbol 146) to the TED 136 to providing the DFE-corrected symbol (e.g., the second symbol 148) to the TED 136.

[0092] At block 1216, the communication system 100 generates a timing error based on the DFE-corrected symbol. For example, the TED 136 can generate a timing error (e.g., a timing error signal) based on the second symbol 148 and / or the third symbol 150. In response to generating the timing error at block 1216 based on the DFE-corrected symbol, the communication system 100 adjusts the phase of the sampling operation based on the timing error at block 1220. For example, the NCO 140 can generate the control signal 152 based on the timing error from the TED 136. In some such examples, the phase interpolator circuit 110 can adjust the phase of the ADC 108 to control the timing of the sampling of the RX input 112 by the ADC 108.

[0093] In response to adjusting the phase of the sampling operation based on the timing error at block 1220, the communication system 100 determines whether to continue monitoring the wired receiver at block 1222. For example, the DSP 102 can determine to obtain another RX input at the wired receiver to continue data communication between the devices (e.g., the wired transmitter and the wired receiver). If at block 1222, the communication system 100 determines to continue monitoring the wired receiver, then control returns to block 1202, otherwise Figure 14 The example process 1200 of FIG. 12 ends.

[0094] Figure 4 FIG. 13 is a flowchart representing an example process 1300 that can be executed to perform a constellation-based TED technique. Figure 4 The example process 1300 of FIG. 13 begins at block 1302, where the communication system 100 determines a current (N) slicer decision based on one or more previously detected symbols. For example, the slicer circuit 128 can determine the third symbol 150 to be the current slicer decision based on the one or more previously detected symbols. In some such examples, the slicer circuit 128 can determine the current slicer decision to be +1.

[0095] At block 1304, the communication system 100 determines a previous (N-1) slicer decision. For example, the TED 136 and / or the TED 200 can determine the previous slicer decision to be 0. In some such examples, the previous slicer decision can be stored in a memory of the DSP 102, the TED 136, and / or the TED 200. In some examples, the TED 136 and / or the TED 200 can query the slicer circuit 128 for the previous slicer decision.

[0096] At block 1306, the communication system 100 determines a second-to-last (N-2) slicer decision. For example, the TED 136 and / or the TED 200 can determine the previous slicer decision to be -1. In some such examples, the previous slicer decision can be stored in a memory of the DSP 102, the TED 136, and / or the TED 200. In some examples, the TED 136 and / or the TED 200 can query the slicer circuit 128 for the previous slicer decision.

[0097] At block 1308, the communication system 100 determines whether a negative slope exists based on the slicer decisions. For example, the TED 136 and / or the TED 200 can detect a negative slope based on the N-2, N-1, N symbol transitions of +1, 0, -1. In some such examples, the TED 136 and / or the TED 200 can detect a zero-crossing transition (e.g., a zero-crossing symbol transition) based on the detection of the +1, 0, -1 symbol transitions.

[0098] If, at block 1308, the communication system 100 detects a negative slope based on the slicer decision, then at block 1310, the communication system 100 generates a timing error as a negative value of a previous timing error corresponding to a previously detected symbol. For example, the TED 136 and / or the TED 200 can output a timing error for a current symbol (N) based on a negative value of a timing error for a previously detected symbol (N-1), as described above in connection with FIG. 2. In response to generating the timing error at block 1310, control proceeds to block 1320 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve the sampling window for detecting symbols of the RX input 112. Figure 4

[0099] If, at block 1308, the communication system 100 does not detect a negative slope based on the slicer decision, then control proceeds to block 1312 to detect whether a positive slope exists based on the slicer decision. For example, the TED 136 and / or the TED 200 can detect a positive slope based on N-2, N-1, N symbol transitions of -1, 0, +1. In some such instances, the TED 136 and / or the TED 200 can detect a zero-crossing transition (e.g., a zero-crossing symbol transition) based on detection of -1, 0, +1 symbol transitions.

[0100] If, at block 1312, the communication system 100 detects a positive slope based on the slicer decision, then at block 1314, the communication system 100 generates a timing error as a positive value of a previous timing error corresponding to a previously detected symbol. For example, the TED 136 and / or the TED 200 can output a timing error for a current symbol (N) based on a positive value of a timing error for a previously detected symbol (N-1), as described above in connection with FIG. 2. In response to generating the timing error at block 1314, control proceeds to block 1320 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve the sampling window for detecting symbols of the RX input 112. Figure 4

[0101] ​​If, at block 1312, the communication system 100 fails to detect a positive slope based on the slicer decision, then control proceeds to block 1316 to determine whether the communication system 100 failed to detect either a positive slope or a negative slope based on the slicer decision. For example, the TED 136 and / or the TED 200 can fail to detect either a positive slope or a negative slope based on the slicer decision. In some such instances, the TED 136 and / or the TED 200 can fail to detect a zero-crossing transition. In some such instances, the TED 136 and / or the TED 200 can output a previously determined timing error to improve the lock-in capability of the PLL 144.

[0102] If, at block 1316, the communication system 100 is able to detect either a positive slope or a negative slope based on the slicer decision, then Figure 14 the process 1300 ends. If, at block 1316, the communication system 100 is unable to detect either a positive slope or a negative slope based on the slicer decision, then, at block 1318, the communication system 100 generates a timing error based on a previous timing error. For example, the TED 136 and / or the TED 200 can generate the timing error as a previously determined timing error (e.g., a timing error of a previously detected symbol). In some such instances, in response to the timing error from the TED 136 and / or the TED 200, the NCO 140 can output a stored value of an accumulator of the NCO 140. In response to generating the timing error at block 1318, control proceeds to block 1320 to adjust a phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve a sampling window for detecting a symbol of the RX input 112. In response to adjusting the phase based on the timing error, Figure 14 the process 1300 ends.

[0103] Figure 15 is a flowchart representative of an example process 1400 that can be executed to perform a pseudo-ML TED technique. Figure 15 The example process 1400 begins at block 1402, where the communication system 100 determines a current (N) slicer decision based on one or more previously detected symbols. For example, the slicer circuit 128 can determine the third symbol 150 as the current slicer decision based on one or more previously detected symbols. In some such instances, the slicer circuit 128 can determine the current slicer decision as -1.

[0104] At block 1404, the communication system 100 determines a previous (N-1) slicer decision and a second-to-last (N-2) slicer decision. For example, the TED 136 and / or the TED 200 can determine the previous slicer decision to be +1 and the second-to-last slicer decision to be -1. In some such examples, the previous slicer decision and / or the second-to-last slicer decision can be stored in a memory of the DSP 102, the TED 136, and / or the TED 200. In some examples, the TED 136 and / or the TED 200 can query the slicer circuit 128 for the previous slicer decision and / or the second-to-last slicer decision.

[0105] At block 1406, the communication system 100 detects whether a peak symbol point transition exists based on the slicer decisions. For example, the TED 136 and / or the TED 200 can detect a peak symbol point transition based on the N-2, N-1, N symbol transitions of -1, +1, -1.

[0106] If, at block 1406, the communication system 100 detects a peak symbol point transition based on the slicer decisions, then at block 1408, the communication system 100 generates a timing error based on the differential samples associated with the peak symbol point transition. For example, the TED 136 and / or the TED 200 can be a differentiator to generate a timing error for the current symbol (N), as described above in connection with the first pseudocode 402. Figure 5 In some such examples, the differentiator can execute the second pseudocode 404. Figure 5 In response to generating the timing error at block 1408, control proceeds to block 1418 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve the sampling window for detecting symbols of the RX input 112.

[0107] If, at block 1406, the communication system 100 does not detect a peak symbol point transition based on the slicer decisions, then control proceeds to block 1410 to detect whether a valley symbol point transition exists based on the slicer decisions. For example, the TED 136 and / or the TED 200 can detect a valley symbol point transition based on the N-2, N-1, N symbol transitions of +1, -1, +1.

[0108] If, at block 1410, the communication system 100 detects a valley symbol point transition based on the slicer decisions, then at block 1412, the communication system 100 generates a timing error based on the differential samples associated with the valley symbol point transition. For example, the TED 136 and / or the TED 200 can be a differentiator to generate a timing error for the current symbol (N), as described above in connection with the first pseudocode 402. Figure 5 In some such examples, the differentiator can execute the second pseudocode 404. Figure 5second pseudo code 404. In response to generating the timing error at block 1412, control proceeds to block 1418 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve the sampling window for detecting the sign of the RX input 112.

[0109] If at block 1410, the communication system 100 fails to detect a valley sign point transition based on the slicer decision, then control proceeds to block 1414 to determine whether the communication system 100 failed to detect a peak or valley sign point transition based on the slicer decision. For example, the TED 136 and / or the TED 200 can fail to detect both a peak sign point transition and a valley sign point transition based on the slicer decision. In some such instances, the TED 136 and / or the TED 200 can output a previously determined timing error to improve the lock-in capability of the PLL 144.

[0110] If at block 1414, the communication system 100 is able to detect a peak or valley sign point transition based on the slicer decision, then Figure 15 The process 1400 of FIG. 14 ends. If at block 1414, the communication system 100 is unable to detect a peak or valley sign point transition based on the slicer decision, then at block 1416, the communication system 100 generates a timing error based on a previous timing error. For example, the TED 136 and / or the TED 200 can generate the timing error as a previously determined timing error (e.g., a timing error of a previously detected sign). In some such instances, in response to the timing error from the TED 136 and / or the TED 200, the NCO 140 can output a stored value of an accumulator of the NCO 140. In response to generating the timing error at block 1416, control proceeds to block 1418 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 to improve the sampling window for detecting the sign of the RX input 112. In response to adjusting the phase based on the timing error, ​ The process 1400 of FIG. 14 ends.

[0111] ​ is a flowchart representing an example process 1500 that can be executed to perform an intermediate sign TED technique. ​ The example process 1500 of FIG. 15 begins at block 1502, where the communication system 100 determines a current (N) slicer decision based on one or more previously detected signs. For example, the slicer circuit 128 can determine that the third sign 150 is the current slicer decision based on one or more previously detected signs. In some such instances, the slicer circuit 128 can determine the current slicer decision to be -1.

[0112] At block 1504, the communication system 100 determines a previous (N-1) slicer decision. For example, the TED 136 and / or the TED 200 can determine the previous slicer decision to be 0. In some such examples, the previous slicer decision can be stored in a memory of the DSP 102, the TED 136, and / or the TED 200. In some examples, the TED 136 and / or the TED 200 can query the slicer circuit 128 for the previous slicer decision.

[0113] At block 1506, the communication system 100 detects whether there is an intermediate symbol based on ((N-1) = -1) and (N = +1) based on the slicer decision. For example, the TED 136 and / or the TED 200 can detect the first symbol position 508 based on -1, +1 N-1, N symbol transitions. If, at block 1506, the communication system 100 detects an intermediate symbol based on ((N-1) = -1) and (N = +1), then, at block 1508, the communication system 100 generates a timing error based on a difference between the intermediate value and the coefficient. For example, the TED 136 and / or the TED 200 can generate the timing error based on the pseudocode 502 of ​ In response to generating the timing error based on the difference between the intermediate value and the coefficient at block 1508, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the symbols of the RX input 112 are detected.

[0114] If, at block 1506, the communication system 100 does not detect an intermediate symbol based on ((N-1) = -1) and (N = +1), then the communication system 100 detects whether there is an intermediate symbol based on ((N-1) = +1) and (N = -1) at block 1510. For example, the TED 136 and / or the TED 200 can detect the intermediate symbol based on +1, -1 N-1, N symbol transitions. If, at block 1510, the communication system 100 detects an intermediate symbol based on ((N-1) = +1) and (N = -1), then, at block 1512, the communication system 100 generates a timing error based on a difference between the intermediate value and the coefficient. For example, the TED 136 and / or the TED 200 can generate the timing error based on the pseudocode 502 of ​the pseudo code 502 produces a timing error. In some such instances, the coefficient can be 0. Responsive to producing the timing error based on the difference between the intermediate symbol and the coefficient at block 1512, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the symbols of the RX input 112 are detected.

[0115] If at block 1510, the communication system 100 does not detect an intermediate symbol based on ((N-1) = +1) and (N = -1), then the communication system 100 detects whether there is an intermediate symbol based on ((N-1) = 0) and (N = +1) at block 1514. For example, the TED 136 and / or the TED 200 can detect an intermediate (intermediate or mid) symbol based on 0, +1 N-1, N symbol transitions. If at block 1514, the communication system 100 detects an intermediate symbol based on ((N-1) = 0) and (N = +1), then at block 1516, the communication system 100 produces a timing error based on a difference between the intermediate symbol and the coefficient. For example, the TED 136 and / or the TED 200 can produce a timing error based on ​ the pseudo code 502 produces a timing error. Responsive to producing the timing error based on the difference between the intermediate symbol and the coefficient at block 1516, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase of the ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the symbols of the RX input 112 are detected.

[0116] If at block 1514, the communication system 100 does not detect an intermediate symbol based on ((N-1) = 0) and (N = +1), then the communication system 100 detects whether there is an intermediate symbol based on ((N-1) = +1) and (N = 0) at block 1518. For example, the TED 136 and / or the TED 200 can detect an intermediate symbol based on +1, 0 N-1, N symbol transitions. If at block 1518, the communication system 100 detects an intermediate symbol based on ((N-1) = +1) and (N = 0), then at block 1520, the communication system 100 produces a timing error based on a difference between the intermediate symbol and the coefficient. For example, the TED 136 and / or the TED 200 can produce a timing error based on ​The pseudo code 502 produces a timing error. In response to producing the timing error based on the difference between the intermediate symbol and the coefficient at block 1520, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 can adjust the phase (e.g., increase or decrease the phase) of the ADC 108 to adjust and / or otherwise shift the sampling window in which the symbols of the RX input 112 are detected. In response to adjusting the phase based on the timing error at block 1522, ​ The process 1500 ends.

[0117] In this description, the term "and / or," when used in, for example, the form "A, B, and / or C" means any combination of A, B, C, or subsets thereof, e.g., (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A, B, and C. Likewise, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") means an implementation that includes at least one of A, at least one of B, or both at least one of A and at least one of B.

[0118] The example systems, methods, apparatuses, and articles of manufacture described herein include symbol and timing recovery techniques to achieve improved timing loop lock performance independent of channel length or ISI present in the channel. The example systems, methods, apparatuses, and articles of manufacture described herein include constellation-based TED techniques to determine timing error based on zero-crossing transitions. The example systems, methods, apparatuses, and articles of manufacture described herein include pseudo-ML TED techniques to determine timing error based on detection of peak or valley symbol transitions. The example systems, methods, apparatuses, and articles of manufacture described herein include intermediate symbol TED techniques to determine timing error based on interpolation of samples comparing a symbol midpoint to an expected midpoint. The example systems, methods, apparatuses, and articles of manufacture described herein include a combination of constellation-based TED techniques and pseudo-ML TED techniques to improve TED gain since both techniques use complementary symbol transitions. The example systems, methods, apparatuses, and articles of manufacture described herein include a differentiator that performs the pseudo-ML TED techniques with one or more filters. The example systems, methods, apparatuses, and articles of manufacture described herein include an interpolation operation that performs the pseudo-ML TED techniques with one or more filters. The example systems, methods, apparatuses, and articles of manufacture described herein include symbol and timing recovery techniques that cause a TED to pass a previous timing error value when a specified or expected symbol transition is not detected. Advantageously, the symbol and timing recovery techniques described herein can be performed by any wired receiver, transmitter, transceiver, etc. (e.g., an Ethernet PHY device) to achieve reduced hardware cost and power consumption.

[0119] Example methods, apparatus, systems, and articles of manufacture, and related methods, for symbol and timing recovery are described herein. Further examples and combinations thereof include the following:

[0120] Example 1 includes an apparatus comprising: a feed forward equalizer (FFE) having an FFE output; a summer circuit having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output; a multiplexer (MUX) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output; a decision feedback equalizer (DFE) having a DFE output coupled to the second summer input; and a timing error detector (TED) having a first TED input coupled to the MUX output.

[0121] Example 2 includes the apparatus of Example 1, wherein the summer circuit has a second summer output, the DFE has a DFE input, the TED has a second TED input, and the apparatus further includes a slicer circuit having a slicer input, a first slicer output, and a second slicer output, the slicer input coupled to the second summer output, the first slicer output coupled to the DFE input, the second slicer output coupled to the second TED input.

[0122] Example 3 includes the apparatus of Example 1, wherein the MUX is a first MUX, the MUX output is a first MUX output, the DFE has a first DFE output and a second DFE output, and the TED includes: a second MUX having a third MUX input, a fourth MUX input, a fifth MUX input, a second MUX output, the third MUX input coupled to the first DFE output, the fourth MUX input coupled to the second DFE output; and a latch having a latch input and a latch output, the latch input coupled to the second MUX output, the latch output coupled to the fifth MUX input.

[0123] Example 4 includes the apparatus of Example 3, wherein the first MUX has a first MUX control input, the second MUX has a second MUX control input, and the apparatus further includes a sequencer circuit having a first sequencer output coupled to the first MUX control input and a second sequencer output coupled to the second MUX control input.

[0124] Example 5 includes the apparatus of Example 3, wherein the second MUX has a third MUX output, and the apparatus further includes a phase-locked loop (PLL) having a PLL input coupled to the third MUX output.

[0125] Example 6 includes the apparatus of Example 1, wherein the TED has a TED output, and the apparatus further includes a loop filter having a loop filter input and a loop filter output, the loop filter input coupled to the TED output; a numerically controlled oscillator (NCO) having an NCO input and an NCO output, the NCO input coupled to the loop filter output; and a phase detector having a phase detector input coupled to the NCO output.

[0126] Example 7 includes the apparatus of Example 6, wherein the phase detector has a phase detector output, and the apparatus further includes an analog-to-digital converter (ADC) having a first ADC input and a second ADC input, the first ADC input coupled to the phase detector output; a low pass filter having a first filter input and a first filter output, the first filter output coupled to the second ADC input; a high pass filter having a second filter input and a second filter output, the second filter output coupled to the first filter input; and a terminal coupled to the second filter input.

[0127] Example 8 includes the apparatus of Example 1, wherein the FFE has a FFE input, the TED has a TED output, and the apparatus further includes a phase-locked loop (PLL) having a PLL input and a PLL output, the PLL input coupled to the TED output; an analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input coupled to the PLL output; a direct current (DC) removal circuit having a first input and a first output, the first input coupled to the ADC output; a digital automatic gain control (AGC) circuit having a second input and a second output, the second input coupled to the first output; and a de-emphasis circuit having a third input and a third output, the third input coupled to the second output, the third output coupled to the FFE input.

[0128] Example 9 includes a receiver operable to receive a communication signal including a plurality of symbols, the receiver comprising: a memory including instructions stored in the memory; a processor coupled to the memory and operable to execute the instructions to at least: detect one or more first symbols of the plurality of symbols in the communication signal based on a first phase of a sampling clock; determine a second symbol of the plurality of symbols in the communication signal based on the one or more first symbols; generate a voltage corresponding to a timing phase offset, the voltage based on the second symbol; generate a control signal based on the second symbol in response to the voltage satisfying a threshold; and adjust the first phase to a second phase based on the control signal.

[0129] Example 10 includes the receiver of Example 9, wherein the processor is to identify a timing loop lock based on the voltage satisfying the threshold.

[0130] Example 11 includes the receiver of Example 9, wherein the one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is to: determine that the third symbol corresponds to a positive one value; determine that the fourth symbol corresponds to a zero value; determine that the fifth symbol corresponds to a negative one value; and detect a zero-crossing transition based on the determinations.

[0131] Example 12 includes the receiver of Example 11, wherein the third symbol is a current decision of a slicer circuit, the timing phase offset is a second timing phase offset, and the processor is to, in response to the detection of the zero-crossing transition: determine that the second symbol is a product of a sign of the current decision and a first timing phase offset corresponding to the fourth symbol.

[0132] Example 13 includes the receiver of Example 9, wherein the one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is to: determine that the third symbol corresponds to a negative one value; determine that the fourth symbol corresponds to a zero value; determine that the fifth symbol corresponds to a positive one value; and detect a zero-crossing transition based on the determinations.

[0133] Example 14 includes the receiver of Example 13, wherein the third symbol is a current decision of a slicer circuit, the timing phase offset is a second timing phase offset, and the processor is to, in response to the detection of the zero-crossing transition: determine that the second symbol is a product of a sign of the current decision and a first timing phase offset corresponding to the fourth symbol.

[0134] Example 15 includes the receiver of Example 9, wherein the processor is to: determine values of respective symbols of the one or more first symbols; and in response to determining that a zero-crossing transition is not detected based on the values, determine that the second symbol is a zero value.

[0135] Example 16 includes the receiver of Example 9, wherein the timing phase offset is a second timing phase offset determined at a second time, and the processor is to: determine a value of a respective symbol of the one or more first symbols; and in response to determining that no zero-crossing transition is detected based on the value, determine the second symbol as a first timing phase offset determined at a first time prior to the second time.

[0136] Example 17 includes the receiver of Example 9, wherein the one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is to: determine that the third symbol corresponds to a negative one value; determine that the fourth symbol corresponds to a positive one value; determine that the fifth symbol corresponds to a negative one value; and detect a peak symbol point transition based on the determinations.

[0137] Example 18 includes the receiver of Example 17, wherein the third symbol is a current decision of a slicer circuit, the timing phase offset is a second timing phase offset, and the processor is to, in response to the detection of the peak symbol point transition: determine a difference between a first differentiator output and a second differentiator output; and determine the second symbol as a product of the difference and a first timing phase offset corresponding to the fourth symbol.

[0138] Example 19 includes the receiver of Example 9, wherein the one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is to: determine that the third symbol corresponds to a positive one value; determine that the fourth symbol corresponds to a negative one value; determine that the fifth symbol corresponds to a positive one value; and detect a peak symbol point transition based on the determinations.

[0139] Example 20 includes the receiver of Example 19, wherein the third symbol is a current decision of a slicer circuit, the timing phase offset is a second timing phase offset, and the processor is to, in response to the detection of the peak symbol point transition: determine a difference between a first differentiator output and a second differentiator output; and determine the second symbol as a product of a negative one value, the difference, and a first timing phase offset corresponding to the fourth symbol.

[0140] Example 21 includes the receiver of Example 9, wherein the one or more first symbols include a third symbol and a fourth symbol, and the processor is to: determine that the third symbol corresponds to a first value; determine that the fourth symbol corresponds to a second value; detect a fifth symbol having a third value between the first value and the second value; and determine the second symbol based on a difference between the third value and a fourth value, the fourth value based on half of a sum of the first value and the second value.

[0141] Example 22 includes at least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a processor to at least: determine one or more first signs of a first phase of a sampling clock; determine a second sign based on the one or more first signs; generate a voltage corresponding to a timing phase offset, the voltage based on the second sign; generate a control signal based on the second sign in response to the voltage satisfying a threshold; and adjust the first phase to a second phase based on the control signal.

[0142] Example 23 includes the at least one non-transitory computer-readable storage medium of Example 22, wherein the one or more first signs include a third sign and a fourth sign, the timing phase offset is a second timing phase offset, and the instructions, when executed, cause the processor to: detect a zero-crossing transition of the digital signal based on the one or more first signs; and determine the second sign as a product of a sign of the third sign and a first timing offset corresponding to the fourth sign in response to detection of the zero-crossing transition.

[0143] Example 24 includes the at least one non-transitory computer-readable storage medium of Example 22, wherein the one or more first signs include a third sign, a fourth sign, and a fifth sign, the timing phase offset is a second timing phase offset, and the instructions, when executed, cause the processor to: detect a peak or valley sign point transition of the digital signal based on the one or more first signs; determine a difference between a first differentiator output associated with the third sign and a second differentiator output associated with the fifth sign in response to detection of the peak sign point transition or the valley sign point transition; and determine the second sign as a product of the difference and a first timing phase offset corresponding to the fourth sign.

[0144] Example 25 includes the at least one non-transitory computer-readable storage medium of Example 22, wherein the one or more first signs include a third sign, a fourth sign, and a fifth sign, the timing phase offset is a second timing phase offset, and the instructions, when executed, cause the processor to: determine that the fourth sign is between the third sign and the fifth sign; and determine the second sign based on a difference between a first value corresponding to the fourth sign and a second value based on a half of a sum of a third value corresponding to the third sign and a fourth value corresponding to the fifth sign.

[0145] The term "coupled" is used throughout the specification. The term can encompass a connection, communication, or signal path that enables a functional relationship between the connected components. For example, if device A provides a signal to control device B to perform an action, then in a first instance device A is coupled to device B, or in a second instance device A is coupled to device B through intervening component C that does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

[0146] A device "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) at a manufacturing or construction facility to perform that function, and / or can be configured (or reconfigured) by a user after manufacturing or construction to perform the function and / or other additional or alternative functions. The configuration can be through firmware and / or software programming of the device, through a construction and / or layout of hardware components and interconnections of the device, or a combination thereof.

[0147] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" can be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnect or a termination point of an interconnect between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0148] Circuits or devices described herein that include certain components can alternatively be adapted to be coupled to those components to form the described circuit or device. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) can alternatively include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be adapted to be coupled to at least some of the passive elements and / or sources at the time of manufacture or after the time of manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0149] Circuits described herein can be reconfigurable to include replaced components to provide functionality at least similar to some of the functionality available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors, respectively, coupled in series between the same two nodes.

[0150] "approximately" or "essentially" before a value means + / - 10% of the stated value, unless otherwise indicated.

[0151] Modifications can be made to the described embodiments, and other embodiments are possible.

Claims

1. An apparatus comprising: a feed forward equalizer (FFE) having an FFE output; a summer circuit having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output; a multiplexer (MUX) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output; a decision feedback equalizer (DFE) having a DFE output coupled to the second summer input; and a timing error detector (TED) having a first TED input coupled to the MUX output.

2. The apparatus of claim 1, wherein the summer circuit has a second summer output, the DFE has a DFE input, the TED has a second TED input, and the apparatus further includes a slicer circuit having a slicer input, a first slicer output, and a second slicer output, the slicer input coupled to the second summer output, the first slicer output coupled to the DFE input, the second slicer output coupled to the second TED input.

3. The apparatus of claim 1, wherein the MUX is a first MUX, the MUX output is a first MUX output, the DFE has a first DFE output and a second DFE output, and the TED includes: a second MUX having a third MUX input, a fourth MUX input, a fifth MUX input, a second MUX output, the third MUX input coupled to the first DFE output, the fourth MUX input coupled to the second DFE output; and a latch having a latch input and a latch output, the latch input coupled to the second MUX output, the latch output coupled to the fifth MUX input.

4. The apparatus of claim 3, wherein the first MUX has a first MUX control input, the second MUX has a second MUX control input, and the apparatus further includes a sequencer circuit having a first sequencer output coupled to the first MUX control input and a second sequencer output coupled to the second MUX control input.

5. The apparatus of claim 3, wherein the second MUX has a third MUX output, and the apparatus further includes a phase locked loop (PLL) having a PLL input coupled to the third MUX output.

6. The apparatus of claim 1, wherein the TED has a TED output, and the apparatus further includes: a loop filter having a loop filter input and a loop filter output, the loop filter input coupled to the TED output; a numerically controlled oscillator (NCO) having an NCO input and an NCO output, the NCO input coupled to the loop filter output; and a phase detector having a phase detector input coupled to the NCO output. ​ ​ 7. The apparatus of claim 6, wherein the phase detector has a phase detector output, and the apparatus further comprises: an analog-to-digital converter (ADC) having a first ADC input and a second ADC input, the first ADC input coupled to the phase detector output; a low pass filter having a first filter input and a first filter output, the first filter output coupled to the second ADC input; a high pass filter having a second filter input and a second filter output, the second filter output coupled to the first filter input; and a terminal coupled to the second filter input.

8. The apparatus of claim 1, wherein the FFE has an FFE input, the TED has a TED output, and the apparatus further comprises: a phase-locked loop (PLL) having a PLL input and a PLL output, the PLL input coupled to the TED output; an analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input coupled to the PLL output; a direct current (DC) removal circuit having a first input and a first output, the first input coupled to the ADC output; a digital automatic gain control (AGC) circuit having a second input and a second output, the second input coupled to the first output; and a de-emphasis circuit having a third input and a third output, the third input coupled to the second output, the third output coupled to the FFE input.

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