A shift register, its control timing and display device

Abstract

The present invention provides a shift register, its control timing, and display device. In the first phase of LPWG, the thin-film transistor controlled by the frame reset control terminal is in the on state, and the second voltage of the first power supply terminal is provided to the scan signal output terminal. Therefore, the second voltage output by the scan signal output terminal can control the TFT of the sub-pixel in the display area to turn off, which can reduce the leakage current of the TFT in the sub-pixel. During the touch detection in the second phase, no additional coupling capacitance is detected by the Touch IC to cause noise. At the same time, the present invention eliminates the All Gate On action in the no-sensing area, that is, the period when VSP is pulled high and maintained in Figure 1, which can avoid the coupling of the continuous change of the Gate level to the pixel voltage. In this way, in LPWG mode, the pixel voltage is not coupled with any signal, which solves the problem of screen flickering when the screen is turned on again.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a control timing thereof, and a display device. Background Art

[0002] With the rapid development of display technology, display devices are increasingly moving towards high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) gate drive circuits on the array substrate of a display device to provide scanning drive for the display device. Summary of the Invention

[0003] Embodiments of the present invention provide a shift register, a control timing thereof, and a display device to solve the problems of coupling noise occurring during a touch phase of a gesture wake-up mode and charge residue occurring during a non-touch phase.

[0004] A shift register provided by an embodiment of the present invention includes a frame reset module, wherein the frame reset module is electrically connected to a frame reset control terminal, a first power supply terminal, a first node, and a scan signal output terminal respectively; wherein,

[0005] The frame reset module is configured to, in a first stage of a gesture wake-up mode, provide a second voltage from the first power supply terminal to the scan signal output terminal in response to control of the first voltage from the frame reset control terminal; wherein the first voltage is greater than or equal to a threshold voltage of a thin film transistor of the frame reset module, and a polarity of the second voltage is opposite to a polarity of the first voltage;

[0006] The frame reset module is configured to provide a first touch modulation voltage to the frame reset control end and a second touch modulation voltage to the first power supply end in the second stage of the gesture wake-up mode; wherein the polarity of the second touch modulation voltage is opposite to the polarity of the first touch modulation voltage.

[0007] In some embodiments, in the above-mentioned shift register provided by an embodiment of the present invention, the first voltage is a positive voltage output by an external power supply, and the second voltage is a negative voltage output by the external power supply.

[0008] In some embodiments, in the above-mentioned shift register provided by an embodiment of the present invention, the first voltage is 5V to 6.5V, and the second voltage is -6.5V to -5V.

[0009] In some embodiments, in the above-mentioned shift register provided in an embodiment of the present invention, the frequency of the first touch modulation voltage is the same as the frequency of the second touch modulation voltage, and the number of square waves of the first touch modulation voltage is the same as the number of square waves of the second touch modulation voltage.

[0010] In some embodiments, in the above-mentioned shift register provided in an embodiment of the present invention, the frequency of the first touch modulation voltage and the frequency of the second touch modulation voltage are both 70kHz~110kHz, and the number of square waves of the first touch modulation voltage and the number of square waves of the second touch modulation voltage are both 4~12.

[0011] In some embodiments, in the shift register provided by the embodiments of the present invention, the amplitude of the first touch modulation voltage is 0 to 5V, and the amplitude of the second touch modulation voltage is -5V to 0.

[0012] In some embodiments, in the above-mentioned shift register provided by an embodiment of the present invention, the sum of the duration of the first stage and the duration of the second stage is 16.67ms-50ms, and the duration of the second stage is 600ns-2ms.

[0013] In some embodiments, the shift register provided in the embodiments of the present invention further includes:

[0014] an input module, the input module being electrically connected to the input control terminal, the second power terminal, and the first node respectively; the input module being configured to provide the second voltage to the second power terminal in the first phase, and being configured to provide the second touch modulation voltage to the second power terminal in the second phase;

[0015] a row reset module, the row reset module being electrically connected to the row reset control terminal, the third power supply terminal, and the first node, respectively; the row reset module being configured to provide the second voltage to the third power supply terminal in the first phase, and being configured to provide the second touch modulation voltage to the third power supply terminal in the second phase;

[0016] a node inverting module, the node inverting module being electrically connected to the first power supply terminal, the fourth power supply terminal, the first node, and the second node respectively;

[0017] An output module, wherein the output module is electrically connected to the clock signal terminal, the first node and the scan signal output terminal respectively; the output module is configured to input the second voltage to the clock signal terminal in the first stage, and is configured to input the second touch modulation voltage to the clock signal terminal in the second stage.

[0018] In some embodiments, in the above-mentioned shift register provided by an embodiment of the present invention, the input module is further configured to input the second voltage to the input control terminal in the first phase, and is configured to input the second touch modulation voltage to the input control terminal in the second phase;

[0019] The node inversion module is further configured to provide the second voltage to the fourth power terminal in the first phase, and is configured to provide the second touch modulation voltage to the fourth power terminal in the second phase.

[0020] In some embodiments, in the above-mentioned shift register provided in an embodiment of the present invention, the node inversion module is also configured to provide the first voltage to the fourth power supply terminal in the first stage, and is configured to provide the first touch modulation voltage to the fourth power supply terminal in the second stage.

[0021] In some embodiments, in the above-mentioned shift register provided in an embodiment of the present invention, the input module is further configured to provide the first voltage to the input control end in the first stage, and is configured to input the first touch modulation voltage to the input control end in the second stage.

[0022] In some embodiments, in the above-mentioned shift register provided by the embodiments of the present invention, all control terminals, clock signal terminals and power supply terminals of the shift register are configured to input a ground voltage in the black screen stage.

[0023] In some embodiments, in the above-mentioned shift register provided by an embodiment of the present invention, the frame reset module includes a first switch transistor and a second switch transistor; the gate of the first switch transistor is electrically connected to the frame reset control terminal, the first electrode of the first switch transistor is electrically connected to the first power supply terminal, and the second electrode of the first switch transistor is electrically connected to the first node; the gate of the second switch transistor is electrically connected to the frame reset control terminal, the first electrode of the second switch transistor is electrically connected to the first power supply terminal, and the second electrode of the second switch transistor is electrically connected to the scan signal output terminal;

[0024] The input module includes a third switch transistor, wherein a gate of the third switch transistor is electrically connected to the input control terminal, a first electrode of the third switch transistor is electrically connected to the second power supply terminal, and a second electrode of the third switch transistor is electrically connected to the first node;

[0025] The row reset module includes a fourth switch transistor, a gate of the fourth switch transistor is electrically connected to the row reset control terminal, a first electrode of the fourth switch transistor is electrically connected to the third power supply terminal, and a second electrode of the fourth switch transistor is electrically connected to the first node;

[0026] The node inversion module includes a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, and a tenth switching transistor; the gate and first electrode of the fifth switching transistor are both electrically connected to the fourth power supply terminal, the second electrode of the fifth switching transistor is electrically connected to the gate of the sixth switching transistor and the second electrode of the seventh switching transistor; the first electrode of the sixth switching transistor is electrically connected to the fourth power supply terminal, and the second electrode of the sixth switching transistor is electrically connected to the second node; the gate of the seventh switching transistor is electrically connected to the first node, and the first electrode of the seventh switching transistor is electrically connected to the first power supply terminal; the gate of the eighth switching transistor is electrically connected to the first node, the first electrode of the eighth switching transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth switching transistor is electrically connected to the second node; the gate of the ninth switching transistor is electrically connected to the second node, the first electrode of the ninth switching transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth switching transistor is electrically connected to the first node; the gate of the tenth switching transistor is electrically connected to the second node, the first electrode of the tenth switching transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth switching transistor is electrically connected to the scan signal output terminal;

[0027] The output module includes an eleventh switching transistor and a capacitor, the gate of the eleventh switching transistor is electrically connected to the first node, the first electrode of the eleventh switching transistor is electrically connected to the clock signal end, and the second electrode of the eleventh switching transistor is electrically connected to the scan signal output end.

[0028] Accordingly, an embodiment of the present invention further provides a control timing sequence of a shift register, wherein the control timing sequence is used to drive the above-mentioned shift register provided by the embodiment of the present invention, and the control timing sequence includes:

[0029] In the first stage of the gesture wake-up mode, the frame reset control terminal provides a first voltage, and the first power supply terminal provides a second voltage; wherein the first voltage is greater than or equal to a threshold voltage of the thin film transistor of the frame reset module, and the polarity of the second voltage is opposite to that of the first voltage;

[0030] In the second stage of the gesture wake-up mode, the frame reset control terminal provides a first touch modulation voltage, and the first power supply terminal provides a second touch modulation voltage; wherein the polarity of the second touch modulation voltage is opposite to that of the first touch modulation voltage.

[0031] Correspondingly, an embodiment of the present invention also provides a display device, including a display panel, the display panel including a display area and a non-display area arranged around the display area, the non-display area including a gate driving circuit, and the gate driving circuit including a plurality of cascaded shift registers provided by an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A timing diagram of a GOA circuit signal in LPWG mode provided in the related art;

[0033] Figure 2 This is a schematic diagram of the corresponding shutdown effect when the pixel TFT has no leakage;

[0034] Figure 3 This is a schematic diagram of the corresponding shutdown effect when the pixel TFT has leakage;

[0035] Figure 4 For Figure 1 Schematic diagram of pixel voltage coupling corresponding to the VSP period in the no sensing area;

[0036] Figure 5 A schematic structural diagram of a shift register provided by an embodiment of the present invention;

[0037] Figure 6 for Figure 5 A timing diagram of the shift register shown in LPWG mode;

[0038] Figure 7 for Figure 5 Another timing diagram of the shift register shown in LPWG mode;

[0039] Figure 8 for Figure 5 Another timing diagram of the shift register shown in LPWG mode;

[0040] Figure 9 for Figure 5 The actual timing diagram of the shift register in LPWG mode is shown;

[0041] Figure 10 A schematic diagram of a shift register (GOA) driving a row of sub-pixels (pixels) in a display area according to an embodiment of the present invention;

[0042] Figure 11 for Figure 1 The timing shown and Figure 6 The timing shown is a schematic diagram comparing the touch signal measured in the sensing area;

[0043] Figure 12 A schematic diagram of a control timing of a shift register provided by an embodiment of the present invention;

[0044] Figure 13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0048] In actual use, the GOA circuit sometimes needs to be used in conjunction with other functions, such as touch functions, so it is sometimes necessary to pause the GOA circuit signal to cooperate with other functions. Typically, after the GOA circuit achieves signal pausing, the display device needs to be awakened by a low-power wake-up gesture (LPWG). LPWG is a special feature of current smartphones. When the smartphone is in standby mode (sleep in), it supports screen sliding operations. Users can use preset gestures to directly wake up certain functions or corresponding software of the smartphone. In other words, when the smartphone is in LPWG mode, it is a low-power mode that can retain the touch function. In this mode, the display is turned off and the charge pump function is turned off. The touch function is driven only by the positive voltage (VSP) / negative voltage (VSN) of the external power supply.

[0049] The design scheme of the timing of the GOA circuit signal in the LPWG mode in the related art is as follows: Figure 1 As shown, after the display phase ends, the display enters the black screen state (SLPIN). All GOA circuit signals are pulled back to the GND level. GOA circuit signals include the frame reset signal (STV0) and other signals such as the clock signal (Others). The display then enters LPWG mode. An LPWG frame is divided into two phases: the touch sensing area and the non-touch sensing area. In the touch sensing area, all GOA circuit signals are pulled to VSN to shut down the display. At this point, the GOA circuit's scan signal output (G_OUT(n)) is similar to a floating state, and the GOA circuit's thin-film transistors are susceptible to environmental factors and leakage. In the nosensing area, the current GOA circuit does not have a total reset function, so the GOA circuit signal will be pulled high for a period of time in this area, turning on the thin-film transistor (TFT) of the GOA circuit. This can discharge the residual charge in the sub-pixels (defined by the gate line Gate and data line Data) in the display area, thereby avoiding abnormal display problems such as screen flicker or flicker drift caused by liquid crystal polarization.

[0050] like Figure 1 As shown in the figure, in LPWG mode, the signal inputs of the GOA circuit are first low (VSN), so G_OUT(n) has no output, thus turning off the sub-pixels in the display area. Under normal circumstances, since the TFT characteristics in the sub-pixels are stable, G_OUT(n) can turn off the TFTs in the sub-pixels. However, after the reliability test, the TFT characteristics will change, especially the off-state current (Ioff ) will show a negative drift as the experimental time goes by. Therefore, under the same output voltage conditions, the turn-off capability of the sub-pixel TFT decreases, and a pA-level leakage current will flow between the source and drain of the TFT, which will pull the voltage level of the pixel electrode in the sub-pixel. Figure 2 As shown in the figure, when there is no TFT leakage, the pixel TFT has a strong turn-off capability and the pixel electrode (PITO is in a floating state). Figure 3 As shown in the figure, when TFT leakage occurs, the pixel TFT's turn-off capability deteriorates, and a coupled waveform (PITO) appears on the pixel, causing the pixel's voltage level to fluctuate. In the sensing area, when the Touch IC outputs a modulation waveform for capacitance detection, due to the pixel's voltage level fluctuation, its coupled waveform differs from the modulation waveforms of other signals (Gate, Data, CITO), forming a coupling capacitor Cx. This additional coupling capacitor Cx is detected by the Touch IC, causing the transient capacitance value to be excessive, exceeding the reporting threshold, and manifesting as noise.

[0051] like Figure 1 As shown, in the no sensing area, the GOA circuit performs All gate on, that is, all GOA circuit signals are pulled high to VSP for a period of time to discharge the residual charge in the sub-pixel. Figure 4 As shown, at the rising edge of the Gate signal, the pixel voltage is coupled upward, but at this time the TFT is turned on and the pixel quickly returns to ground. At the falling edge of the Gate signal, the pixel voltage is coupled downward, but at this time the TFT is turned off, resulting in a pixel voltage difference of △Vp for the sub-pixel, causing residual charge in the sub-pixel. In the LWPG mode for a long time, the liquid crystal becomes polarized, and a flickering screen will appear when the screen is turned on again. The inventors of this case used the CA310 device and the FMA method to test the Flicker value of the grayscale image. It can be seen that compared to the display state before entering the LPWG mode, the Flicker value at this time is significantly increased, indicating that the brightness between the positive and negative frames at this time is greatly different due to the influence of the residual charge.

[0052] In order to solve the problem in the related art that the sensing area in the LPWG mode shows poor noise and the screen flickers in the nosensing area, an embodiment of the present invention provides a shift register, such as Figure 5 As shown, it includes a frame reset module 1, which is electrically connected to the frame reset control terminal STV0, the first power terminal VGL, the first node PU and the scan signal output terminal G_OUT(n) respectively; wherein,

[0053] like Figure 6-Figure 8 As shown, Figure 6-Figure 8 They are Figure 5 As shown in the timing diagram of the shift register in the LPWG mode, the frame reset module 1 is configured to, in the first phase T1 of the gesture wake-up mode (LPWG), respond to the control of the first voltage VSP of the frame reset control terminal STV0 to provide the second voltage VSN of the first power supply terminal VGL to the scan signal output terminal G_OUT(n); wherein the first voltage VSP is greater than or equal to the threshold voltage of the thin film transistor of the frame reset module 1, and the polarity of the second voltage (VSN) is opposite to the polarity of the first voltage VSP;

[0054] like Figure 6-Figure 8 As shown, the frame reset module 1 is configured to provide a first touch modulation voltage V1 to the frame reset control terminal STV0 and a second touch modulation voltage V2 to the first power supply terminal VGL in the second stage T2 of the gesture wake-up mode (LPWG); wherein the polarity of the second touch modulation voltage V2 is opposite to the polarity of the first touch modulation voltage V1.

[0055] The shift register provided by the embodiment of the present invention has the following characteristics: in the first stage (no sensing area) of LPWG, since the first voltage VSP of the frame reset control terminal is greater than or equal to the threshold voltage of the thin film transistor of the frame reset module, in the first stage, the thin film transistor controlled by the frame reset control terminal is in the on state, and the second voltage (VSN) of the first power supply terminal VGL is provided to the scan signal output terminal, so the voltage output by the scan signal output terminal is the second voltage (VSN). Therefore, the VSN output by the scan signal output terminal can control the TFT of the sub-pixel in the display area to turn off, thereby reducing the leakage current of the TFT in the sub-pixel. When performing touch detection in the second stage (sensing area), no additional coupling capacitance will be detected by the Touch IC to cause noise. At the same time, the present invention cancels the All gate on action in the no sensing area, that is, Figure 1 The time when VSP is pulled high and maintained can prevent the continuous change of Gate level from coupling with the pixel voltage. In this way, in LPWG mode, the pixel voltage is not coupled with any signal, solving the problem of screen flickering when the screen is turned on again.

[0056] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 6-Figure 8 As shown, the first stage T1 and the second stage T2 are performed alternately until the LPWG mode ends.

[0057] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 6-Figure 8As shown, the first voltage VSP is a positive voltage output by an external power supply, and the second voltage VSN is a negative voltage output by the external power supply. Specifically, the first voltage is generally 5V to 6.5V, and the second voltage is generally -6.5V to -5V.

[0058] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 6-Figure 8 As shown, the frequency of the first touch modulation voltage V1 is the same as the frequency of the second touch modulation voltage V2, for example, both are 70kHz~110kHz; the number of square waves of the first touch modulation voltage V1 is the same as the number of square waves of the second touch modulation voltage V2, for example, both are 4~12, and the embodiment of the present invention takes the number of square waves as 4 as an example.

[0059] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 6-Figure 8 As shown, the sum of the durations of the first phase, T1, and the second phase, T2 (i.e., the period), is typically 16.67ms to 50ms. The second phase, T2 (sensing zone), is the modulation area, which depends primarily on the detection time. The modulation length in the sensing zone is determined by the frequency of the modulating voltage and the number of square waves. The second phase, T2, is typically set to 600ns to 2ms, while the first phase, T1 (no sensing zone), is longer.

[0060] In a specific implementation, the frequency of sensing area detection in the LPWG mode is 20 Hz to 60 Hz.

[0061] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 9 As shown, Figure 9 for Figure 5 The actual timing diagram of the shift register in LPWG mode is shown. It can be seen that Figure 9 The timing and Figure 6-Figure 8 The timing is the same as shown, where the amplitude of the first touch modulation voltage V1 is formed by the superposition of two voltages, namely TVCL (0~1V) and TVCH (0~4V), where TVCL (0~1V) is Figure 6-Figure 8 The first step height in the T2 stage, TVCH (0~4V) is Figure 6-Figure 8 The height of the second step in the middle T2 phase, that is, the amplitude of the first touch modulation voltage V1 is 0-5V, and therefore the amplitude of the second touch modulation voltage V2 is -5V-0.

[0062] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5-Figure 8 As shown, it also includes:

[0063] The input module 2 is electrically connected to the input control terminal INPUT, the second power supply terminal VDD, and the first node PU respectively; the input module 2 is configured to provide the second voltage VSN to the second power supply terminal VDD in the first phase T1, and is configured to provide the second touch modulation voltage V2 to the second power supply terminal VDD in the second phase T2;

[0064] The row reset module 3 is electrically connected to the row reset control terminal G_OUT(n+1), the third power supply terminal VSS, and the first node PU respectively; the row reset module 3 is configured to provide the second voltage VSN to the third power supply terminal VSS in the first phase T1, and is configured to provide the second touch modulation voltage V2 to the third power supply terminal VSS in the second phase T2;

[0065] a node inverting module 4, the node inverting module 4 being electrically connected to the first power supply terminal VGL, the fourth power supply terminal GCH, the first node PU and the second node PD respectively;

[0066] The output module 5 is electrically connected to the clock signal terminal CLK, the first node PU and the scan signal output terminal G_OUT(n) respectively; the output module 5 is configured to input the second voltage VSN to the clock signal terminal CLK in the first stage T1, and is configured to input the second touch modulation voltage V2 to the clock signal terminal CLK in the second stage T2.

[0067] In the embodiment of the present invention, VDD, VSS, and CLK are set to the same voltage as VGL in the first and second stages, so as to ensure that the scan signal output terminal G_OUT(n) outputs a low voltage (the second voltage VSN) in the no-sensing area, thereby ensuring that the TFT of the pixel is in the off state and eliminating the touch noise problem caused by leakage current; at the same time, the embodiment of the present invention provides Figure 5 The shift register shown is provided with a row reset module 3, that is, a reset function for each row is added, so there is no problem of residual charge in the sub-pixels of the display area, so there is no need Figure 1 During the time when VSP is pulled high and maintained, the present invention cancels the All gate on action in the no sensing area. The voltage of the pixel in the no sensing area is not coupled by any signal, thereby solving the screen flickering phenomenon when the screen is lit again.

[0068] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5As shown, the frame reset module 1 includes a first switch transistor M1 and a second switch transistor M2; the gate of the first switch transistor M1 is electrically connected to the frame reset control terminal STV0, the first electrode of the first switch transistor M1 is electrically connected to the first power supply terminal VGL, and the second electrode of the first switch transistor M1 is electrically connected to the first node PU; the gate of the second switch transistor M2 is electrically connected to the frame reset control terminal STV0, the first electrode of the second switch transistor M2 is electrically connected to the first power supply terminal VGL, and the second electrode of the second switch transistor M2 is electrically connected to the scan signal output terminal G_OUT(n);

[0069] The input module 2 includes a third switching transistor M3, a gate of the third switching transistor M3 is electrically connected to the input control terminal INPUT, a first electrode of the third switching transistor M3 is electrically connected to the second power supply terminal VDD, and a second electrode of the third switching transistor M3 is electrically connected to the first node PU;

[0070] The row reset module 3 includes a fourth switch transistor M4, a gate of the fourth switch transistor M4 is electrically connected to the row reset control terminal G_OUT(n+1), a first electrode of the fourth switch transistor M4 is electrically connected to the third power supply terminal VSS, and a second electrode of the fourth switch transistor M4 is electrically connected to the first node PU;

[0071] The node inversion module 4 includes a fifth switch transistor M5, a sixth switch transistor M6, a seventh switch transistor M7, an eighth switch transistor M8, a ninth switch transistor M9 and a tenth switch transistor M10; the gate and the first electrode of the fifth switch transistor M5 are both electrically connected to the fourth power supply terminal GCH, the second electrode of the fifth switch transistor M5 is electrically connected to the gate of the sixth switch transistor M6 and the second electrode of the seventh switch transistor M7; the first electrode of the sixth switch transistor M6 is electrically connected to the fourth power supply terminal GCH, the second electrode of the sixth switch transistor M6 is electrically connected to the second node PD; the gate of the seventh switch transistor M7 is electrically connected to the first node PU, the first electrode of the seventh switch transistor M7 is electrically connected to the first power supply terminal VGL is electrically connected; a gate of the eighth switching transistor M8 is electrically connected to the first node PU, a first electrode of the eighth switching transistor M8 is electrically connected to the first power supply terminal VGL, and a second electrode of the eighth switching transistor M8 is electrically connected to the second node PD; a gate of the ninth switching transistor M9 is electrically connected to the second node PD, a first electrode of the ninth switching transistor M9 is electrically connected to the first power supply terminal VGL, and a second electrode of the ninth switching transistor M9 is electrically connected to the first node PU; a gate of the tenth switching transistor M10 is electrically connected to the second node PD, a first electrode of the tenth switching transistor M10 is electrically connected to the first power supply terminal VGL, and a second electrode of the tenth switching transistor M10 is electrically connected to the scan signal output terminal G_OUT(n);

[0072] The output module 5 includes an eleventh switching transistor M11 and a capacitor C, the gate of the eleventh switching transistor M11 is electrically connected to the first node PU, the first electrode of the eleventh switching transistor M11 is electrically connected to the clock signal terminal CLK, and the second electrode of the eleventh switching transistor M11 is electrically connected to the scan signal output terminal G_OUT(n).

[0073] The above is merely an example to illustrate the specific structure of each module in the shift register provided by the embodiment of the present invention. In specific implementation, the specific structure of the above modules is not limited to the above structure provided by the embodiment of the present invention, and can also be other structures known to those skilled in the art, which is not limited here.

[0074] It should be noted that the above embodiments of the present invention provide Figure 5 The shift register shown in the figure operates on the same principle as in related art during the display phase of the display device, primarily implementing signal shifting by scanning the signal output from the signal output terminal. Specifically, the output of G_OUT(n) is ultimately achieved through INPUT and CLK; the previous row signal is cleared through G_OUT(n+1) and VSS; VDD and GCH mutually pull the PU and PD, ensuring that the PD is low when the PU is high, and that the PD can be pulled low when the PD is high; after one frame, STV0 is used to force the PU and G_OUT(n) to be pulled low to prevent voltage fluctuations and output abnormalities.

[0075] In order to simplify the preparation process, in the specific implementation, in the embodiment of the present disclosure, as Figure 5 As shown, all switching transistors are N-type transistors, which are turned on under high voltage and turned off under low voltage.

[0076] It should be noted that the embodiment of the present invention chooses to use an 11T1C shift register that transmits signals more stably. Of course, the shift register is not limited to the 11T1C structure provided by the embodiment of the present invention, and can be other shift registers that can realize the shift function and have a frame reset function.

[0077] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5 and Figure 6 As shown, the input module 2 is further configured to input a second voltage VSN to the input control terminal INPUT in the first phase T1, and is configured to input a second touch modulation voltage V2 to the input control terminal INPUT in the second phase T2;

[0078] The node inversion module 4 is further configured to provide the second voltage VSN to the fourth power terminal GCH in the first phase T1 , and is configured to provide the second touch modulation voltage V2 to the fourth power terminal GCH in the second phase T2 .

[0079] In the embodiment of the present invention, by setting GCH and INPUT to the same voltage as VGL in the first and second stages, it can further ensure that the scan signal output terminal G_OUT(n) outputs a low voltage (the second voltage VSN) in the no-sensing area, thereby ensuring that the TFT of the pixel is in the off state and eliminating the touch noise problem caused by leakage current.

[0080] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5 and Figure 7 As shown, the node inversion module 4 is further configured to provide the first voltage VSP to the fourth power supply terminal GCH during the first phase T1, and to provide the first touch modulation voltage V1 to the fourth power supply terminal GCH during the second phase T2. Specifically, during the first phase T1, by raising the voltage of the fourth power supply terminal GCH to VSP, the voltage of the second node PD can be raised to ensure that the first node PU outputs a low voltage. At this time, the output of G_OUT(n) is also VSN, which does not affect the reduction of the leakage current of the TFT in the sub-pixel.

[0081] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5 and Figure 8 As shown, the node inversion module 4 is further configured to provide the first voltage VSP to the fourth power supply terminal GCH during the first phase T1, and to provide the first touch modulation voltage V1 to the fourth power supply terminal GCH during the second phase T2. The input module 2 is further configured to provide the first voltage VSP to the input control terminal INPUT during the first phase T1, and to input the first touch modulation voltage V1 to the input control terminal INPUT during the second phase T2. Specifically, during the first phase T1, by raising the voltage of the fourth power supply terminal GCH to VSP, the voltage of the second node PD can be raised to ensure that the first node PU outputs a low voltage. At this time, the output G_OUT(n) is also VSN, which does not affect the reduction of the leakage current of the TFT within the sub-pixel. During the first phase T1, by raising the voltage of the input control terminal INPUT to VSP, the third switching transistor M3 is turned on. However, since the voltage of the second power supply terminal VDD is the second voltage VSN, the first node PU can also be ensured to be a low voltage. At this time, the output G_OUT(n) is also VSN, which does not affect the reduction of the leakage current of the TFT within the sub-pixel.

[0082] It should be noted that Figure 6 Others in include INPUT, CLK, VGL, VDD, VSS and GCH, Figure 7 Others in include INPUT, CLK, VGL, VDD and VSS, Figure 8Others include CLK, VGL, VDD, and VSS.

[0083] from Figure 3 It can be seen that the TFT characteristics change after the reliability test, resulting in I off The increase causes the addition of coupling capacitance Cx, so the embodiment of the present invention is mainly to reduce I off Since the display device no longer has any display after entering LPWG mode, Figure 6 Taking the timing shown as an example, the input module, row reset module, node inversion module and output module all adopt a full pull-down design. The frame reset module can reduce the noise of G_OUT(n) and PU, which can further enhance the pixel TFT shutdown capability. Moreover, in the first stage T1, STV0 is pulled up to VSP, and other GOA circuit signals are pulled down to VSN. At this time, G_OUT(n) outputs a stable VSN, which enhances the pixel TFT's shutdown capability. After the reliability test, the pixel TFT's Ioff will not increase like the Ioff in the related art. The pixel TFT in the embodiment of the present invention can still be stably turned off, thereby avoiding the influence of the additional coupling capacitor Cx. Figure 10 As shown, Figure 10 A schematic diagram of a shift register (GOA) driving a row of sub-pixels (pixels) in a display area provided by an embodiment of the present invention, and Figure 10 Just a hint Figure 5 Among M1, M2 and M11, in the first stage T1 of the LPWG mode, STV0 is pulled high to VSP (indicated by STV0:H), the first power supply terminal VGL is pulled low to VSN (indicated by VGL:L), and the clock signal terminal CLK is pulled low to VSN (indicated by CLK:L). Therefore, M1 and M2 are both turned on, and VSN of the first power supply terminal VGL is transmitted to PU through M1 and to G_OUT(n) through M2. Therefore, PU is pulled low to VSN, and M11 is turned off. Therefore, G_OUT(n) outputs a stable VSN (indicated by G_OUT(n):L), and VSN controls the TFT in the sub-pixel (pixel(n), pixel(n+1)) to be turned off, thereby reducing the leakage current of the TFT in the sub-pixel.

[0084] In a specific implementation, in the above shift register provided in the embodiment of the present invention, as Figure 5-Figure 8 As shown, all control terminals (STV0, INPUT), clock signal terminals CLK and power terminals (VGL, VDD, VSS, GCH) of the shift register are configured to input the ground voltage GND in the black screen phase (SLPIN). Specifically, in the black screen phase, the display of the display device ends.

[0085] Below Figure 6The timing shown is an example of Figure 5 The working principle of the shift register (GOA) shown in the figure is explained in LPWG mode:

[0086] like Figure 5 and Figure 6 As shown, when the display ends and enters the black screen stage (SLPIN), Figure 5 All GOA circuit signals shown are input to ground voltage GND. When entering LPWG mode, in the first phase T1 (no sensing region), STV0 is pulled high to VSP, while the other GOA circuit signals (others) are pulled low to VSN. This causes G_OUT(n) to output VSN, turning off the pixel TFT and reducing leakage current. In the second phase T2 (sensing region), STV0 is modulated at VSP, while the other GOA circuit signals (others) are modulated at VSN. This causes G_OUT(n) to also output VSN, collecting touch signals and enabling touch control. The first and second phases T1 and T2 then alternate until exiting LPWG mode, at which point all GOA circuit signals are input to ground voltage GND.

[0087] Specifically, in LPWG mode, the GOA circuit signal levels can only be set to VSP (+6V), VSN (-6V), and GND (0V). Therefore, compared to the bright screen state, the GOA circuit signals do not reach the turn-on voltage (+12V) and turn-off voltage (-12V) required by the pixel TFT. Figure 1 As shown in the timing, in the no sensing area, G_OUT(n) is in the floating state, and the Pixel TFT has no external driving voltage. off When enlarged, the pixel TFT can be similar to the open state. Figure 6-Figure 8 The solution shown in the figure pulls STV0 up to VSP in the no sensing area, and M1 is turned on to further pull down the first node PU to prevent G_OUT(n) from being pulled up due to leakage in M11; M2 is turned on to pull G_OUT(n) down to VSN. Although it does not have a strong shutdown capability of VGL (-12V), it is better than the related art. Figure 1 The solution shown in the figure can effectively reduce the I off .

[0088] The following is the use of relevant technologies to collect the Touch IC Figure 1 The timing shown and the embodiment of the present invention provide Figure 6The timing shown is compared with the Touch signal in the sensing area. Figure 11 As shown on the left, it can be clearly seen that in the related technology, in the bright screen state (Screen on), the raw value (measured Touch signal quantity) is about 8500, and in the dark screen state (Screen off), that is, in the LPWG mode, the raw value (measured Touch signal quantity) is about 8500. off The coupling capacitance between the pixel and the touch electrode block (sensor block) is detected by the Touch IC, and the raw value gradually increases until it stabilizes at around 10500. Therefore, in the related art, the raw value increases in LPWG mode, and the Baseline (reference signal quantity) is established when power is applied in LPWG mode, which is manifested as an increase in Noise (Rawdata-Baseline). Figure 11 As shown on the right, the solution provided by the embodiment of the present invention is still around 8500 in the bright screen state. After entering the LPWG mode, the pixel TFT is stably turned off, and the pixel is in a high-impedance state relative to the touch electrode block. The coupling capacitance between the pixel and the touch electrode block is not introduced. In the LPWG mode, the raw value remains unchanged at around 8500, and the noise does not increase, which is OK. Therefore, the solution provided by the embodiment of the present invention is stable. Figure 6 The timing shown can reduce the leakage current of the pixel TFT and avoid the noise problem during touch detection in the sensing area.

[0089] As shown in Table 1 below, Table 1 is a table of flicker data measured for three random display devices (sample #1, sample #2, and sample #3) after 2 hours of standby in LPWG mode. The experimental data is the flicker value of the purple-green FLK screen tested using the CA310 device and the FMA method. It can be seen that before entering the LPWG mode (Before), the flicker data of the three samples are very small, and there is no obvious difference in the brightness of the positive and negative frames; using the embodiment of the present invention provided Figure 6 The GOA timing shown in the figure shows that after 2 hours of LPWG mode, the flicker value of the three samples changes by only 1.3% at most, which means there is no significant change and is far less than the specified range (<10%). Figure 1 As shown in the GOA timing, after 2 hours in LPWG mode, the flicker values ​​of the three samples increase significantly, thus further verifying that the embodiment of the present invention can solve the screen flickering problem when the screen is turned on again after the LPWG mode.

[0090] Table 1

[0091] Purple-green FLK LPWG duration Before After After the present invention sample#1 2h 2.9％ 28.3％ 4.2％ sample#2 2h 3.6％ 38.8％ 3.8％ sample#3 2h 2.5％ 34.7％ 3.2％

[0092] It should be noted that other essential components of the shift register are well understood by those skilled in the art and are not described in detail herein and should not be construed as limiting the present invention.

[0093] Based on the same inventive concept, an embodiment of the present invention provides a control timing sequence of a shift register, which is used to drive the control timing sequence provided by the present invention. Figure 5 The shift register shown, such as Figure 12 As shown, the control sequence includes:

[0094] S1201: In a first stage of a gesture wake-up mode, a frame reset control terminal provides a first voltage, and a first power terminal provides a second voltage; wherein the first voltage is greater than or equal to a threshold voltage of a thin film transistor of a frame reset module, and a polarity of the second voltage is opposite to that of the first voltage;

[0095] S1202. In the second stage of the gesture wake-up mode, the frame reset control terminal provides a first touch modulation voltage, and the first power supply terminal provides a second touch modulation voltage; wherein the polarity of the second touch modulation voltage is opposite to that of the first touch modulation voltage.

[0096] Among them, the driving principle and specific implementation of the control timing are the same as those of the shift register in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register in the above embodiment, and will not be repeated here.

[0097] Based on the same inventive concept, an embodiment of the present invention provides a display device, such as Figure 13 As shown, the display panel 1 includes a display area AA and a non-display area BB arranged around the display area AA. The non-display area BB includes a gate drive circuit 2. The gate drive circuit 2 includes a plurality of cascaded embodiments of the present invention. Figure 5 Since the principle of the display device to solve the problem is similar to that of the above shift register, the implementation of the display device can refer to the embodiment of the above shift register, and the repeated parts will not be repeated.

[0098] It should be noted that Figure 13 The scanning signal output terminals (not shown) of the shift registers in the gate driving circuit 2 are electrically connected to the gate lines (not shown) in the display area AA in a one-to-one correspondence.

[0099] The display device may be an LCD (Liquid Crystal Display), such as an Advanced Super Dimension Switch (ADS) LCD; or it may be any product or component with a display function, such as a television, digital camera, mobile phone, or tablet computer, that incorporates such a display device. Such a display device has an extremely low risk of screen flicker or flicker drift, and features excellent brightness uniformity, superior display quality, and high product quality.

[0100] In some embodiments, the above-mentioned display device provided by the embodiments of the present invention can be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function.

[0101] The embodiment of the present invention provides a shift register, its control timing and display device. In the first stage of LPWG (no sensing area), since the first voltage VSP of the frame reset control terminal is greater than or equal to the threshold voltage of the thin film transistor of the frame reset module, the thin film transistor controlled by the frame reset control terminal is in the on state in the first stage, and the second voltage (VSN) of the first power supply terminal VGL is provided to the scan signal output terminal. Therefore, the voltage output by the scan signal output terminal is the second voltage (VSN). Therefore, the VSN output by the scan signal output terminal can control the TFT of the sub-pixel in the display area to turn off, thereby reducing the leakage current of the TFT in the sub-pixel. When performing touch detection in the second stage (sensing area), no additional coupling capacitance will be detected by the Touch IC to cause noise. At the same time, the present invention cancels the All gateon action in the no sensing area, that is, Figure 1 The time when VSP is pulled high and maintained can prevent the continuous change of Gate level from coupling with the pixel voltage. In this way, in LPWG mode, the pixel voltage is not coupled with any signal, solving the problem of screen flickering when the screen is turned on again.

[0102] Although the present invention has described preferred embodiments, it should be understood that those skilled in the art may make various changes and modifications to the embodiments without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A shift register, characterized in that: It includes a frame reset module, which is electrically connected to the frame reset control terminal, the first power supply terminal, the first node and the scan signal output terminal respectively; wherein, The frame reset module is configured to, in a first stage of a gesture wake-up mode, output a second voltage of the first power supply terminal through the scan signal output terminal in response to control of the first voltage of the frame reset control terminal; wherein the first voltage is greater than or equal to a threshold voltage of a thin film transistor of the frame reset module, and the polarity of the second voltage is opposite to that of the first voltage, and the second voltage controls the thin film transistor of the sub-pixel to turn off; The frame reset module is configured to output the second touch modulation voltage of the first power supply end through the scanning signal output end in response to the control of the first touch modulation voltage of the frame reset control end in the second stage of the gesture wake-up mode; wherein the polarity of the second touch modulation voltage is opposite to the polarity of the first touch modulation voltage.

2. The shift register according to claim 1, wherein: The first voltage is a positive voltage output by an external power supply, and the second voltage is a negative voltage output by the external power supply.

3. The shift register according to claim 2, wherein: The first voltage is 5V to 6.5V, and the second voltage is -6.5V to -5V.

4. The shift register according to claim 1, wherein: The frequency of the first touch modulation voltage is the same as the frequency of the second touch modulation voltage, and the number of square waves of the first touch modulation voltage is the same as the number of square waves of the second touch modulation voltage.

5. The shift register according to claim 4, wherein: The frequencies of the first touch modulation voltage and the second touch modulation voltage are both 70 kHz to 110 kHz, and the numbers of square waves of the first touch modulation voltage and the second touch modulation voltage are both 4 to 12.

6. The shift register according to claim 5, wherein: The amplitude of the first touch modulation voltage is 0V to 5V, and the amplitude of the second touch modulation voltage is -5V to 0.

7. The shift register according to claim 1, wherein: The sum of the duration of the first stage and the duration of the second stage is 16.67ms to 50ms, and the duration of the second stage is 600ns to 2ms.

8. The shift register according to any one of claims 1 to 7, wherein: Also includes: an input module, the input module being electrically connected to the input control terminal, the second power supply terminal and the first node respectively; The input module is configured to provide the second voltage to the second power supply terminal in the first phase, and is configured to provide the second touch modulation voltage to the second power supply terminal in the second phase; a row reset module, the row reset module being electrically connected to the row reset control terminal, the third power supply terminal, and the first node, respectively; the row reset module being configured to provide the second voltage to the third power supply terminal in the first phase, and being configured to provide the second touch modulation voltage to the third power supply terminal in the second phase; a node inverting module, the node inverting module being electrically connected to the first power supply terminal, the fourth power supply terminal, the first node, and the second node respectively; An output module, wherein the output module is electrically connected to the clock signal terminal, the first node and the scan signal output terminal respectively; the output module is configured to input the second voltage to the clock signal terminal in the first stage, and is configured to input the second touch modulation voltage to the clock signal terminal in the second stage.

9. The shift register according to claim 8, wherein: The input module is further configured to input the second voltage to the input control terminal in the first phase, and is configured to input the second touch modulation voltage to the input control terminal in the second phase; The node inversion module is further configured to provide the second voltage to the fourth power terminal in the first phase, and is configured to provide the second touch modulation voltage to the fourth power terminal in the second phase.

10. The shift register according to claim 8, wherein: The node inversion module is further configured to provide the first voltage to the fourth power terminal in the first phase, and is configured to provide the first touch modulation voltage to the fourth power terminal in the second phase.

11. The shift register according to claim 10, wherein: The input module is further configured to provide the first voltage to the input control terminal in the first phase, and is configured to input the first touch modulation voltage to the input control terminal in the second phase.

12. The shift register according to any one of claims 1 to 7 and 9 to 11, wherein: All control terminals, clock signal terminals and power supply terminals of the shift register are configured to input ground voltage in the black screen phase.

13. The shift register according to claim 8, wherein: The frame reset module includes a first switching transistor and a second switching transistor; the gate of the first switching transistor is electrically connected to the frame reset control terminal, the first electrode of the first switching transistor is electrically connected to the first power supply terminal, and the second electrode of the first switching transistor is electrically connected to the first node; the gate of the second switching transistor is electrically connected to the frame reset control terminal, the first electrode of the second switching transistor is electrically connected to the first power supply terminal, and the second electrode of the second switching transistor is electrically connected to the scan signal output terminal; The input module includes a third switch transistor, wherein a gate of the third switch transistor is electrically connected to the input control terminal, a first electrode of the third switch transistor is electrically connected to the second power supply terminal, and a second electrode of the third switch transistor is electrically connected to the first node; The row reset module includes a fourth switch transistor, a gate of the fourth switch transistor is electrically connected to the row reset control terminal, a first electrode of the fourth switch transistor is electrically connected to the third power supply terminal, and a second electrode of the fourth switch transistor is electrically connected to the first node; The node inversion module includes a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, and a tenth switching transistor; the gate and the first electrode of the fifth switching transistor are both electrically connected to the fourth power supply terminal, the second electrode of the fifth switching transistor is electrically connected to the gate of the sixth switching transistor and the second electrode of the seventh switching transistor; the first electrode of the sixth switching transistor is electrically connected to the fourth power supply terminal, and the second electrode of the sixth switching transistor is electrically connected to the second node; the gate of the seventh switching transistor is electrically connected to the first node, and the first electrode of the seventh switching transistor is electrically connected to the first power supply terminal; the gate of the eighth switching transistor is electrically connected to the first node, the first electrode of the eighth switching transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth switching transistor is electrically connected to the second node; the gate of the ninth switching transistor is electrically connected to the second node, the first electrode of the ninth switching transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth switching transistor is electrically connected to the first node; The gate of the tenth switch transistor is electrically connected to the second node, the first electrode of the tenth switch transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth switch transistor is electrically connected to the scan signal output terminal; The output module includes an eleventh switching transistor and a capacitor, the gate of the eleventh switching transistor is electrically connected to the first node, the first electrode of the eleventh switching transistor is electrically connected to the clock signal end, and the second electrode of the eleventh switching transistor is electrically connected to the scan signal output end.

14. A control timing of a shift register, wherein the control timing is used to drive the shift register according to any one of claims 1 to 13, wherein: The control sequence includes: In the first stage of the gesture wake-up mode, the frame reset control terminal provides a first voltage, and the first power supply terminal provides a second voltage; wherein the first voltage is greater than or equal to a threshold voltage of the thin film transistor of the frame reset module, and the polarity of the second voltage is opposite to that of the first voltage; In the second stage of the gesture wake-up mode, the frame reset control terminal provides a first touch modulation voltage, and the first power supply terminal provides a second touch modulation voltage; wherein the polarity of the second touch modulation voltage is opposite to that of the first touch modulation voltage.

15. A display device, characterized in that: The invention comprises a display panel, wherein the display panel comprises a display area and a non-display area arranged around the display area, the non-display area comprises a gate drive circuit, and the gate drive circuit comprises a plurality of cascaded shift registers according to any one of claims 1 to 13.

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