Bandgap reference circuit and bandgap reference source circuit

Abstract

A bandgap reference circuit and a bandgap reference source circuit, the bandgap reference circuit comprises: a cascode current mirror, a first cascode unit, a first operational amplifier unit and an output unit, wherein: the first cascode unit is coupled to the cascode current mirror and is suitable for mirroring the output current of the cascode current mirror; its output end is coupled to the bias input end of the first operational amplifier unit; the first operational amplifier unit, its first input end is coupled to the second branch of the cascode current mirror, its second input end is coupled to the first branch of the cascode current mirror, and its output end is coupled to the control end of the cascode current mirror; the output unit, its control end is coupled to the control end of the cascode current mirror, and its output end outputs a reference voltage. The above scheme can improve the accuracy of the mirror current and the power supply rejection ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a bandgap reference circuit and a bandgap reference source circuit. Background Art

[0002] As the scale of integrated circuits becomes larger and larger, the size of semiconductor processes decreases, and the process line width decreases, low voltage and low power consumption have become the development trend. At the same time, facing the noise of power supply in mixed signal circuit systems, high power supply rejection ratio is also an inevitable requirement. Therefore, high power supply rejection ratio bandgap reference sources suitable for low voltage structures have broad application space and prospects.

[0003] Under the combined effects of low voltage, low temperature and slow process corner conditions, the voltage margin consumed by the current mirror part of the bandgap reference circuit is extremely limited. Since the drain-source voltage is depressed, the mirror current accuracy is poor and the power supply rejection ratio is low. Summary of the invention

[0004] The embodiment of the present invention solves the technical problems of poor mirror current accuracy and low power supply rejection ratio in a bandgap reference circuit.

[0005] To solve the above technical problems, an embodiment of the present invention provides a bandgap reference circuit, comprising: a cascade current mirror, a first cascade unit, a first operational amplifier unit and an output unit, wherein: the first cascade unit is coupled to the cascade current mirror and is suitable for mirroring the output current of the cascade current mirror; its output end is coupled to the bias input end of the first operational amplifier unit; the first operational amplifier unit, its first input end is coupled to the second branch of the cascade current mirror, its second input end is coupled to the first branch of the cascade current mirror, and its output end is coupled to the control end of the cascade current mirror; the output unit, its control end is coupled to the control end of the cascade current mirror, and its output end outputs a reference voltage.

[0006] Optionally, the bandgap reference circuit further includes: a clamping unit, configured to clamp the voltage on the second branch of the common-source and common-gate current mirror to the reference voltage.

[0007] Optionally, the clamping unit includes a second operational amplifier unit, wherein: the second operational amplifier unit has a first input terminal coupled to the second branch of the common-source and common-gate current mirror, a second input terminal coupled to the output unit, and an output terminal coupled to the control terminal of the output unit.

[0008] Optionally, the cascade current mirror includes a first current mirror unit and a second current mirror unit; the control end of the first current mirror unit is coupled to the output end of the first operational amplifier unit, the first end of the first cascade unit, and the first end of the output unit; the control end of the second current mirror unit is coupled to the second end of the first cascade unit.

[0009] Optionally, the common-source and common-gate current mirror includes: a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein: the first PMOS tube, its source inputs the power supply voltage, its gate is coupled to the gate of the second PMOS tube, and its drain is coupled to the source of the third PMOS tube; the second PMOS tube, its source inputs the power supply voltage, its gate is coupled to the output end of the first operational amplifier unit, and its drain is coupled to the source of the fourth PMOS tube; the third PMOS tube, its gate is coupled to the gate of the fourth PMOS tube, and its drain is coupled to the second input end of the first operational amplifier unit; the fourth PMOS tube, its drain is coupled to the first input end of the first operational amplifier unit; the first PMOS tube and the second PMOS tube constitute the first current mirror unit; the third PMOS tube and the fourth PMOS tube constitute the second current mirror unit.

[0010] Optionally, the common-source and common-gate current mirror also includes: a first resistor, a second resistor, a third resistor, a first diode and a second diode, wherein: the first resistor, a first end thereof is coupled to the drain of the third PMOS tube, and a second end thereof is grounded; the first diode, a positive electrode thereof is coupled to the drain of the third PMOS tube, and a negative electrode thereof is grounded; the second resistor, a first end thereof is coupled to the drain of the fourth PMOS tube, and a second end thereof is coupled to the first end of the third resistor and the positive electrode of the second diode; the third resistor, a second end thereof is grounded; the second diode, a positive electrode thereof is coupled to the first end of the third resistor, and a negative electrode thereof is grounded.

[0011] Optionally, the output unit includes: a fifth PMOS tube and a sixth PMOS tube, and a fourth resistor, wherein: the fifth PMOS tube has a source input power supply voltage, a gate coupled to the output end of the first operational amplifier unit, and a drain coupled to the source of the sixth PMOS tube; the sixth PMOS tube has a gate coupled to the control end of the second current mirror unit, and a drain coupled to the first end of the fourth resistor and the output end of the output unit; the fourth resistor has a second end connected to ground.

[0012] Optionally, the second operational amplifier unit has a first input terminal coupled to the drain of the second PMOS tube, a second input terminal coupled to the drain of the fifth PMOS tube, and an output terminal coupled to the gate of the sixth PMOS tube.

[0013] Optionally, the first common-source and common-gate unit includes: a seventh PMOS tube and an eighth PMOS tube, wherein: the seventh PMOS tube has a source input power supply voltage, a gate coupled to the output end of the first operational amplifier unit, and a drain coupled to the source of the eighth PMOS tube; the eighth PMOS tube has a gate coupled to the control end of the second current mirror unit, and a source coupled to the output end of the first common-source and common-gate unit.

[0014] An embodiment of the present invention further provides a bandgap reference source circuit, comprising a startup circuit and any one of the bandgap reference circuits described above; wherein: the startup circuit is coupled to the bandgap reference circuit and is suitable for outputting a startup current to the bandgap reference circuit.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] The bias current input to the bias input terminal of the first operational amplifier unit in the bandgap reference circuit is a zero temperature coefficient current generated by the bandgap reference circuit itself. The consistency of the temperature coefficient makes the output terminal voltage of the first operational amplifier unit consistent with its symmetric terminal voltage, that is, the gate voltage of the PMOS current mirror inside the first operational amplifier unit is equal to the gate voltage of the current mirror composed of the first PMOS tube and the second PMOS tube, which ensures the accurate replication of the current and reduces the influence of high-frequency power supply ripple and temperature on the bandgap reference circuit.

[0017] Furthermore, by providing a clamping unit, the voltage on the second branch of the common-source and common-gate current mirror is made equal to the voltage on the output unit, which can further improve the accurate replication of the current.

[0018] In addition, the second operational amplifier unit is used as the clamping unit. On the basis of achieving the clamping effect, the impedance of the PMOS tube in the output unit is increased by times the intrinsic gain of the second operational amplifier unit, reducing the voltage division of the resistor in the output unit, which can further improve the power supply rejection ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a circuit structure diagram of a bandgap reference circuit in an embodiment of the present invention;

[0020] Figure 2 is a circuit structure diagram of another bandgap reference circuit in an embodiment of the present invention;

[0021] Figure 3is a circuit structure diagram of a bandgap reference source circuit in an embodiment of the present invention;

[0022] Figure 4 4 is a circuit structure diagram of an operational amplifier unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As described in the background art above, the existing bandgap reference circuit has the problems of poor mirror current accuracy and low power supply rejection ratio.

[0024] In the embodiment of the present invention, the bias current input to the bias input terminal of the first operational amplifier unit in the bandgap reference circuit is a zero temperature coefficient current generated by the bandgap reference circuit itself. The consistency of the temperature coefficient makes the output terminal voltage of the first operational amplifier unit consistent with its symmetric terminal voltage, that is, the gate voltage of the PMOS current mirror inside the first operational amplifier unit is equal to the gate voltage of the current mirror composed of the first PMOS tube and the second PMOS tube, thereby ensuring the accurate replication of the current and reducing the influence of high-frequency power supply ripple and temperature on the bandgap reference circuit.

[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] An embodiment of the present invention provides a bandgap reference circuit, comprising: a cascode current mirror, a first cascode unit, a first operational amplifier unit, and an output unit.

[0027] In an embodiment of the present invention, the first cascode unit may be coupled to a cascode current mirror, and is suitable for mirroring an output current of the cascode current mirror; the output terminal of the first cascode unit may be coupled to a bias input terminal of the first operational amplifier unit;

[0028] A first input terminal of the first operational amplifier unit is coupled to a second branch of the cascode current mirror, a second input terminal of the first operational amplifier unit is coupled to a first branch of the cascode current mirror, and an output terminal of the first operational amplifier unit is coupled to a control terminal of the cascode current mirror;

[0029] The output unit has a control terminal coupled to the control terminal of the common-source common-gate current mirror, and an output terminal thereof outputs a reference voltage.

[0030] Reference Figure 1 , a circuit structure diagram of a bandgap reference circuit in an embodiment of the present invention is given. Figure 1 , the bandgap reference circuit provided in the above embodiments of the present invention is described in detail.

[0031] In a specific implementation, the cascode current mirror may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, wherein:

[0032] The source of the first PMOS tube MP1 is input with a power supply voltage, the gate of the first PMOS tube MP1 is coupled with the gate of the second PMOS tube MP2, and the drain of the first PMOS tube MP1 is coupled with the source of the third PMOS tube MP3;

[0033] The source of the second PMOS tube MP2 is input with a power supply voltage, the gate of the second PMOS tube MP2 is coupled to the output end of the first operational amplifier unit A1, and the drain of the second PMOS tube MP2 is coupled to the source of the fourth PMOS tube MP4;

[0034] The gate of the third PMOS tube MP3 is coupled to the gate of the fourth PMOS tube MP4, and the drain of the third PMOS tube MP3 is coupled to the second input terminal of the first operational amplifier unit A1;

[0035] The drain of the fourth PMOS transistor MP4 is coupled to the first input terminal of the first operational amplifier unit A1 ; the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor MP4 are externally connected to the external bias voltage Vb.

[0036] In a specific implementation, the first PMOS transistor MP1 and the second PMOS transistor MP2 can form a first current mirror unit, and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 can form a second current mirror unit. The gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 can be coupled to the output terminal of the first operational amplifier unit A1.

[0037] In a specific implementation, the cascode current mirror may further include a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1 and a second diode D2, wherein:

[0038] A first end of the first resistor R1 is coupled to the drain of the third PMOS transistor MP3, and a second end of the first resistor R1 is grounded;

[0039] The anode of the first diode D1 is coupled to the drain of the third PMOS transistor MP3, and the cathode of the first diode D1 is grounded;

[0040] A first end of the second resistor R2 is coupled to the drain of the fourth PMOS transistor MP4, and a second end of the second resistor R2 is coupled to a first end of the third resistor R3 and an anode of the first diode D1;

[0041] A second end of the third resistor R3 is grounded;

[0042] An anode of the second diode D2 is coupled to the first end of the third resistor R3 , and a cathode of the second diode D2 is grounded.

[0043] In a specific implementation, the resistance values ​​of the second resistor R2 and the third resistor R3 may be equal.

[0044] Reference Figure 1 The first branch of the cascode current mirror includes a first PMOS tube MP1, a third PMOS tube MP3, a first resistor R1 and a first diode D1, and the second branch of the cascode current mirror includes a second PMOS tube MP2, a fourth PMOS tube MP4, a second resistor R2, a third resistor R3 and a second diode D2.

[0045] In a specific implementation, the common-source common-gate current mirror may include two control terminals, a first control terminal and a second control terminal, wherein: the first control terminal is set at the gate of the first PMOS tube MP1 and the second PMOS tube MP2; the second control terminal is set at the gate of the third PMOS tube MP3 and the fourth PMOS tube MP4.

[0046] In the embodiment of the present invention, the first input terminal of the first operational amplifier unit A1 is coupled to the second branch of the common-source common-gate current mirror, specifically, the first input terminal of the first operational amplifier unit A1 is coupled to the drain of the fourth PMOS tube MP4; the second input terminal of the first operational amplifier unit A1 is coupled to the first branch of the common-source common-gate current mirror, specifically, the first input terminal of the first operational amplifier unit A1 is coupled to the drain of the third PMOS tube MP3.

[0047] In a specific implementation, the first input terminal of the first operational amplifier unit A1 may be a non-inverting input terminal “+”, and the second input terminal of the first operational amplifier unit A1 may be an inverting input terminal “−”.

[0048] In the embodiment of the present invention, the output unit includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a fourth resistor R4, wherein:

[0049] The source of the fifth PMOS tube MP5 is input with the power supply voltage, the gate of the fifth PMOS tube MP5 is coupled with the control end of the first current mirror unit and the output end of the first operational amplifier unit A1, and the drain of the fifth PMOS tube MP5 is coupled with the source of the sixth PMOS tube MP6;

[0050] The gate of the sixth PMOS tube MP6 is coupled to the control end of the second current mirror unit, and the drain of the sixth PMOS tube MP6 is coupled to the first end of the fourth resistor R4; the drain of the sixth PMOS tube MP6 is coupled to the output end of the output unit (the drain of the sixth PMOS tube MP6 can also be regarded as the output end of the output unit);

[0051] A second terminal of the fourth resistor R4 is grounded.

[0052] In a specific implementation, the gate of the sixth PMOS transistor MP6 can be used as the control terminal of the output unit.

[0053] Those skilled in the art will appreciate that the purpose of providing the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 is to form a corresponding voltage drop, which can be specifically achieved by components with impedance. In other words, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can also be other types of impedance units, and the specific type of the impedance unit is not limited here.

[0054] In a specific implementation, the first cascode unit may include a seventh PMOS transistor MP7 and an eighth PMOS transistor MP8, wherein:

[0055] A source of the seventh PMOS tube MP7 is input with a power supply voltage, a gate of the seventh PMOS tube MP7 is coupled to a first control terminal of the common-source common-gate current mirror, and a drain of the seventh PMOS tube MP7 is coupled to a source of the eighth PMOS tube MP8;

[0056] The gate of the eighth PMOS transistor MP8 is coupled to the second control terminal of the common-source common-gate current mirror, and the drain of the eighth PMOS transistor MP8 is coupled to the bias input terminal of the first operational amplifier unit A1. The bias input terminal of the first operational amplifier unit A1 inputs the bias current Ib.

[0057] Specifically, refer to Figure 1 The gate of the seventh PMOS tube MP7 is coupled to the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2, and the gate of the eighth PMOS tube MP8 is coupled to the gate of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4.

[0058] In an embodiment of the present invention, the bandgap reference circuit may further include a clamping unit for clamping the voltage on the second branch of the common-source common-gate current mirror and the voltage on the output unit so that the voltage on the second branch of the common-source common-gate current mirror is equal to the voltage on the output unit.

[0059] Reference Figure 2 , another bandgap reference circuit in an embodiment of the present invention is given.

[0060] In a specific implementation, the clamping unit may include a second operational amplifier unit A2. The first input terminal of the second operational amplifier unit A2 may be coupled to the second branch of the common-source common-gate current mirror, and the voltage drop on the second branch may be input; the second input terminal of the second operational amplifier unit A2 may be coupled to the output unit, and the voltage drop on the output unit may be input; the output terminal of the second operational amplifier unit A2 may be coupled to the control terminal of the output unit. When there is a deviation between the voltage drop on the second branch and the voltage drop on the output unit, the second operational unit controls the output of the output unit, thereby realizing the clamping function.

[0061] In a specific implementation, the first input terminal of the second operational amplifier unit A2 can be coupled to the drain of the second PMOS tube MP2 and the source of the fourth PMOS tube MP4, the second input terminal of the second operational amplifier unit A2 can be coupled to the drain of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6, and the output terminal of the second operational amplifier unit A2 is coupled to the gate of the sixth PMOS tube MP6.

[0062] By adding the second operational amplifier unit A2, the drain voltage of the second PMOS tube MP2 and the drain voltage of the fifth PMOS tube MP5 are clamped, and the output end of the second operational amplifier unit A2 is connected to the gate of the sixth PMOS tube MP6. Since the on-state voltage of the diode in the PMOS tube varies greatly with the PVT conditions (process, voltage and temperature), there may be a large difference between the drain voltage of the second PMOS tube MP2 and the drain voltage of the fifth PMOS tube MP5. Since the second operational amplifier unit A2 is used as the clamping unit, the drain voltage of the second PMOS tube MP2 is approximately equal to the drain voltage of the fifth PMOS tube MP5, and accurate replication of the current is achieved.

[0063] In addition, the second operational amplifier unit A2 and the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a gain-enhanced structure, so that its output impedance is increased by times the intrinsic gain of the second operational amplifier unit A2 of the original impedance, reducing the voltage division of the fourth resistor R4, and also improving the power supply rejection ratio.

[0064] In summary, it can be seen that in the embodiment of the present invention, the bias current input to the bias input terminal of the first operational amplifier unit in the bandgap reference circuit is a zero temperature coefficient current generated by the bandgap reference circuit itself. The consistency of the temperature coefficient makes the output terminal voltage of the first operational amplifier unit consistent with its symmetric terminal voltage, that is, the gate voltage of the PMOS current mirror inside the first operational amplifier unit is equal to the gate voltage of the current mirror formed by the first PMOS tube MP1 and the second PMOS tube MP2, which ensures the accurate replication of the current and reduces the influence of high-frequency power supply ripple and temperature on the bandgap reference circuit.

[0065] Reference Figure 3 , a bandgap reference source circuit in an embodiment of the present invention is given, including a start-up circuit and a bandgap reference circuit provided in the above embodiment. Figure 1 or Figure 2 Provide explanation.

[0066] In a specific implementation, the startup circuit may include a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth PMOS transistor MP16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, and a nineteenth NMOS transistor MN19, wherein:

[0067] The source of the seventh PMOS tube MP7 is input with the power supply voltage VDD, the gate of the seventh PMOS tube MP7 is coupled with the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2, and the drain of the seventh PMOS tube MP7 is coupled with the source of the eighth PMOS tube MP8;

[0068] The gate of the eighth PMOS transistor MP8 is coupled to the gate of the seventh PMOS transistor MP7, and the drain of the eighth PMOS transistor MP8 is coupled to the bias input terminal of the first operational amplifier unit A1; the bias input terminal of the first operational amplifier unit A1 inputs the bias current I4U (that is, the above-mentioned Ib);

[0069] The source of the ninth PMOS tube MP9 is input with the power supply voltage, the gate of the ninth PMOS tube MP9 is coupled with the gate of the seventh PMOS tube MP7 and the gate of the tenth PMOS tube MP10, and the drain of the ninth PMOS tube MP9 is coupled with the source of the tenth PMOS tube MP10;

[0070] The drain of the tenth PMOS transistor MP10 is coupled to the gates of the sixteenth PMOS transistor MP16 and the seventeenth NMOS transistor MN17;

[0071] The gate of the eleventh PMOS tube MP11 is coupled to the drain of the sixteenth PMOS tube MP16 and the drain of the seventeenth NMOS tube MN17, the source of the eleventh PMOS tube MP11 inputs the bias current IB2_4U, and the drain of the eleventh PMOS tube MP11 is coupled to the drain of the eighth PMOS tube MP8;

[0072] The drain of the twelfth NMOS tube MN12 is coupled to the drain of the tenth PMOS tube MP10, the gate of the twelfth NMOS tube MN12 inputs the enable signal ENB, and the source of the twelfth NMOS tube MN12 is grounded;

[0073] The drain of the thirteenth NMOS tube MN13 is coupled to the drain of the fourteenth NMOS tube and the drain of the fifteenth NMOS tube MN15, the gate of the thirteenth NMOS tube MN13 is input with the voltage VIN, and the source of the thirteenth NMOS tube MN13 is grounded;

[0074] The gate of the fourteenth NMOS tube MN14 is input with the voltage VIP, and the source of the fourteenth NMOS tube MN14 is grounded;

[0075] The gate of the fifteenth NMOS transistor MN15 is input with the voltage VREF, and the source of the fifteenth NMOS transistor MN15 is grounded;

[0076] The source of the sixteenth PMOS tube MP16 is input with the power supply voltage VDD, and the drain of the sixteenth PMOS tube MP16 is coupled with the drain of the seventeenth NMOS tube MN17;

[0077] The source of the seventeenth NMOS tube MN17 is grounded;

[0078] The gate of the eighteenth NMOS tube MN18 is input with the enable signal EN, the drain of the eighteenth NMOS tube MN18 is coupled with the gate of the ninth PMOS tube MP9, and the source of the eighteenth NMOS tube MN18 is coupled with the drain of the nineteenth NMOS tube MN19;

[0079] The source of the nineteenth NMOS transistor MN19 and the power terminal of the first operational amplifier unit A1 are connected to the same potential IS_8U.

[0080] The bias input terminal of the second operational amplifier unit A2 can input a bias current IB1_4U. The bias current IB2_4U can be a startup current of a startup circuit. The bias current IB2_4U and IB1_4U can be generated by the same bias circuit.

[0081] It is understandable that the above-mentioned startup circuit may also adopt other existing startup circuit structures and is not limited to the above-mentioned examples.

[0082] In the specific implementation, refer to Figure 4 , a circuit structure diagram of an operational amplifier unit in an embodiment of the present invention is given. The specific structures of the first operational amplifier unit A1 and the second operational amplifier unit A2 can refer to Figure 4 .

[0083] Figure 4 In the example, the operational amplifier unit includes MOS tubes M1 to M15. Among them, M1 to M4, M14 to M15 are PMOS tubes, and M5 to M13 are NMOS tubes. Among them:

[0084] The source of M1 is connected to the power supply voltage VDD, the gate of M1 is coupled to the gate of M2, and the drain of M1 is coupled to the source of M3;

[0085] The source of M2 is connected to the power supply voltage VDD, the gate of M2 is coupled to the gate of M1, the gate of M3 and the gate of M4, and the drain of M2 is coupled to the source of M4;

[0086] The source of M3 is coupled to the drain of M1, the gate of M3 is coupled to the drain of M3 and the gate of M4, and the drain of M3 is coupled to the drain of M5;

[0087] The drain of M4 is coupled to the drain of M6; the drain of M4 is connected to the output end of the operational amplifier unit;

[0088] The gate of M5 is coupled to the gate of M6, and the source of M5 is coupled to the drain of M7; the gates of M5 and M6 are both coupled to the first input terminal VIP of the operational amplifier unit;

[0089] The source of M6 is coupled to the drain of M8; the drain of M4 and the drain of M6 are the output terminal VO of the operational amplifier unit;

[0090] The gate of M7 is coupled to the first input terminal VIP of the operational amplifier unit, and the source of M7 is coupled to the drain of M9;

[0091] The source of M8 is coupled to the drain of M9, and the gate of M8 is coupled to the second input terminal VIN of the operational amplifier unit;

[0092] The source of M9 is grounded, and the gate of M9 is coupled to the drain of M13;

[0093] The gate of M13 is connected to the enable signal ENB, and the source of M13 is grounded;

[0094] The source of M15 inputs a bias current, the gate of M15 inputs an enable signal ENB, and the drain of M15 is coupled to the drain of M10;

[0095] The gate of M10 is coupled to the gate of M11 and is coupled to the first input terminal VIP of the operational amplifier unit; the source of M10 is coupled to the drain of M11;

[0096] The source of M11 is coupled to the drain of M12;

[0097] The source of M12 is grounded, and the gate of M12 is coupled to the drain of M15;

[0098] The gate of M14 is input with an enable signal EN, the source of M14 is input with a power supply voltage VDD, and the drain of M14 is coupled to the gate of M1 and the gate of M3.

[0099] In a specific implementation, the enable signal ENB may be a negated signal of the enable signal EN.

[0100] In a specific implementation, the circuit structure of the second operational amplifier unit may be the same as the circuit structure of the first operational amplifier unit. It is understandable that in a specific application, the first operational amplifier unit and the second operational amplifier unit may also adopt different circuit structures.

[0101] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A bandgap reference circuit, characterized in that: include: A cascode current mirror, a first cascode unit, a first operational amplifier unit and an output unit, wherein: The first cascode unit is coupled to the cascode current mirror and is suitable for mirroring the output current of the cascode current mirror; an output terminal of the first cascode unit is coupled to the bias input terminal of the first operational amplifier unit; The first operational amplifier unit has a first input terminal coupled to the second branch of the cascode current mirror, a second input terminal coupled to the first branch of the cascode current mirror, and an output terminal coupled to the control terminal of the cascode current mirror; The output unit has a control end coupled to the control end of the common-source common-gate current mirror, and an output end thereof outputs a reference voltage; The common-source common-gate current mirror includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first resistor, a second resistor, a third resistor, a first diode and a second diode, wherein: the first PMOS tube has a source electrode inputting a power supply voltage, a gate electrode thereof being coupled to a gate electrode of the second PMOS tube, and a drain electrode thereof being coupled to a source electrode of the third PMOS tube; the second PMOS tube has a source electrode inputting the power supply voltage, a gate electrode thereof being coupled to an output terminal of the first operational amplifier unit, and a drain electrode thereof being coupled to a source electrode of the fourth PMOS tube; the gate electrode of the third PMOS tube is coupled to a gate electrode of the fourth PMOS tube , whose drain is coupled to the second input terminal of the first operational amplifier unit; the fourth PMOS tube, whose drain is coupled to the first input terminal of the first operational amplifier unit; the first resistor, whose first end is coupled to the drain of the third PMOS tube, and whose second end is grounded; the first diode, whose anode is coupled to the drain of the third PMOS tube, and whose cathode is grounded; the second resistor, whose first end is coupled to the drain of the fourth PMOS tube, and whose second end is coupled to the first end of the third resistor and the anode of the second diode; the third resistor, whose second end is grounded; the second diode, whose anode is coupled to the first end of the third resistor, and whose cathode is grounded; The first common-source common-gate unit includes: a seventh PMOS tube and an eighth PMOS tube, wherein: the seventh PMOS tube has a source inputting a power supply voltage, a gate coupled to the output end of the first operational amplifier unit, and a drain coupled to the source of the eighth PMOS tube; the eighth PMOS tube has a gate coupled to the gate of the third PMOS tube and the gate of the fourth PMOS tube, and a source coupled to the output end of the first common-source common-gate unit.

2. The bandgap reference circuit according to claim 1, wherein: Also includes: A clamping unit is used to clamp the voltage on the second branch of the common-source and common-gate current mirror to the reference voltage.

3. The bandgap reference circuit according to claim 2, wherein: The clamping unit comprises a second operational amplifier unit, wherein: The second operational amplifier unit has a first input terminal coupled to the second branch of the common-source and common-gate current mirror, a second input terminal coupled to the output unit, and an output terminal coupled to the control terminal of the output unit.

4. The bandgap reference circuit according to claim 1, wherein: The output unit includes: a fifth PMOS tube and a sixth PMOS tube, and a fourth resistor, wherein: The fifth PMOS tube has a source electrode inputting a power supply voltage, a gate electrode coupled to the output terminal of the first operational amplifier unit, and a drain electrode coupled to the source electrode of the sixth PMOS tube; The sixth PMOS tube has a gate coupled to the gates of the third PMOS tube and the fourth PMOS tube, and a drain coupled to the first end of the fourth resistor and the output end of the output unit; the second end of the fourth resistor is grounded.

5. The bandgap reference circuit according to claim 4, characterized in that: The second operational amplifier unit has a first input terminal coupled to the drain of the second PMOS tube, a second input terminal coupled to the drain of the fifth PMOS tube, and an output terminal coupled to the gate of the sixth PMOS tube.

6. A bandgap reference source circuit, characterized in that: include: A start-up circuit, and a bandgap reference circuit as claimed in any one of claims 1 to 5, wherein: The startup circuit is coupled to the bandgap reference circuit and is suitable for outputting a startup current to the bandgap reference circuit.

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