Storage device, computing system and operating method thereof

Abstract

Embodiments of the present disclosure relate to a storage device, a computing system, and an operating method thereof. According to one embodiment of the present technology, a storage device can include a memory device including a secure storage area for storing data therein, the secure area accessing data according to authentication; an access mode memory configured to store therein information of a device access mode related to an operation mode of the secure storage area; and a memory controller configured to receive a command related to the secure storage area from an external host, and to process the command according to whether information of a host access mode contained in the command matches the information of the device access mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0150052, filed on November 3, 2021, and Korean Patent Application No. 10-2022-0064212, filed on May 25, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically to a storage device, a computing system, and a method of operating the same. Background Technology

[0004] With the recent significant development of information and communication technologies, semiconductor technologies, and other fields, the dissemination and use of various electronic devices are rapidly increasing. Specifically, recent electronic devices can be portable and can communicate, use applications to provide various services, and send and receive various data to and from external electronic devices or servers.

[0005] Electronic devices may include at least one processor and an operating system (OS) to provide a variety of services. The OS of electronic devices is strategically opened up by major manufacturers and major suppliers, and application programming interfaces, software development kits, and source files are open to the general public.

[0006] However, the use of such open operating systems is weakening the data security of electronic devices, and in fact, incidents such as the use of various malicious codes to damage or intrude into the data of electronic devices occur frequently. Therefore, various methods for protecting the data of electronic devices have recently been sought. Summary of the Invention

[0007] One embodiment of this disclosure provides a storage device, a computing system, and a method of operating the same with improved security features.

[0008] According to one embodiment of this disclosure, a storage device may include: a memory device including a secure storage region for storing data therein, the secure storage region being accessed based on authentication; an access mode memory configured to store device access mode information relating to the operating mode of the secure storage region; and a memory controller configured to receive commands relating to the secure storage region from an external host and process the commands based on whether the host access mode information included in the commands matches the device access mode information.

[0009] According to one embodiment of this disclosure, a method of operating a storage device includes a memory device, an access mode memory, and a memory controller. The memory device includes a secure storage region for storing data, the secure storage region being accessed based on authentication. The access mode memory is configured to store information therein regarding device access modes relating to the operation modes of the secure storage region of the storage device. The memory controller is configured to process commands received from an external host, which may include receiving commands from the external host relating to the secure storage region, identifying a host access mode based on the commands, the host access mode indicating the external host's operation mode for the secure storage region within the memory device, and comparing the host access mode with the device access mode.

[0010] According to one embodiment of this disclosure, a computing system may include a storage device, the storage device including a memory device including a secure storage region for storing data therein, the secure storage region being accessed based on authentication; an access mode memory configured to store device access mode information relating to the operating mode of the secure storage region; and a memory controller configured to control the memory device and the access mode memory; the storage device further includes a host device configured to provide commands relating to the secure storage region to the storage device, wherein the memory controller is further configured to process the commands based on whether the host access mode information included in the commands matches the device access mode information.

[0011] According to one embodiment of this disclosure, an operating method of an authenticator may include: accessing a storage area based on the first information in response to a request when the first information is the same as the second information; and rejecting the request when the first information is different from the second information, wherein the first information is provided together with the request, wherein the second information is pre-stored in the authenticator, and wherein each of the first information and the second information represents a scheme for authenticating the request.

[0012] Based on this technology, storage devices, computing systems, and methods of operation thereof with improved security features are provided. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0014] Figure 2 The illustration shows an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0015] Figure 3 It's a diagram. Figure 2 A diagram showing the configuration of one of the memory blocks.

[0016] Figure 4 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0017] Figure 5 This is a diagram illustrating a data communication unit between a host access controller and a device access controller according to an embodiment of the present disclosure.

[0018] Figure 6 This is a diagram illustrating the structure of the basic header segment of a Protocol Information Unit (PIU) according to an embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating the configuration of a command PIU according to an embodiment of the present disclosure.

[0020] Figure 8 This is a diagram illustrating the configuration of a response PIU according to an embodiment of the present disclosure.

[0021] Figure 9 This is a diagram illustrating a Replay Protection Memory Block (RPMB) message according to an embodiment of the present disclosure.

[0022] Figure 10 This is a diagram illustrating an RPMB cell descriptor stored in a storage device according to an embodiment of the present disclosure.

[0023] Figure 11 This is a diagram illustrating a device descriptor stored in a storage device according to an embodiment of the present disclosure.

[0024] Figure 12 This is a diagram illustrating the result code included in an RPMB message according to an embodiment of the present disclosure.

[0025] Figure 13 This is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0026] Figure 14 This is a flowchart illustrating an authenticated data write operation performed in normal RPMB mode according to an embodiment of the present disclosure.

[0027] Figure 15 The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1405.

[0028] Figure 16 The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1413.

[0029] Figure 17The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1419.

[0030] Figure 18 This is a flowchart illustrating an authenticated data read operation performed in normal RPMB mode according to an embodiment of the present disclosure.

[0031] Figure 19 The illustration shows an embodiment of the present disclosure. Figure 18 The diagram shows the operation of the RPMB message provided by S1805.

[0032] Figure 20 The illustration shows an embodiment of the present disclosure. Figure 18 The diagram shows the operation of the RPMB message provided by S1811.

[0033] Figure 21 This is a flowchart illustrating an authenticated data write operation performed in advanced RPMB mode according to an embodiment of the present disclosure.

[0034] Figure 22 The illustration shows an embodiment of the present disclosure. Figure 21 A diagram showing the structure of the command PIU transmitted in operation S2101.

[0035] Figure 23 The illustration shows an embodiment of the present disclosure. Figure 21 A diagram showing the structure of the response PIU transmitted in operation S2107.

[0036] Figure 24 This is a flowchart illustrating an authenticated data read operation performed in advanced RPMB mode according to an embodiment of the present disclosure.

[0037] Figure 25 The illustration shows an embodiment of the present disclosure. Figure 24 A diagram showing the structure of the command PIU transmitted in operation S2401.

[0038] Figure 26 The illustration shows an embodiment of the present disclosure. Figure 24 A diagram showing the structure of the response PIU transmitted in operation S2405.

[0039] Figure 27 This is a diagram illustrating a PIU transmitter 2700 included in an initiator device according to an embodiment of the present disclosure.

[0040] Figure 28 This is a diagram illustrating a PIU receiver 2800 included in a target device according to an embodiment of the present disclosure.

[0041] Figure 29 The illustration shows another embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0042] Figure 30 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0043] Figure 31 This is a block diagram illustrating a solid-state drive (SSD) system that applies a storage device according to an embodiment of the present disclosure.

[0044] Figure 32 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0045] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are illustrated for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0046] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0047] refer to Figure 1 The computing system may include storage device 50 and host 400. Storage device 50 may include memory device 100, memory controller 200, and access mode memory 300. Storage device 50 may be a device that stores data under the control of host 400, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. Alternatively, storage device 50 may be a device that stores data under the control of host 400 (such as a server or data center) that stores large amounts of data in one place.

[0048] Storage device 50 can be manufactured as one of various types of storage devices depending on the host interface used as a communication method with host 400. For example, storage device 50 can be configured as any of various types of storage devices, such as SSDs; multimedia cards in the form of MMC, eMMC, RS-MMC, and micro-MMC; secure digital cards in the form of SD, mini-SD, and micro-SD; Universal Serial Bus (USB) storage devices; Universal Flash Storage (UFS) devices; PCMCIA card-type storage devices; Peripheral Component Interconnect (PCI) card-type storage devices; PCI-Rapid (PCI-e or PCIe) card-type storage devices; Compact Flash (CF) cards; smart media cards, and Memory Sticks.

[0049] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0050] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0051] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0052] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple pages. In one embodiment, a page may be a unit for storing or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0053] The memory blocks included in the memory device 100 may include an access-restricted secure storage area 110a and a general storage area 110b. The secure storage area 110a may be an area used to store data accessible based on authentication. Additional conditions or processes may be required to access the secure storage area 110a. For example, the secure storage area 110a may only be accessible when the storage device 50 receives a predetermined specific command or through authentication performed by the memory controller 200. In one embodiment, the secure storage area 110a may be a playback-protected memory block (RPM). The general storage area 110b may be a memory block that can be accessed without separate authentication. The general storage area 110b may be a memory block that stores data other than the data stored in the secure storage area 110a.

[0054] In this specification, for ease of explanation, the secure storage area 110a may be described as an RPMB; however, the embodiments disclosed herein are not limited to the secure storage area 110a being an embodiment of an RPMB, and can be applied to all types of memory blocks whose access methods differ from those of the ordinary storage area 110b.

[0055] In the method of accessing secure storage area 110a, there may be two or more modes with different access speeds. For example, there may be a first access mode with relatively strict security for secure storage area 110a and a second access mode with relatively fast access speed for secure storage area 110a. In the case of the second access mode, the access speed to secure storage area 110a can be improved by performing relatively fewer authentication processes compared to the first access mode.

[0056] For example, when storage device 50 supports RPMB, RPMB can be accessed according to at least two or more modes. For example, RPMB can be accessed in either normal RPMB mode or advanced RPMB mode.

[0057] In this specification, the normal RPMB mode may be referred to as an example of the first access mode, which has a relatively slow access speed to the secure storage area 110a, and the advanced RPMB mode may be referred to as an example of the second access mode, which has a relatively fast access speed to the secure storage area 110a.

[0058] In one embodiment, memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of explanation, memory device 100 is referred to as NAND flash memory.

[0059] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access a region in the memory cell array selected by the address. Memory device 100 can perform operations instructed by commands on the region selected by the address. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data in the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data stored in the region selected by the address.

[0060] The memory controller 200 can control the overall operation of the storage device 50.

[0061] When power is applied to storage device 50, memory controller 200 can execute firmware such as flash translation layer (FTL) for controlling communication between host 400 and storage device 100.

[0062] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from the host 400 and may translate the LBAs into physical block addresses (PBAs) that indicate the addresses of memory cells in the memory device 100 where the data will be stored.

[0063] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations according to a request from the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and PBA.

[0064] In one embodiment, independent of requests from host 400, memory controller 200 can independently generate commands, addresses, and data, and send them to memory device 100. For example, memory controller 200 can provide memory device 100 with commands, addresses, and data for performing programming operations, read operations, and erase operations accompanied by wear leveling, read recycling, garbage collection, etc.

[0065] In one embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can be a method of controlling the operation of at least two memory devices 100 so that they overlap with each other.

[0066] The access mode memory 300 may store various fragments of information provided by commands transmitted between the host 400 and the storage device 50. For example, it may include information about device access modes related to the operating mode of the secure storage area 110a of the storage device 50. For instance, the device access mode information may indicate the method by which the storage device 50 accesses the secure storage area 110a. Specifically, the device access mode information may indicate information related to one or more access modes supported by the storage device 50, or information related to the currently active access mode in the storage device 50. In one embodiment, such information may be stored in the form of descriptors. Figure 1 In this diagram, access-mode memory 300 is shown in a configuration separate from memory device 100 and memory controller 200; however, access-mode memory 300 is not limited to this and may be a portion of the storage area within memory device 100 or memory controller 200. In one embodiment, access-mode memory 300 may be a register. See later. Figure 10 and Figure 11 To describe it in more detail.

[0067] The memory controller 200 can identify a device access mode based on device access mode information stored in the access mode memory 300. Additionally, the memory controller 200 can identify a host access mode for the secure storage region 110a provided by the host 400 based on an access request (i.e., command) for the secure storage region 110a, and can compare the device access mode with the host access mode. The host access mode can be identified based on host access mode information in a command provided by the host, and the host access mode information may include information related to the operating mode of the secure storage region provided by the host.

[0068] When the device access mode and the host access mode match, the memory controller 200 can access the secure storage area 110a according to a request from the host 400. When the device access mode and the host access mode do not match, the memory controller 200 may cause the host 400's request to fail. When the host 400's request fails, access to the secure storage area 110a may no longer be performed, or information indicating that the host 400's request failed (i.e., an error message) may be provided to the host.

[0069] The device access mode and the host access mode can be either a first access mode with a relatively slow access speed or a second access mode with a relatively fast access speed, respectively. When the device access mode is the first access mode, the memory controller 200 can obtain the information required for authentication from a command received after a command related to the secure storage area 110a. When the device access mode is the second access mode, the memory controller 200 can obtain the information required for authentication from a command related to the secure storage area 110a. In this case, the information required for authentication can refer to one or more of the various types of information required to perform authentication. For example, all information indicating the command related to accessing the secure storage area 110a, the authentication code used to perform authentication, and all types of information used to generate the authentication code can be the information required for authentication.

[0070] In one embodiment, when the secure storage area 110a is an RPMB, the first access mode and the second access mode can be a normal RPMB mode and an advanced RPMB mode, respectively. In the normal RPMB mode, the host RPMB message can be included in a data output command provided from the host 400 and can be provided to the storage device 50. The data output command can be provided after the host 400 provides a command requesting access to the RPMB. In the advanced RPMB mode, the host RPMB message can be included in a command requesting access to the RPMB provided by the host and can be provided to the storage device 50. See later. Figures 14 to 26 To describe it in more detail.

[0071] The host 400 can communicate with the storage device 50 using at least one of various communication standards or interfaces, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Faster (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0072] In this specification, for ease of explanation, storage device 50 and host 400 communicate data via a UFS communication interface; however, embodiments of this disclosure are not limited to performing data communication via a UFS communication interface. Specifically, storage device 50 and host 400 may perform data communication using commands defined as Protocol Information Units (PIUs). A PIU may be a data packet type generated according to a predetermined protocol. Therefore, in this specification, a PIU is simply a form of command transmitted between storage device 50 and host 400, and thus commands and PIUs can have the same meaning.

[0073] Commands can be requested, instructed, or responded to from host 400 or storage device 50 to perform any operation. In one embodiment, various commands can be defined according to their purpose and intended use. For example, all of the following in preparation for transmission can be referred to as commands, and in one embodiment, commands can be sent in the form of the aforementioned PIU.

[0074] The smallest unit of a PIU can be 32 bytes in size, and the maximum size of a PIU can be 65,600 bytes. The format of a PIU can vary in size depending on its type.

[0075] The host 400 may provide commands to the storage device 50 relating to the secure storage area 110a, and the commands may be, for example, a command requesting access to the secure storage area 110a. Commands relating to the secure storage area 110a may include common segments typically included in commands transmitted between an external host and a memory controller, unique fields including unique values ​​depending on the command type, and additional segments that are segments other than the common segments. Here, the common segments may include information indicating the length of the additional segments.

[0076] The memory controller 200 can identify a host access mode based on one or more of a common segment and additional segments of a command. Specifically, the host access mode can be identified based on at least one of the length of the additional segments included in the common segment and whether the additional segments include information required for authentication. For example, when the length of the additional segments is 0 or the information required for authentication is not included in the additional segments, the memory controller 200 can identify the host access mode as a first access mode. Alternatively, when the length of the additional segments is not 0 or the information required for authentication is included in the additional segments, the memory controller 200 can identify the host access mode as a second access mode.

[0077] When a command is provided in the form of a PIU, a command relating to secure storage region 110a, more specifically, a command requesting access to secure storage region 110a, can be provided in the form of a command PIU. In this case, a common field may refer to a basic header field, a unique field may refer to a transaction-specific field, and an extra field may refer to an extra header field. Additionally, the basic header field may include a total extra header field length field, which includes the length information of the extra header fields. This will refer to... Figures 5 to 8 To describe in more detail.

[0078] The memory controller 200 may include a device access controller 210.

[0079] Device access controller 210 can handle access requests from host 400 to secure storage area 110a.

[0080] For example, when secure storage area 110a is an RPMB, device access controller 210 can handle authenticated data write operations that store data in the RPMB and authenticated data read operations that read data stored in the RPMB. See later. Figure 27 and Figure 28 The specific methods by which the device access controller 210 processes authenticated data write operations and authenticated data read operations are described in more detail.

[0081] Host 400 may also include host access controller 410.

[0082] The host access controller 410 can generate commands for controlling the secure storage area 110a and provide these commands to the device access controller 210. The host access controller 410 can receive commands from the device access controller 210.

[0083] Refer to later Figure 4 , Figure 27 and Figure 28 The device access controller 210 and the host access controller 410 are described in more detail.

[0084] Figure 2 The illustration shows an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0085] refer to Figure 2 The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0086] The memory cell array 110 includes multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi are connected to the address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi are connected to the input / output circuitry 140 via column lines CL. In one embodiment, the row line RL may include word lines, source select lines, and drain select lines. In one embodiment, the column line CL may include bit lines.

[0087] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In one embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each memory cell of the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0088] A portion of multiple memory blocks BLK1 to BLKi may be referenced Figure 1 The described secure storage area 110a may be a general storage area 110b. In one embodiment, secure storage area 110a may be an RPMB.

[0089] In one embodiment, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. The peripheral circuitry can drive the memory cell array 110 under the control of control logic 150. The peripheral circuitry can drive the memory cell array 110 to perform programming, reading, and erasing operations.

[0090] Voltage generator 120 is configured to generate multiple operating voltages using the external power supply voltage supplied to memory device 100. Voltage generator 120 operates in response to control of control logic 150.

[0091] In one embodiment, voltage generator 120 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 120 is used as the operating voltage of memory device 100.

[0092] In one embodiment, voltage generator 120 can generate multiple operating voltages by using an external power supply voltage or an internal power supply voltage. Voltage generator 120 can be configured to generate various voltages required in memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selected read voltages, and multiple unselected read voltages.

[0093] The voltage generator 120 may include a plurality of pump capacitors that receive an internal power supply voltage to generate a plurality of operating voltages having various voltage levels, and the plurality of operating voltages may be generated by selectively activating the plurality of pump capacitors in response to the control of the control logic 150.

[0094] The generated operating voltages can be supplied to the memory cell array 110 by the address decoder 130.

[0095] Address decoder 130 is connected to memory cell array 110 via row line RL. Address decoder 130 is configured to operate in response to control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 can select at least one memory block from memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In one embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 can connect input / output circuitry 140 and memory cell array 110 to each other based on the decoded column address.

[0096] For example, address decoder 130 may include components such as row decoder, column decoder, and address buffer.

[0097] Input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to the memory cell array 110 via bit lines. During programming operations, data (DATA) can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0098] During a read operation, the data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0099] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuitry 140. Control logic 150 can operate in response to commands (CMD) sent from external devices. Control logic 150 can generate control signals to control peripheral circuitry in response to commands (CMD) and addresses (ADDR).

[0100] Figure 3 The illustration shows an embodiment according to the present disclosure. Figure 2 A diagram showing the configuration of one of the memory blocks.

[0101] Memory block BLKi is Figure 2 The memory blocks BLK1 through BLKi can be selected. A normal storage area or a secure storage area can be selected from memory blocks BLK1 through BLKi upon request from the host.

[0102] refer to Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line SSL, and the second select line can be a drain select line DSL. More specifically, memory block 110 can include multiple strings ST connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to strings ST individually, and the source line SL can be connected together to strings ST. Since strings ST can be configured to be identical to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

[0103] A string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST connected in series between the source line SL and the first bit line BL1. A string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include more memory cells than the number shown in the figure.

[0104] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different string STs can be connected to the source select line SSL, the gates of the drain select transistor DSTs can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. Among the memory cells included in different string STs, the group of memory cells connected to the same word line can be referred to as a page PG. Therefore, a memory block BLKi can include the number of page PGs corresponding to word lines WL1 to WL16.

[0105] A memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0106] A memory cell can store two or more data bits. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0107] Figure 4 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0108] In the following, in one embodiment of this disclosure, in Figures 4 to 12 and Figures 14 to 26 In this disclosure, it may be disclosed that the secure storage area 110a is an RPMB, but the embodiments of this disclosure are not limited thereto, and the secure storage area can be various types of memory blocks with restricted access.

[0109] Additionally, in one embodiment of this disclosure, in Figures 4 to 12 and Figures 14 to 26 In this process, commands transmitted between storage device 50 and host 400 are sent in the form of PIUs. However, the embodiments of this disclosure are not limited to this, and various communication methods may be used.

[0110] refer to Figure 1 and Figure 4 Storage device 50 may include a secure storage area 110a and a device access controller 210. The secure storage area 110a may be located in reference... Figure 1The described memory device 100 includes at least a portion of the storage regions, and in one embodiment, the secure storage region 110a may be an RPMB. Device access controller 210 may be included in memory controller 200, and host access controller 410 may be included in host 400.

[0111] The secure storage area 110a may include an authentication key 111, a write counter 112, a result register 113, and a data area 114.

[0112] The authentication key 111 may be a value pre-stored in secure storage area 110a for use in accessing secure storage area 110a during authentication. For example, when secure storage area 110a is an RPMB, the authentication key 111 may be stored only once, may not be read by itself, and may only be accessible when calculating the Message Authentication Code (MAC) used to authenticate access to the RPMB. In one embodiment, the authentication key 111 may have a size of 32 bytes, but the size of the authentication key is not limited to 32 bytes.

[0113] Write counter 112 can count the number of times secure storage area 110a is accessed. Access to secure storage area 110a can be allowed only within a preset number of times, and thus security can be improved. In one embodiment, when secure storage area 110a is an RPMB, write counter 112 can count the number of times an authenticated data write operation is successfully performed, which is the operation of storing data in the RPMB. The value indicated by write counter 112 or the value stored in write counter 112 can be a write count value. Write counter 112 can store a write count value corresponding to 4 bytes, but it can also store a write count value corresponding to larger data sizes. The initial write count value can be "0000 0000h". The write count value of write counter 112 may not be reset or decremented. The write count value of write counter 112 may stop increasing after reaching the maximum value "FFFF FFFFh". Therefore, when the write count value of write counter 112 reaches its maximum value, the data may no longer be stored in the secure storage area 110a, and the secure storage area 110a can be operated as a read-only storage area.

[0114] Result register 113 can store the result of an operation performed on secure storage area 110a. For example, when secure storage area 110a is an RPMB, result register 113 can store a result code indicating the result of an operation performed on the RPMB. The type of the result code stored in the result register will be determined by... Figure 12 Let me describe it in more detail.

[0115] In one embodiment, the authentication key 111, write counter 112, and result register 113 may be included independently for each different region in the secure storage region 110a and may have unique values. In various embodiments, the secure storage region 110a may be divided into multiple secure storage sub-regions. In one embodiment, when the secure storage region 110a is an RPMB, the maximum number of RPMB sub-regions included in the RPMB may be four. Each RPMB sub-region may have a unique authentication key and write counter value.

[0116] The data area can be an area where data is stored only when authentication is successful. In one embodiment, when the secure storage area 110a is an RPMB, the capacity of the data area (RPMB data area) can be a minimum of 128 kilobytes and a maximum of 16 megabytes.

[0117] The device access controller 210 may also include an authentication manager 211, an access execution unit 212, and an access pattern recognition unit 213.

[0118] Access pattern recognition unit 213 can verify whether the host access pattern and device access pattern match before accessing secure storage area 110a. That is, access operations (such as authentication) to secure storage area 110a can only be performed if the method of accessing secure storage area 110a provided by storage device 50 matches the method of accessing secure storage area 110a provided by host 400. Access pattern recognition unit 213 can identify device access patterns based on information stored in access pattern memory 300, and can identify host access patterns based on command PIU from host 400. Various descriptors provided from host 400 can exist in access pattern memory 300, and may include, for example, device descriptor 310 and cell descriptor 320. Device descriptor 310 may include information related to whether storage device 50 supports a second access pattern, and cell descriptor 320 may include information related to whether the second access pattern is activated. Authentication manager 211 can identify device access patterns based on one or more of such information. For example, when the information included in the device descriptor indicates that the storage device 50 does not support the second access mode, the authentication manager 211 can identify the device access mode as the first access mode. Alternatively, when the information included in the device descriptor indicates that the storage device 50 supports the second access mode, the device access mode can be identified based on whether the second access mode included in the cell descriptor 320 is activated. In one embodiment, when the secure storage area 110a is an RPMB, the cell descriptor 320 can be an RPMB cell descriptor, and the second access mode can be an advanced RPMB access mode.

[0119] When a write operation is performed on secure storage area 110a, host access controller 410 may provide device access controller 210 with a message regarding access to secure storage area 110a, according to a predetermined format. Such a message may include information indicating a write request to secure storage area 110a, metadata required for authentication, authentication data required for authentication, etc. For example, when secure storage area 110a is an RPMB, when an authenticated data write operation is performed, host access controller 410 may provide RPMB messages to device access controller 210 according to a predetermined format. The RPMB message provided by host access controller 410 may include information required for RPMB authentication. For example, the RPMB message may include metadata required for authentication and authentication data required for authentication. Authentication data may include a MAC generated by host access controller 410.

[0120] When the host access mode and device access mode match, the authentication manager 211 can perform authentication using the authentication key 111 stored in the secure storage area 110a. The authentication manager 211 can provide the authentication result to the access execution unit 212. The access execution unit 212 can, based on the authentication result, store data in the secure storage area 110a or prevent data from being stored in the secure storage area 110a.

[0121] When authentication is successful, the access execution unit 212 can control the secure storage area 110a, so that the data to be stored in the secure storage area 110a received from the host 400 is stored in the data area 114. When the data is successfully stored, the access execution unit 212 can increment the write count value stored in the write counter 112 and store the result of the write operation in the result register 113.

[0122] When authentication fails, access execution unit 212 may store the request data in data area 114 instead of in secure storage area 110a. Access execution unit 212 may maintain the value of write counter 112 and store the information indicating authentication failure in result register 113.

[0123] When the host access mode and device access mode do not match, the authentication manager 211 can control the storage of error indication information to prevent authentication from being performed. In one embodiment, the error indication information can be stored in the result register 113 in the same manner as in the case of authentication failure, and then provided to the host access controller 410 as a response PIU to the command PIU. Alternatively, the error indication information can be stored in another location and then provided to the host access controller 410, or it can be provided directly to the host access controller 410 without being stored separately.

[0124] When the host access mode and device access mode match, and a data read operation is performed on secure storage area 110a, the host access controller 410 may provide the device access controller 210 with a message related to accessing secure storage area 110a, according to a predetermined format. This message may include information indicating a read request for secure storage area 110a, metadata required for authentication, etc.

[0125] Access execution unit 212 can read data stored in secure storage area 110a and generate a response message to be provided to host access controller 410. Access execution unit 212 can generate metadata to be included in the response message. The metadata may be information required for authentication by host access controller 410 and may include, for example, a portion of information included in a message received from host access controller 410, data read from secure storage area 110a, a result code indicating the result of performing the read operation, etc. Additionally, the response message may also include authentication data required for authentication. In one embodiment, when secure storage area 110a is an RPMB, access execution unit 212 can use the authentication key 111 and metadata stored in the RPMB to generate a MAC as authentication data.

[0126] Access execution unit 212 can generate a response message that includes authentication data and metadata. Access execution unit 212 can then provide the read data and response message to host access controller 410.

[0127] At this time, when the host access mode and device access mode do not match, the authentication manager 211 can control the access execution unit 212 not to perform the authenticated data read operation itself. Alternatively, the authentication manager 211 can control the access execution unit 212 not to generate a response message or not to provide the generated response message to the host access controller 410.

[0128] Figure 5 This is a diagram illustrating a data communication unit between a host access controller and a device access controller according to an embodiment of the present disclosure.

[0129] refer to Figure 1 and Figure 5Host access controller 410 and device access controller 210 can communicate using data packets called Protocol Information Units (PIUs). In terms of physical devices, host access controller 410 is included in host 400, while device access controller 210 is included in storage device 50. Regarding the interfacing between the two devices, one device can send a PIU to the other. In this case, the device generating the PIU can be referred to as the initiating device, and the device receiving the generated PIU can be referred to as the target device. That is, a PIU can be a data packet sent between the two devices, rather than a data packet unilaterally sent by one device (host 400 or storage device 50) to the other.

[0130] The PIU can include a query request PIU, a command PIU, a response PIU, a data output PIU, a data input PIU, and a prepare to transmit PIU, depending on the operation to be performed by the host access controller 410 or the device access controller 210.

[0131] The Query Request Unit (PIU) can provide a device descriptor to storage device 50, which provides various parameters of storage device 50. The device descriptor may include information indicating whether storage device 50 supports advanced RPMB mode.

[0132] Additionally, in one embodiment, the query request PIU may include a cell descriptor. The cell descriptor may include information indicating whether a second access mode is activated. In one embodiment, the cell descriptor may be an RPMB cell descriptor, and in this case, the RPMB cell descriptor may include information indicating whether an advanced RPMB mode of the storage device 50 is activated. In this case, the RPMB cell descriptor may include an 8-bit RPMB region enable field (bRPMBRegionEnable) for setting the RPMB region included in the RPMB. In one embodiment, the RPMB region enable field (bRPMBRegionEnable) may be used to determine whether the storage device 50 currently supports accessing the RPMB in either normal RPMB mode or advanced RPMB mode.

[0133] A command PIU can be a PIU sent when the host 400 transmits a command to the storage device 50.

[0134] A response PIU can be a PIU transmitted when the storage device 50 provides a response to a command provided by the host 400.

[0135] A data output PIU can be a PIU sent when the host 400 provides data to the storage device 50.

[0136] A data input PIU can be a PIU sent when storage device 50 provides data to host 400.

[0137] A prepare to transmit PIU can be a PIU sent when storage device 50 notifies storage device 50 that it is ready to receive a data output PIU from host 400. A prepare to transmit PIU can also be sent when storage device 50 has sufficient buffer space to store the data provided by host 400.

[0138] The smallest PIU can be 32 bytes in size, and the largest PIU can be 65,600 bytes. The format of a PIU can vary in size depending on its type.

[0139] In one embodiment, the PIU may include a basic header segment 61, a transaction-specific field 62, an additional header segment 63, and a data segment 64.

[0140] The basic header segment 61 can be 12 bytes in size. The basic header segment 61 can be included in all PIUs. The basic header segment 61 can include basic configuration information related to the PIU.

[0141] Transaction-specific field 62 may be included in byte addresses 12 to 31 from the PIU. Transaction-specific field 62 may include a dedicated transaction code depending on the type of the PIU.

[0142] Additional header segment 63 may be limited when the total additional header segment length field of the basic header segment 61 has a non-zero value. Additional header segment 63 may begin at byte address 32 of the PIU. Additional header segment 63 may be a region capable of storing additional data when the basic header segment 61 may not contain sufficient information.

[0143] Data segment 64 may be included in a data output PIU or a data input PIU, but may not be included in other PIUs.

[0144] In one embodiment, additional header segment 63 and data segment 64 may not be included in all PIUs, but may be included only in specific PIUs.

[0145] Figure 6 This is a diagram illustrating the structure of the basic header segment of a PIU according to an embodiment of the present disclosure.

[0146] refer to Figure 6 The basic header segment 61 may include transaction type, flags, logical unit number (LUN), task label, initiator ID, command set type, query function / task management function, response, status, total extra header segment length, device information, and data segment length.

[0147] Depending on the PIU type, the transaction type can have a unique value. Examples of transaction types based on the PIU type are shown in Table 1 below.

[0148] Table 1

[0149]

[0150] Flags can be fields with different values ​​based on the transaction type. A logical unit number can be a field indicating the number of logical units among multiple logical units included in the object to be operated on. For example, refer to... Figure 1 Each of the described host 400 and storage device 50 may include multiple logical units, and the logical unit number of the basic header segment 61 included in the PIU may indicate a specific logical unit among the multiple logical units.

[0151] Task labels can be fields that have different values ​​depending on the transaction type.

[0152] The initiator ID can be a field that identifies who initiated the requested operation. Therefore, the initiator ID may have different values ​​if the PIU is generated by the host and the PIU is generated by the storage device.

[0153] The command set type can be a field included in the command PIU and the response PIU. The command set type can also be a field indicating which interface supports the command, such as whether the command is a SCSI command, a UFS command, or a manufacturer-defined command.

[0154] The query / task management function can be fields entered into the PIU, such as query requests, query responses, or task management requests.

[0155] The response can be a field indicating whether the requested operation was executed successfully or failed.

[0156] The status can be a field indicating the SCSI status.

[0157] The total extra header segment length can be a field indicating the size of the extra header segment in 32-bit units. The total extra header segment length can be used when the PIU includes an extra header segment. The length of the extra header segment can be in 4-byte units. The maximum size of the extra header segment can be 1024 bytes. When no extra header segment is used, the total extra header segment length may be 0.

[0158] Device information may include information that is only used when performing a specific function.

[0159] The data segment length can be a field that indicates the length of the data segment in the PIU. When the PIU does not include a data segment, the data segment length may be 0.

[0160] Figure 7 This is a diagram illustrating the configuration of a command PIU according to an embodiment of the present disclosure.

[0161] Figure 8 This is a diagram illustrating the configuration of a response PIU according to an embodiment of the present disclosure.

[0162] refer to Figure 1 , Figure 7 and Figure 8 Command and response PIUs can include a basic header field, transaction-specific fields, additional header fields, and a data field. The basic header field included in the command and response PIUs can include a total additional header field. Additional header field fields included in the command and response PIUs can be used when the total additional header field has a non-zero value. Additional header fields can begin at byte address 32 of the PIU. Additional header fields can be areas capable of storing additional data when the basic header field may not contain sufficient information.

[0163] In advanced RPMB mode, host 400 and storage device 50 can send RPMB messages using additional header segments included in the command PIU and response PIU. Specifically, host 400 and storage device 50 can set the total additional header segment length field included in the basic header segment of the command PIU and response PIU to a non-zero value, and can send RPMB messages by including RPMB messages in the additional header segments.

[0164] The memory controller 200 can identify the host access mode by checking the total extra header length field or the extra header field in the basic header field of the command PIU received from the host 400. For example, the memory controller 200 can first check the total extra header length field of the command PIU. When the value of the total extra header length field is 0, the host access mode can be identified as normal RPMB mode. When the value of the total extra header length field is not 0, the extra header field can be checked, and if an RPMB message is present in the extra header field, the host access mode can be identified as advanced RPMB mode. Alternatively, depending on the situation, when the value of the total extra header length field is not 0, the host access mode can be identified as advanced RPMB mode without checking the extra header field. Alternatively, the host access mode can be identified by directly checking the extra header field based on the presence or absence of an RPMB message without checking the total extra header length field.

[0165] Figure 9 This is a diagram illustrating an RPMB message according to an embodiment of the present disclosure.

[0166] refer to Figure 1 and Figure 9When host 400 or storage device 50 sends and receives PIUs related to RPMB, host 400 or storage device 50 can transmit RPMB messages to each other. RPMB messages may include information for authentication.

[0167] An RPMB message may include multiple components. Depending on how the RPMB message is transmitted, it may include... Figure 9 Some or all of the components shown.

[0168] Request message types can be 2 bytes in size. A request message type can be a component indicating the type of request to the RPMB. Request message types can be included in requests sent from the initiating device to the target device. Examples of possible code values ​​for request message types are shown in the following [Table 2].

[0169] [Table 2]

[0170]

[0171]

[0172] An authentication key programming request can be a message type that requests programming of an authentication key. A write counter read request can be a message type that requests a write counter value stored in a write counter. An authenticated data write request can be a message type that requests data to be stored in the RPMB. An authenticated data read request can be a message type that requests data stored in the read RPMB. A result read request can be a message type that requests the execution result (the value stored in the result register) of an operation related to the RPMB. An RPMB message with these request message types can be an example of a message requesting access to secure storage area 110a. A response message type can be 2 bytes in size. A response message type can be a component indicating the response type. A response message type may not be included in a request sent by the initiating device to the target device, but may be included in a response sent by the target device to the initiating device. The possible code values ​​for response message types are shown in the following [Table 3].

[0173] Table 3

[0174]

[0175]

[0176] An authentication key programming response can be a response message type indicating a response to an RPMB message requesting the programming of an authentication key. A write counter read response can be a response message type indicating a response message to an RPMB message requesting the sending of the write counter value stored in the write counter to the initiating device. An authenticated data write response can be a response message type indicating a response to an authentication data write request requesting the writing of authenticated data stored in the RPMB. An authenticated data read response can be a response message type indicating a response to an authentication data read request requesting the reading of data stored in the RPMB. A result read response can be a response message type indicating a response to a result read request requesting the reading of the result (the value stored in the result register) of an operation related to the RPMB. The authentication key can be 32 bytes in size. The authentication key can be an RPMB message component included in the PIU corresponding to the authentication key programming request when the RPMB is initially requested to be programmed. Therefore, the authentication key can be included only in the request sent by the initiating device to the target device.

[0177] A MAC can be 32 bytes in size. A MAC can be included in a response sent from the target device to the initiating device, as well as in a request sent from the initiating device to the target device. A MAC can be a component of an RPMB message used for authentication.

[0178] The result can be 2 bytes in size. The result can be a value stored in a result register included in the RPMB. Therefore, the result can be included in the response sent by the target device to the initiating device.

[0179] The write counter can be 4 bytes in size. The write counter indicates the total number of successfully executed, authenticated data write operations. The write counter can be a write count value stored in the write counters included in the RPMB. The write counter can be included in responses sent by the target device to the initiating device, and in requests sent by the initiating device to the target device.

[0180] An address can be 2 bytes in size. An address can be data to be stored in the RPMB, or it can be the logical address of data already stored in the RPMB. Addresses can be included in responses sent from the target device to the initiating device, and in requests sent from the initiating device to the target device.

[0181] The random number can be 16 bytes in size. The random number can be a value with randomness. The random number can be included in a response sent by the target device to the initiating device, and in a request sent by the initiating device to the target device. In one embodiment, the random number can be generated by host 400, and storage device 50 can copy and use the random number generated by host 400.

[0182] The data can be data to be stored in the RPMB or data read from the RPMB. The data can be 256 bytes in size. In one embodiment, the data can be data transferred between the initiator device and the target device when accessing the RPMB in normal RPMB mode.

[0183] Advanced RPMB data can be data to be stored in the RPMB or data read from the RPMB in advanced RPMB mode. Advanced RPMB data can be sent in 4KB units. Advanced RPMB data can be data to be stored in the RPMB based on a certified data write request, or data read from the RPMB by storage device 50 based on a certified data read request.

[0184] The block count can be 2 bytes in size. The block count can be a value indicating the number of data blocks transferred between the initiating and destination devices in normal RPMB mode. In normal RPMB mode, a block can be 256 bytes in size.

[0185] Advanced RPMB block count can be a value indicating the number of Advanced RPMB data blocks sent between the initiating and target devices in Advanced RPMB mode. In Advanced RPMB mode, a block can be 4KB in size.

[0186] In the aforementioned message component, information directly used for authentication (such as MAC addresses) can be referred to as authentication data. Additionally, in the aforementioned message component, information other than authentication data such as MAC addresses can be referred to as metadata. Since such metadata can also be used to generate authentication data in the target device (e.g., the MAC address of the target device), metadata can also be information indirectly used for authentication. Therefore, both authentication data and metadata can be information required for authentication.

[0187] Messages related to accessing secure storage area 110a, such as references Figure 9 The described RPMB message may include some or all of the authentication data and metadata. For example, when accessing an RPMB block in normal RPMB mode or advanced RPMB mode, refer to... Figure 9 The described RPMB message component may be included in an RPMB message transmitted between host 400 and storage device 50, or in an RPMB message transmitted between an initiator device and a target device. The RPMB message component may be included in a single PIU, or it may be divided and included in multiple PIUs depending on the type of operation.

[0188] Figure 10This is a diagram illustrating an RPMB cell descriptor stored in a storage device according to an embodiment of the present disclosure. Here, the RPMB cell descriptor is merely described as an example of a cell descriptor, which includes information related to whether a second access mode is activated, and can be stored... Figure 3 The cell descriptors in the access mode memory 300 are not limited to RPMB cell descriptors.

[0189] refer to Figure 4 and Figure 10 An RPMB unit descriptor can be provided from host 400 to storage device 50. The RPMB regions included in the RPMB can be defined according to the RPMB descriptor. The RPMB unit descriptor may include an 8-bit RPMB region enable field (bRPMBRegionEnable) for setting the RPMB regions included in the RPMB. In one embodiment, the RPMB region enable field (bRPMBRegionEnable) can be used to determine whether storage device 50 supports accessing the RPMB in normal RPMB mode or advanced RPMB mode. In the RPMB region enable field, RPMB region 0 is always active regardless of the value of BIT-0; RPMB region 1 is active when the value of BIT-1 is 1; RPMB region 2 is active when the value of BIT-2 is 1; and RPMB region 3 is active when the value of BIT-3 is 1. Additionally, advanced RPMB mode is activated when the value of BIT-4 is 1, and normal RPMB mode is activated when the value of BIT-4 is 0. In one embodiment, the RPMB access method can be set to either normal RPMB mode or advanced RPMB mode based on the RPMB region enable field (bRPMBRegionEnable).

[0190] The RPMB cell descriptor can be stored in the access mode memory 300 in the storage device 50. The memory controller can identify the device access mode based on the RPMB cell descriptor stored in the storage device 50 (more specifically, the BIT-4 of the RPMB region enable field (bRPMBRegionEnable) in the RPMB cell descriptor).

[0191] Figure 11 This is a diagram illustrating a device descriptor stored in a storage device according to an embodiment of the present disclosure.

[0192] refer to Figure 4 and Figure 11A device descriptor can be provided from host 400 to storage device 50. For example, the device descriptor can be provided via a query request PIU. The device descriptor can provide various parameters of storage device 50. The device descriptor may include information indicating whether storage device 50 supports a second access mode. In one embodiment, the device descriptor may include an extended UFS feature support field (dExtendedUFSFeatureSupport). This field indicates the features supported by the device. bit[0] indicates the Field Firmware Update (FFU) function, bit[1] indicates the Production Status Awareness (PSA) function, bit[2] indicates the Device Lifetime Improvement function, bit[3] indicates the Refresh Operation function, bit[4] indicates the Device Overheating function, bit[5] indicates the Device Underheating function, bit[6] indicates the Extended Temperature Range function, bit[7] indicates the Host Aware Performance Booster (HPB) Reserved Area, bit[8] indicates the Write Booster function, bit[9] indicates the Performance Throttling function, and bit

[10] indicates the Second Access Mode function. When each bit is set to 1, it means that the function corresponding to that bit is supported. That is, bit

[10] of the UFS Feature Support field (dExtendedUFSFeatureSupport) can indicate whether the Secure Storage Area 110a supports the Second Access Mode function, and the memory controller can check this to identify the device access mode. For example, when bit

[10] of the UFS Feature Support field (dExtendedUFSFeatureSupport) is checked to 0, the access mode of the corresponding device can be the first access mode, and therefore the access mode of the device can be identified as the first access mode. The device descriptor can be stored in the access mode memory 300 in the storage device 50. In one embodiment, when the secure storage area 110a is RPMB, bit

[10] of the UFS Feature Support field (dExtendedUFSFeatureSupport) can indicate whether advanced RPMB features are supported.

[0193] Figure 12 This is a diagram illustrating the result code included in an RPMB message according to an embodiment of the present disclosure.

[0194] refer to Figure 4 and Figure 12 The result of the operation performed on RPMB can be stored in result register 113. For example, result register 113 can store a result code indicating the result of the operation performed on RPMB. Figure 12Examining the result codes, 0000h (0008h) indicates that the operation performed on the RPMB was successful; 0001h (0081h) indicates a normal failure; 0002h (0082h) indicates authentication failure, such as a MAC comparison mismatch or MAC calculation failure; 0003h (0083h) indicates counter failure, such as a counter mismatch when comparing counters with each other, or a counter increment failure; 0004h (0084h) indicates address failure, such as an address out of range or an incorrect address arrangement; 0005h (0085h) indicates write failure, such as a failure to write data / counter / results; and 0006h (0086h) indicates read failure, such as a failure to read data / counter / results. 0007h indicates that the authentication key has not been programmed, and this value is only valid before the authentication key is programmed and is no longer used after the authentication key is programmed. Additionally, 0008h (0088h) indicates a failure to access the secure write protection configuration block, such as a failure to read or write the secure write protection configuration; 0009h (0089h) indicates invalid secure write protection block configuration parameters, such as invalid LUNs or inactive logical units, data lengths, logical block addresses, logical block numbers, overlapping regions, etc.; 000Ah (008Ah) indicates that secure write protection is not applicable, such as when a logical unit is configured to another write protection mode. In this case, the result code value in parentheses indicates the value used when the write counter expires.

[0195] These result codes can be provided from storage device 50 to host 400 via a response PIU to the command PIU. As a result of comparing host access mode and device access mode by memory controller 200, when the two RPMB modes do not match, it can be determined that the situation corresponds to a general failure, and 0001h (0081h) can be stored as a result code in result register 113, and such a result code can be provided to host 400 via a response PIU.

[0196] Figure 13 This is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0197] refer to Figure 1 , Figure 4 and Figure 13 Storage device 50 can receive commands during operation S1301. The commands can be received from host 400 and can be commands related to secure storage area 110a, or more specifically, commands requesting access to secure storage area 110a.

[0198] Based on the received command, the memory controller 200 can identify the host access mode in operation S1303. In one embodiment, the host access mode can be identified by checking the total additional header length field and one or more additional header fields in the basic header field of the command. For example, when the total additional header length field in the basic header field of the command has a value of 0, or when the additional header fields of the command do not include information required for authentication, the host access mode can be identified as a first access mode. Additionally, when the total additional header length field in the basic header field of the command has a non-zero value, or when the additional header fields of the command include information required for authentication, the host access mode can be identified as a second access mode.

[0199] Subsequently, the memory controller 200 can identify the device access mode based on the device access mode information stored in the storage device 50, and can compare the identified host access mode and device access mode in operation S1305. The device access mode information can be stored in the access mode memory 300 in the storage device 50. For example, when information indicating that a second access mode is not supported is stored in the device descriptor 310 stored in the access mode memory 300, or when information indicating that the second access mode is deactivated is stored in the cell descriptor 320, the device access mode can be identified as the first access mode. Additionally, when information indicating that a second access mode is supported is stored in the device descriptor 310 stored in the access mode memory 300, or when information indicating that the second access mode is activated is stored in the cell descriptor 320, the device access mode can be identified as the second access mode.

[0200] When the two access modes match in operation S1307, that is, when both the host access mode and the device access mode are the first access mode, or both the host access mode and the device access mode are the second access mode, in operation S1309, access to the secure storage area can be performed according to the matched access modes.

[0201] When two access modes do not match in operation S1307, that is, when one of the host access mode and the device access mode is the first access mode and the other is the second access mode, an error message indicating the error can be provided to the host 400 in response to the command in operation S1311.

[0202] Figure 14 This is a flowchart illustrating an authenticated data write operation performed in normal RPMB mode according to an embodiment of the present disclosure.

[0203] refer to Figure 1 , Figure 4 and Figure 14In normal RPMB mode, host 400 can send three command PIUs to perform an authenticated data write operation, while storage device 50 can send three response PIUs. Write operations in normal RPMB mode can be executed after the memory controller 200 verifies that both the host access mode and device access mode match normal RPMB mode.

[0204] Specifically, an authenticated data write operation may include the process of transmitting RPMB messages of authenticated data write request, result read request, and result read response via PIU.

[0205] Authenticated data write requests can be executed through operations S1401 to S1407, result read requests can be executed through operations S1409 to S1415, and result read responses can be executed through operations S1417 to S1421.

[0206] An authenticated data write request includes the process by which host 400 transmits an RPMB message and the data to be stored to storage device 50, the RPMB message requesting that the data be stored in the RPMB.

[0207] A result read request may be a request from host 400 to storage device 50 to send an RPMB message, which includes the value stored in the result register of the RPMB that stores the execution result of the authenticated data write operation.

[0208] The result read response can be a response from storage device 50 to host 400 to transmit an RPMB message providing the value of the result register.

[0209] In operation S1401, host 400 may provide a command PIU to storage device 50. The command PIU transmitted in operation S1401 may be a security protocol output command instructing host 400 to send data. In operation S1403, storage device 50 may provide a ready-to-transmit PIU to host 400 in response to the command PIU received in operation S1401. The ready-to-transmit PIU may be a PIU provided when storage device 50 is ready to receive data to be provided by host 400. In one embodiment, the ready-to-transmit PIU may be a PIU providing a message instructing storage device 50 to be ready to receive a data output PIU.

[0210] In operation S1405, host 400 may provide a data output PIU to storage device 50. The data output PIU provided by host 400 may include an RPMB message corresponding to an authenticated data write request. The RPMB message transmitted in operation S1405 may include padding bytes, authentication data, and metadata. The metadata may include data to be stored in the RPMB. Because... Figure 14 This illustrates a scenario where an authenticated data write operation is performed in normal RPMB mode, and the data can include multiple blocks of 256 bytes each. See later. Figure 15 The RPMB message transmitted in operation S1405 is described in more detail.

[0211] In operation S1407, storage device 50 may provide a response PIU to host 400. The response PIU sent in operation S1407 may be a response to a command PIU sent in operation S1401.

[0212] In operation S1409, host 400 may provide a command PIU to storage device 50. The command PIU transmitted in operation S1409 may be a security protocol output command instructing host 400 to send data. Subsequently, in operation S1411, storage device 50 may provide a ready-to-transmit PIU to host 400 in response to the command PIU received in operation S1409. The ready-to-transmit PIU may be a PIU provided when storage device 50 is ready to receive data to be provided by host 400. In one embodiment, the ready-to-transmit PIU may be a PIU providing a message instructing storage device 50 to be ready to receive a data output PIU.

[0213] In operation S1413, host 400 may provide a data output PIU to storage device 50. The data output PIU provided in operation S1413 may include an RPMB message corresponding to a result read request. See later. Figure 16 In one embodiment, the RPMB message included in the data output PIU provided in operation S1413 is described in more detail.

[0214] In operation S1415, storage device 50 may provide a response PIU to host 400. The response PIU sent in operation S1415 may be a response to the command PIU sent in operation S1409.

[0215] In operation S1417, host 400 may provide a command PIU to storage device 50. The command PIU provided in operation S1417 may be a security protocol input command that indicates a command to request data and information from storage device 50.

[0216] In operation S1419, storage device 50 may provide a data input PIU to host 400. The data input PIU transmitted in operation S1419 may include an RPMB message corresponding to a result read response. The RPMB message transmitted in operation S1419 may include padding bytes, authentication data, and metadata. The metadata may include an updated write count value and a value in a result register indicating the execution result of the authenticated data write operation. See later. Figure 17 The RPMB message transmitted in operation S1419 is described in more detail.

[0217] In operation S1421, storage device 50 may provide a response PIU to host 400. The response PIU sent in operation S1421 may be a response to the command PIU sent in operation S1417.

[0218] Figure 15 The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1405.

[0219] refer to Figure 1 , Figure 4 , Figure 14 and Figure 15 The RPMB message corresponding to an authenticated data write request may include padding bytes, authentication data, and metadata.

[0220] Padding bytes can be bits added to synchronize predetermined data formats or data communication. In one embodiment, the field corresponding to the padding byte can be "0".

[0221] The authentication data included in the RPMB message corresponding to the authenticated data write request can be obtained from a reference. Figure 4 The MAC generated by the host access controller 410 is described.

[0222] Metadata may include the data stored in the RPMB, a random number, the current write count, the address corresponding to the data, the number of data blocks (here, one block is 256B), and a request message type indicating that the RPMB message is an authenticated data write request. In one embodiment, the field corresponding to the random number may be "0".

[0223] Figure 16 The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1413.

[0224] refer to Figure 1 , Figure 4 , Figure 14 and Figure 16The RPMB message corresponding to the result read request may include padding bytes, authentication data, and metadata.

[0225] In one embodiment, in the RPMB message corresponding to a result read request, only the request message type included in the metadata can have a value, and the values ​​of the remaining fields can be "0". The request message type can include the code value 0005h indicating that the RPMB message is a result read request.

[0226] Figure 17 The illustration shows an embodiment of the present disclosure. Figure 14 The diagram shows the operation of the RPMB message provided by S1419.

[0227] refer to Figure 1 , Figure 4 , Figure 14 and Figure 17 The RPMB message corresponding to the result read response may include padding bytes, authentication data, and metadata.

[0228] Padding bytes can be bits added to synchronize predetermined data formats or data communication. In one embodiment, the field corresponding to the padding byte can be "0".

[0229] The authentication data included in the RPMB message corresponding to the result read response can be obtained from the reference. Figure 4 The MAC generated by the device access controller 210 is described.

[0230] Specifically, the access execution unit 212 can generate metadata to be included in the RPMB message, and use the generated metadata and the authentication key 111 stored in the RPMB to generate a MAC.

[0231] Metadata may include an updated write count value, the address of data stored via a certified data write operation, a result code indicating the outcome of the certified data write operation, and "0300h," which is a response message type code indicating that the RPMB message is a certified data write response. Here, the address can be related to the reference... Figure 15 The value of the address included in the RPMB message corresponding to the authenticated data write request is described.

[0232] In one embodiment, the padding bytes, data, random number, and block count fields included in the RPMB message corresponding to the result read response can be "0".

[0233] Figure 18 This is a flowchart illustrating an authenticated data read operation performed in normal RPMB mode according to an embodiment of the present disclosure.

[0234] refer to Figure 1 , Figure 4 and Figure 18 In normal RPMB mode, host 400 can send two command PIUs to perform an authenticated data read operation, while storage device 50 can send two response PIUs. Read operations in normal RPMB mode can be executed after the memory controller 200 verifies that both the host access mode and device access mode match normal RPMB mode.

[0235] Specifically, an authenticated data read operation may include the process of transmitting a corresponding RPMB message via PIU for each of the authenticated data read request and authenticated data read response.

[0236] An authenticated data read request can be executed through operations S1801 to S1807, and an authenticated data read response can be executed through operations S1809 to S1813.

[0237] An authenticated data read request includes the process of host 400 transmitting an RPMB message to storage device 50 indicating a read request for data stored in the RPMB, and an authenticated data read response includes the process of storage device 50 transmitting data read from the RPMB to host 400.

[0238] In operation S1801, host 400 may provide a command PIU to storage device 50. The command PIU provided in operation S1801 may be a security protocol output command instructing host 400 to send data.

[0239] In operation S1803, storage device 50 can provide host 400 with a readiness to transmit PIU.

[0240] In operation S1805, host 400 may provide a data output PIU to storage device 50. The data output PIU provided in operation S1805 may include an RPMB message. Specifically, the RPMB message provided in operation S1805 may include metadata. Here, the metadata includes a random number generated by the host, the address to be read, a block count indicating the number of data blocks to be read, and a request message type indicating that the RPMB message is an authenticated data read request. See later. Figure 19 A more detailed description of the RPMB message corresponding to the authenticated data read request.

[0241] In operation S1807, storage device 50 may provide a response PIU to host 400. The response PIU provided by storage device 50 may be a response to the command PIU transmitted in operation S1801.

[0242] In operation S1809, host 400 may provide a command PIU to storage device 50. The command PIU provided in operation S1809 may be a security protocol input command that instructs the storage device 50 to request data and information.

[0243] In operation S1811, storage device 50 may provide a data input PIU to host 400. The data input PIU provided by storage device 50 may include an RPMB message. Specifically, the RPMB message provided in operation S1811 may include padding bytes, authentication data, and metadata. Here, the authentication data may be a MAC generated by storage device 50. The metadata may include the data read from the RPMB, a random number, an address, a block count indicating the number of data blocks read, and a response message type indicating that the RPMB message is an authenticated data read response. See later. Figure 20 To describe in more detail the RPMB messages corresponding to the authenticated data read response.

[0244] In operation S1813, storage device 50 may provide a response PIU to host 400. The response PIU received by host 400 in operation S1813 may be a response to the command PIU transmitted in operation S1809.

[0245] Figure 19 The illustration shows an embodiment of the present disclosure. Figure 18 The diagram shows the operation of the RPMB message provided by S1805.

[0246] refer to Figure 1 , Figure 4 , Figure 18 and Figure 19 The RPMB message corresponding to an authenticated data read request may include metadata and padding bytes, but not authentication data. The padding bytes may be bits added to synchronize a predetermined data format or data communication. In one embodiment, the field corresponding to the padding bytes may be "0".

[0247] Metadata may include a random number generated by the host, the address to be read, a block count indicating the number of data blocks to be read, and a request message type indicating that the RPMB message is an authenticated data read request.

[0248] In various embodiments, the corresponding value of each of the padding bytes, MAC, data, write counter, and result included in the RPMB message corresponding to the authenticated data read request can be "0".

[0249] Figure 20 The illustration shows an embodiment of the present disclosure. Figure 18 The diagram shows the operation of the RPMB message provided by S1811.

[0250] refer to Figure 1 , Figure 4 , Figure 18 and Figure 20 The RPMB message corresponding to the authenticated data read response may include authentication data and metadata. The authentication data may be a MAC generated by the device access controller 210 of storage device 50. The metadata may include the data read from the RPMB, a random number, an address, a block count indicating the number of data blocks read, and a response message type indicating that the RPMB message is an authenticated data read response.

[0251] The random number can be the random number included in the RPMB message corresponding to the authenticated data read request transmitted via operation S1805, i.e., a value obtained by copying the random value generated by host 400 as is. The address and the block count of read data can be the same values ​​as the address to be read and the block count indicating the number of data blocks to be read included in the RPMB message corresponding to the authenticated data read request. The result can be a result code indicating the execution result of the authenticated data read operation. The response message type can be code 0400h, which indicates that the RPMB message is an authenticated data read response.

[0252] The host access controller 410 included in host 400 can receive RPMB messages containing data read according to an authenticated data read operation, and then use the authentication key included in host access controller 410 and the metadata included in the RPMB message to operate the MAC. Host access controller 410 can only obtain the read data if the MAC calculated by host access controller 410 matches the MAC generated by storage device 50 as authentication data included in the RPMB message.

[0253] If passed Figures 14 to 20 As described, in authenticated data write and read operations under normal RPMB mode, a single command PIU is provided to offer the data to be stored or the data already read. However, additional command PIUs or response PIUs may be required to transmit RPMB messages. This can lead to delays in RPMB access speed, design complexity, etc.

[0254] Figure 21 This is a flowchart illustrating an authenticated data write operation performed in advanced RPMB mode according to an embodiment of the present disclosure.

[0255] refer to Figure 1 , Figure 4 and Figure 21In advanced RPMB mode, host 400 can send a single command PIU to perform an authenticated data write operation, and storage device 50 can send a single response PIU. Write operations in advanced RPMB mode can be executed after the memory controller 200 verifies that both the host access mode and device access mode match to advanced RPMB mode.

[0256] Specifically, in operation S2101, host 400 can provide a command PIU to storage device 50. The command PIU may include an RPMB message in an additional header segment. The command PIU may be a security protocol output command instructing host 400 to send data. (More details later...) Figure 22 The description provides a more detailed account of the RPMB messages transmitted during operation S2101.

[0257] In operation S2103, storage device 50 may provide host 400 with a ready-to-transmit PIU in response to the command PIU received in operation S2101.

[0258] In operation S2105, host 400 may provide a data output PIU to storage device 50. Since host 400 has already provided the RPMB message to storage device 50 in operation S2101 by including the RPMB message in an additional header segment of the command PIU, the data output PIU transmitted in operation S2105 may not include the RPMB message and may only include the data to be stored in the RPMB.

[0259] In operation S2107, storage device 50 may provide a response PIU to host 400. The response PIU provided by storage device 50 may include an RPMB message. The RPMB message may be included in the additional header segment of the response PIU.

[0260] Figure 22 The illustration shows an embodiment of the present disclosure. Figure 21 A diagram showing the structure of the command PIU transmitted in operation S2101.

[0261] refer to Figure 1 , Figure 4 , Figure 21 and Figure 22 The command PIU transmitted in operation S2101 can be a PIU using an additional header field, which is consistent with the reference. Figures 14 to 20 The command PIU transmitted in the described embodiments differs. Therefore, the field indicating the total additional header segment length information included in the basic header segment can be set to a non-zero value (02h).

[0262] The additional header field of the command PIU transmitted in operation S2101 may include an RPMB message. The RPMB message included in the additional header field may include references... Figure 15 The description describes some data in the RPMB message corresponding to the authenticated data write request.

[0263] Specifically, the additional header fields of the PIU command can include authentication data and metadata. Figure 15 Unlike RPMB messages, the metadata included in the additional header segment may not include the data to be stored in the RPMB. The metadata may include a random number generated by the host, the current write count, the address corresponding to the data, the number of data blocks (4KB in this case), and a request message type (0003h) indicating that the RPMB message is an authenticated data write request. Authentication data may be provided by a reference... Figure 4 The MAC generated by the device access controller 210 is described. Here, the metadata or authentication data included in the additional header segment and sent may be information required for authentication.

[0264] Figure 23 The illustration shows an embodiment of the present disclosure. Figure 21 A diagram showing the structure of the response PIU transmitted in operation S2107.

[0265] refer to Figure 1 , Figure 4 , Figure 21 and Figure 23 The response PIU transmitted in operation S2107 can be a PIU with additional header segments, which is consistent with the reference. Figures 14 to 20 The response PIU transmitted in the described embodiments differs. Therefore, the field indicating the total additional header segment length information included in the basic header segment can be set to a non-zero value (02h).

[0266] The additional header segment of the response PIU transmitted in operation S2107 may include an RPMB message. The RPMB message included in the additional header segment may include references... Figure 17 The description indicates that the result reads some data from the corresponding RPMB message in the response.

[0267] Specifically, the additional header fields in the PIU response may include authentication data and metadata. The metadata may include a write count value for the write counter updated based on the execution of the authenticated data write operation, the address of the data stored by the authenticated data write operation, a result code indicating the result of the authenticated data write operation, and a response message type indicating that the RPMB message is an authenticated data write response. Here, the address may be related to the reference... Figure 22The authenticated data described is written to the same address as the value included in the RPMB message corresponding to the request. The random number can be generated through copying and referencing. Figure 22 The authenticated data described is obtained by including a random number in the RPMB message corresponding to the request. Figure 4 The device access controller 210 described uses metadata and authentication keys stored in the RPMB to generate a MAC.

[0268] Figure 24 This is a flowchart illustrating an authenticated data read operation performed in advanced RPMB mode according to an embodiment of the present disclosure.

[0269] refer to Figure 1 , Figure 4 and Figure 24 In advanced RPMB mode, host 400 can send a single command PIU to perform an authenticated data read operation, and storage device 50 can send a single response PIU. Read operations based on advanced RPMB mode can be executed after the memory controller 200 verifies that both the host access mode and device access mode match to advanced RPMB mode.

[0270] Specifically, in operation S2401, host 400 can provide a command PIU to storage device 50. The command PIU may include an RPMB message in an additional header segment. The command PIU may be a security protocol input command instructing host 400 to request data transfer to storage device 50. (More details to follow...) Figure 25 The description provides a more detailed account of the RPMB messages transmitted in operation S2401.

[0271] In operation S2403, storage device 50 can use the RPMB message included in the command PIU received in operation S2401 to read data stored in the RPMB and provide host 400 with a data input PIU including the read data. Since host 400 has provided the RPMB message to storage device 50 in operation S2401 by including the RPMB message in an additional header segment of the command PIU, the data input PIU transmitted in operation S2403 may not include the RPMB message and may only include the data read from the RPMB.

[0272] In operation S2405, storage device 50 may provide a response PIU to host 400. The response PIU provided by storage device 50 may include an RPMB message. The RPMB message may be included in the additional header segments of the response PIU. See later. Figure 26To describe in more detail the RPMB message provided by storage device 50 to host 400 in operation S2405. Here, the metadata and authentication data included in the additional header segments and sent can be information required for authentication.

[0273] Figure 25 The illustration shows an embodiment of the present disclosure. Figure 24 A diagram showing the structure of the command PIU transmitted in operation S2401.

[0274] refer to Figure 1 , Figure 4 , Figure 24 and Figure 25 The command PIU transmitted in operation S2401 can be a PIU with an additional header field, which is consistent with the reference. Figures 14 to 20 The command PIU transmitted in the described embodiments differs. Therefore, the field indicating the total additional header segment length information included in the basic header segment can be set to a non-zero value (02h).

[0275] The additional header field of the command PIU transmitted in operation S2401 may include an RPMB message. The RPMB message included in the additional header field may include references... Figure 19 The data included in the RPMB message corresponding to the authenticated data read request described.

[0276] Specifically, the additional header field of the command PIU may include authentication data and metadata. In one embodiment, the command PIU may include only metadata and not authentication data. The metadata may include a random number generated by the host, the address to be read, a high-level RPMB block count indicating the number of data blocks to be read (here, one block is 4KB), and 0004h, which is a request message type indicating that the RPMB message included in the additional header field is an authenticated data read request. In one embodiment, the value corresponding to each of the MAC, write counter, and result included in the RPMB message included in the additional header field may be "0".

[0277] Figure 26 The illustration shows an embodiment of the present disclosure. Figure 24 A diagram showing the structure of the response PIU transmitted in operation S2405.

[0278] refer to Figure 1 , Figure 4 , Figure 24 and Figure 26 The response PIU transmitted in operation S2405 can be a PIU with additional header segments, which is consistent with the reference. Figures 14 to 20The response PIU transmitted in the described embodiments differs. Therefore, the field indicating the total additional header segment length information included in the basic header segment can be set to a non-zero value (02h).

[0279] The additional header field of the response PIU transmitted in operation S2405 may include an RPMB message. The RPMB message included in the additional header field may be related to the reference... Figure 20 The description describes the RPMB message corresponding to the authenticated data read response. Additional header fields may include authentication data and metadata. Authentication data may be a MAC generated by the device access controller 210 of storage device 50. Metadata may include the data read from the RPMB, a random number, an address, an advanced RPMB block count indicating the number of data blocks read, and a response message type indicating that the RPMB message is an authenticated data read response.

[0280] The random number can be the random number included in the RPMB message corresponding to the authenticated data read request transmitted via operation S2401, i.e., a value obtained by copying the random value generated by host 400 as is. The address and the number of data blocks read can be the same values ​​as the address to be read and the block count indicating the number of data blocks to be read included in the RPMB message corresponding to the authenticated data read request. The result can be a result code indicating the execution result of the authenticated data read operation. The response message type can be code 0400h, which indicates that the RPMB message is an authenticated data read response.

[0281] The host access controller 410 included in host 400 can receive data read according to the authenticated data read operation in operation S2403, and in operation S2405, after receiving the RPMB message corresponding to the authenticated data read response, host access controller 410 can use the authentication key included in host access controller 410 and the metadata included in the RPMB message to operate the MAC. Host access controller 410 can only obtain the read data when the MAC calculated by host access controller 410 matches the MAC generated by storage device 50 as authentication data included in the RPMB message.

[0282] According to the reference Figures 21 to 26 In the described embodiment, in advanced RPMB mode, unlike normal RPMB mode, RPMB messages are included in an additional header segment and sent, eliminating the need for data input PIUs or data output PIUs. Therefore, in advanced RPMB mode, since the number of PIUs to be sent is less than in normal RPMB mode, advanced RPMB mode can be a mode capable of accessing RPMB at a faster speed than normal RPMB mode.

[0283] Figure 27 This is a diagram illustrating a PIU transmitter 2700 included in an initiator device according to an embodiment of the present disclosure.

[0284] refer to Figure 4 and Figure 27 The host 400 and storage device 50 can perform RPMB-related operations simultaneously while sending and receiving PIUs. Figures 14 to 26 During the described authenticated data write and authenticated data read operations, both host access controller 410 and device access controller 210 can generate a PIU and send or receive a PIU sent from the other to perform authentication. Therefore, host access controller 410 and device access controller 210 may include features described later. Figure 27 Both the PIU transmitter 2700 and the PIU receiver 2800 are described.

[0285] The device that generates the PIU can be the initiating device. The device that receives the generated PIU can be the target device. When the host access controller 410 provides the PIU to the device access controller 210, the host 400 can be the initiating device, and the storage device 50 can be the target device. Conversely, when the device access controller 210 provides the PIU to the host access controller 410, the storage device 50 can be the initiating device, and the host 400 can be the target device.

[0286] The PIU transmitter 2700 may include a MAC calculator 2720, an authentication key storage unit 2730, a metadata generator 2710, and a PIU generator 2740.

[0287] The authentication key storage unit 2730 can store authentication keys. The authentication key storage unit 2730 can correspond to a reference. Figure 4 The security storage area 110a described includes an authentication key 111. The authentication key can be stored in the RPMB according to the authentication key programming operation. Since the authentication key is used to generate MACs when performing authenticated data write and authenticated data read operations, it needs to be stored in the RPMB before performing these operations. Metadata generator 2710 can generate metadata. Metadata can be included in RPMB messages. Depending on the type of RPMB message, the metadata can include different components. Components that can be included in the metadata may be references... Figure 9 The description includes at least one of the following: write count value, request message type, response message type, result, address, random number, data, advanced RPMB data, block count, and advanced RPMB block count.

[0288] Metadata generator 2710 can provide the generated metadata to MAC calculator 2720 and PIU generator 2740.

[0289] The MAC calculator 2720 can generate a MAC using metadata and an authentication key stored in the authentication key storage unit 2730. Specifically, the MAC calculator 2720 can generate a MAC using a hash-based message authentication code (HMAC SHA-256). The target device can use the generated MAC to perform authentication. The MAC can have a length of 256 bits (32 bytes). The authentication key used to generate the MAC can also be 256 bits. However, according to one embodiment of this disclosure, the size of the MAC and the authentication key is not limited. The MAC calculator 2720 can provide the generated MAC to the PIU generator 2740.

[0290] PIU generator 2740 can generate a PIU to be provided to the target device. Specifically, PIU generator 2740 can generate an RPMB message that includes authentication data and metadata. The authentication data can be a MAC generated by MAC calculator 2720. In one embodiment, the authentication data included in the RPMB corresponding to the authentication key programming request provided in the authentication key programming operation can be the authentication key itself.

[0291] In normal RPMB mode, the PIU generator 2740 can provide the generated RPMB message to the target device by either inputting a data PIU or outputting a data PIU.

[0292] In advanced RPMB mode, PIU generator 2740 can generate a PIU that includes the RPMB message in the additional header segment and provide the generated PIU to the target device. In advanced RPMB mode, the total additional header segment length field in the basic header segment of the PIU that includes the RPMB message can include a non-zero value.

[0293] Figure 28 This is a diagram illustrating a PIU receiver 2800 included in a target device according to an embodiment of the present disclosure.

[0294] refer to Figure 4 and Figure 28 The host 400 and storage device 50 can perform RPMB-related operations simultaneously while sending and receiving PIUs. Figures 14 to 26During the described authenticated data write and authenticated data read operations, both the host access controller 410 and the device access controller 210 can generate a PIU and send or receive a PIU sent from the other to perform authentication. Therefore, the host access controller 410 and the device access controller 210 may include a PIU receiver 2800 and a reference... Figure 27 The PIU transmitter 2700 is described.

[0295] The device that generates the PIU can be the initiating device. The device that receives the generated PIU can be the target device. When the host access controller 410 provides the PIU to the device access controller 210, the host 400 can be the initiating device, and the storage device 50 can be the target device. Conversely, when the device access controller 210 provides the PIU to the host access controller 410, the storage device 50 can be the initiating device, and the host 400 can be the target device.

[0296] The PIU receiver 2800 may include a PIU parser 2810, a MAC calculator 2820, and a MAC comparator 2830. The PIU parser 2810 can receive PIUs provided by the initiating device. The PIUs received by the PIU parser 2810 can be data input PIUs or data output PIUs in normal RPMB mode. The PIUs received by the PIU parser 2810 can also be command PIUs or response PIUs in advanced RPMB mode.

[0297] The PIU parser 2810 can obtain RPMB messages by parsing the received PIUs, and can obtain the included metadata and authentication data by parsing the RPMB messages. In one embodiment, the metadata can include different components depending on the type of the RPMB message. Components that can be included in the metadata may be references... Figure 9 The description includes at least one of the following: write count value, request message type, response message type, result, address, random number, data, advanced RPMB data, block count, and advanced RPMB block count.

[0298] The authentication data can be a MAC generated by the initiating device. In one embodiment, the authentication data included in the RPMB corresponding to the authentication key programming request provided in the authentication key programming operation can be the authentication key itself.

[0299] The MAC Calculator 2820 can obtain the authentication key previously stored on the target device. The authentication key previously stored on the target device can be the same value as the authentication key stored on the initiator's device.

[0300] The MAC calculator 2820 can calculate the MAC using metadata received from the PIU parser 2810 and the authentication key previously stored in the target device. For example, the MAC calculator 2820 can calculate the MAC using a hash-based message authentication code (HMACSHA-256). The MAC calculator 2820 can then provide the calculated MAC to the MAC comparator 2830.

[0301] The MAC comparator 2830 compares whether the MAC received from the PIU parser 2810 and the MAC received from the MAC calculator 2820 match, and outputs an authentication result based on the comparison result. The authentication result can be used to perform authenticated data write operations and authenticated data read operations as operations on the RPMB.

[0302] Therefore, authentication may fail when the authentication keys stored in the initiating device and the target device are different, or when the metadata used to calculate the MAC is different. Authentication can only succeed when the authentication keys stored in the initiating device and the target device are the same, and the metadata used to calculate the MAC is also the same. Thus, RPMB can provide data storage capabilities with high security.

[0303] Figure 29 The illustration shows an embodiment according to the present disclosure. Figure 1 A diagram of another embodiment of the memory controller.

[0304] refer to Figure 29 The memory controller 1000 may include a processor 1010, an internal memory 1020, an error correction code circuit 1030, a host interface 1040, a buffer memory interface 1050, and a memory interface 1060.

[0305] The processor 1010 can perform various operations or generate various commands for controlling the memory device 100. When a request is received from the host 400, the processor 1010 can generate a command based on the received request and send the generated command to a queue controller (not shown). Additionally, the processor 1010 can identify the host access mode of the host's secure storage area based on the command received from the host, and compare the host access mode with the device access mode to determine whether to perform an access operation on the secure storage area. Additionally, authentication operations for accessing the secure storage area can be performed to access the secure storage area in the memory device 100.

[0306] Internal memory 1020 may store various information fragments required for the operation of memory controller 1000. For example, internal memory 1020 may include a logical and physical address mapping table. Internal memory 1020 may be configured with at least one of random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), cache, and tightly coupled memory (TCM). In one embodiment, device access mode information may be stored in internal memory 1020, but is not limited thereto, and may be stored in a separate memory different from memory controller 1000.

[0307] Error correction code circuit 1030 is configured to use error correction codes (ECC) to detect and correct errors in data received from memory device 100. Processor 1010 can adjust the read voltage and control memory device 100 to perform a reread based on the error detection results of error correction code circuit 1030. In one embodiment, the error correction block can be provided as a component of memory controller 1000.

[0308] The host interface 1040 can exchange commands, addresses, data, etc., between the memory controller 1000 and the host 400. For example, the host interface 1040 can receive requests, addresses, data, etc. from the host 400, and can output data read from the memory device 100 to the host 400. The host interface 1040 can use communication standards and interfaces to communicate with the host 400, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Faster (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Low Load DIMM (LRDIMM), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0309] The buffer memory interface 1050 can transmit data between the processor 1010 and the buffer memory. The buffer memory can be used as operational memory or cache memory of the memory controller 1000, and can store data used in the storage device 50. Through the processor 1010, the buffer memory interface 1050 can use the buffer memory as a read buffer, write buffer, mapping buffer, etc. According to one embodiment, the buffer memory may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR4 SDRAM, Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), or Rambus Dynamic Random Access Memory (RDRAM). When the buffer memory is included in the memory controller 1000, the buffer memory interface 1050 can be omitted.

[0310] The memory interface 1060 can exchange commands, addresses, data, etc., between the memory controller 1000 and the memory device 100. For example, the memory interface 1060 can send commands, addresses, data, etc. to the memory device 100, and can receive data from the memory device 100 through a channel. The memory interface 1060 can store data in the secure storage area of ​​the memory device 100, or read data from the secure storage area, according to the instructions of the processor 1010.

[0311] Figure 30 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0312] refer to Figure 30 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0313] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. In one embodiment, memory controller 2100 can access secure storage areas within memory device 2200. For example, memory controller 2100 can be configured to control read, program, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 can be referenced... Figure 1 The memory controller 200 described is implemented in the same way.

[0314] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and error corrector.

[0315] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 is configured to communicate with external devices via at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards or interfaces. External devices can request the memory controller 2100 to access secure storage areas within the memory device 2200.

[0316] For example, memory device 2200 may consist of various non-volatile memory elements, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM). Memory device 2200 may include secure storage regions and general storage regions. Secure storage regions are memory blocks with restricted access, such as those accessible only through predetermined special commands or authentication, while general storage regions are memory blocks that can be accessed without separate restrictions.

[0317] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card such as a PC card (PCMCIA International Association), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), a secure digital card (SD) card (SD, miniSD, microSD, or SDHC), and universal flash storage (UFS).

[0318] Figure 31This is a block diagram illustrating a solid-state drive (SSD) system that applies a storage device according to an embodiment of the present disclosure.

[0319] refer to Figure 31 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0320] According to one embodiment of this disclosure, the SSD controller 3210 can perform reference... Figure 1 The functions of the memory controller 200 are described.

[0321] SSD controller 3210 can control multiple flash memories 3221 to 322n in response to signals received from host 3100. For example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. The signal can be transmitted in the form of various commands and can be a signal requesting access to a secure storage area located within a portion of the multiple flash memories 3221 to 322n, or a signal responding to such a request.

[0322] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power from host 3100 and can charge it. When the power supply from host 3100 is insufficient, auxiliary power supply 3230 can provide power to SSD 3200. For example, auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0323] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0324] Figure 32 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure.

[0325] refer to Figure 32 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0326] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include a controller that controls components, interfaces, graphics engines, etc., included in user system 4000. Application processor 4100 can be provided as a system-on-a-chip (SoC).

[0327] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged in a stacked package (POP) and provided as a single semiconductor package.

[0328] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 may be included in application processor 4100.

[0329] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented using non-volatile semiconductor memory elements such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive device) such as a memory card and as an external drive device for user system 4000.

[0330] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be connected to a reference. Figure 1 The described memory device 100 operates identically. That is, a portion of a plurality of non-volatile memory devices may include a secure storage region. Storage module 4400 may be related to the reference... Figure 1 The storage device 50 described operates in the same manner. Storage module 4400 can be compared with the reference... Figure 1 The storage device 50 described operates in the same manner.

[0331] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touchball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0332] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of this disclosure as defined in the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A storage device, comprising: A memory device, including a secure storage area for storing data therein, the secure storage area being accessed based on authentication; An access mode memory is configured to store information therein about device access modes related to the operating mode of the secure storage area; as well as The memory controller is configured to receive commands related to the secure storage area from an external host, and to process the commands based on whether information about the host access mode included in the commands matches information about the device access mode. Each of the host access mode and the device access mode is either a first access mode or a second access mode, wherein access to the secure storage area is faster in the second access mode than in the first access mode.

2. The storage device of claim 1, wherein the memory controller is further configured to access the secure storage area upon receiving a predetermined command or upon passing the authentication.

3. The storage device of claim 1, wherein the host access mode information includes information relating to the operating mode of the secure storage region, and the host access mode information is provided by the external host.

4. The storage device of claim 1, wherein the memory controller is further configured to: when the device access mode is the first access mode, obtain information required for the authentication from an additional command provided after the command.

5. The storage device of claim 1, wherein the memory controller is further configured to: obtain information required for authentication from the command when the device access mode is the second access mode.

6. The storage device of claim 1, wherein the command comprises: The common segment is included in the commands transmitted between the external host and the memory controller. A unique field, which includes unique values ​​depending on the type of the command, and Additional segments, which are different from the common segments.

7. The storage device of claim 6, wherein the common segment includes information indicating the length of the additional segment.

8. The storage device of claim 7, wherein the memory controller is further configured to identify the host access pattern based on at least one of the additional segment and information indicating the length of the additional segment.

9. The storage device of claim 8, wherein when the length of the additional segment is 0 or the additional segment does not include the information required for authentication, the memory controller identifies the host access mode as the first access mode.

10. The storage device of claim 8, wherein the memory controller identifies the host access mode as the second access mode when the length of the additional segment is not 0 or the additional segment includes information required for the authentication.

11. The storage device of claim 10, wherein the information required for authentication includes at least a portion of metadata for the secure storage area and authentication key data.

12. The storage device according to claim 1, wherein, When the host access mode and the device access mode match, the memory controller accesses the secure storage area according to the matched access mode.

13. The storage device of claim 1, wherein the memory controller is further configured to: refuse access to the secure storage area when the host access mode and the device access mode do not match.

14. The storage device of claim 13, wherein the memory controller denies access to the secure storage area by providing the external host with information indicating an error.

15. The storage device of claim 1, wherein the access mode memory is further configured to store one or more of the following: information relating to whether the storage device supports the second access mode and information relating to whether the storage device activates the second access mode.

16. A method of operating a storage device, the storage device including a memory device, an access mode memory, and a memory controller, the memory device including a secure storage region for storing data, the secure storage region being accessed based on authentication, the access mode memory being configured to store device access mode information relating to the operation mode of the secure storage region of the storage device, and the memory controller being configured to process commands received from an external host, the method comprising: Receive commands related to the secure storage area from the external host; Based on the command, a host access pattern is identified, which indicates the external host's operating mode for the secure storage area within the storage device. as well as Compare the host access mode and the device access mode. Each of the host access mode and the device access mode is either a first access mode or a second access mode, wherein access to the secure storage area is faster in the second access mode than in the first access mode.

17. The method of claim 16, further comprising: When the host access mode and the device access mode match, the secure storage area is accessed according to the matched access mode.

18. The method of claim 16, further comprising: When the host access mode and the device access mode do not match, information indicating an error is provided to the external host.

19. A computing system, comprising: Storage devices, including: A memory device, including a secure storage area for storing data therein, the secure storage area being accessed based on authentication; An access mode memory is configured to store information therein regarding device access modes related to the operating mode of the secure storage region; and A memory controller is configured to control the memory device and the access mode memory; and The host device is configured to provide commands related to the secure storage region to the storage device. The memory controller is further configured to process the command based on whether the host access mode information included in the command matches the device access mode information, and Each of the host access mode and the device access mode is either a first access mode or a second access mode, wherein access to the secure storage area is faster in the second access mode than in the first access mode.

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