AXI Bus-Based Bandwidth Control Method, Device, and Electronic Device

Abstract

The present application proposes a bandwidth control method, device and electronic device based on the AXI bus, which relates to the field of communication technologies. The method includes: obtaining a pre-configured time window; determining the read data volume of the time window and the write data volume of the time window; comparing the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus. Thus, by comparing the read data volume and the read data volume threshold, as well as the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is realized, so that the real-time control of the bandwidth can be ensured, the problem of competing for the bandwidth of the AXI bus is reduced, and the control accuracy of the bandwidth is improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a bandwidth control method, apparatus, and electronic device based on the AXI bus. Background Art

[0002] Currently, the emergence of on-chip interconnect buses has solved the data communication of each subsystem within the chip and the need to access on-chip and off-chip storage devices. Due to the transmission rate of data communication, there are bottlenecks in the read and write speeds of each subsystem to the storage device. Storage devices such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and Flash Memory. Therefore, when each subsystem accesses the storage device simultaneously, there will be a problem of competing for the bandwidth of the AXI bus among the subsystems.

[0003] In related technologies, the bandwidth control method of the AXI (Advanced eXtensible Interface) bus is to adjust the Quality of Service (QoS) signals of each subsystem to increase or decrease the data transmission priority of the corresponding subsystem, thereby achieving the purpose of controlling the bandwidth of the AXI bus.

[0004] However, in the above solution, the cooperation of the storage device is required to achieve the purpose of bandwidth control, and there may still be a problem of competing for the bandwidth of the AXI bus, and the control accuracy of the bandwidth is low. Summary of the Invention

[0005] This application aims to solve at least one of the technical problems in the related technologies to some extent.

[0006] This application proposes a bandwidth control method based on the AXI bus to compare the read data volume and the read data volume threshold within a time window, as well as the write data volume and the write data volume threshold, and adjust the Ready signal according to the comparison result to achieve the control of the bandwidth of the AXI bus, thereby being able to ensure real-time bandwidth control, reduce the occurrence of the problem of competing for the bandwidth of the AXI bus, and improve the control accuracy of the bandwidth.

[0007] An embodiment of the first aspect of the present application provides a bandwidth control method based on the AXI bus, including: obtaining a preconfigured time window; determining the read data volume of the time window and the write data volume of the time window; comparing the read data volume and the write data volume with corresponding read data volume thresholds and write data volume thresholds respectively to obtain comparison results; and adjusting the Ready signal according to the comparison results to control the bandwidth of the AXI bus.

[0008] Optionally, the method further includes: determining the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; and determining the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

[0009] Optionally, the determining the read data volume of the time window includes: determining the read data volume of the i-th communication transmission; determining the read data volume of the first i communication transmissions according to the read data volume of the first i - 1 communication transmissions and the read data volume of the i-th communication transmission, where i is an integer greater than 1; and determining the read data volume of the first i communication transmissions as the read data volume of the time window.

[0010] Optionally, the determining the read data volume of the i-th communication transmission includes: obtaining the data length and data bit width of the read data of the i-th communication transmission; multiplying the data length of the read data by 2 to the power of the data bit width to obtain a multiplication result, and determining the multiplication result as the read data volume of the i-th communication transmission.

[0011] Optionally, the determining the write data volume of the time window includes: determining the write data volume of the i-th communication transmission; determining the write data volume of the first i communication transmissions according to the write data volume of the first i - 1 communication transmissions and the write data volume of the i-th communication transmission, where i is an integer greater than 1; and determining the write data volume of the first i communication transmissions as the write data volume of the time window.

[0012] Optionally, the determining the write data volume of the i-th communication transmission includes: obtaining the data length and data bit width of the write data of the i-th communication transmission; multiplying the data length of the write data by 2 to the power of the data bit width to obtain a multiplication result, and determining the multiplication result as the write data volume of the i-th communication transmission.

[0013] Optionally, adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus includes: when the comparison result is that the read data volume is greater than or equal to the read data volume threshold, pulling down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the read data volume is less than the read data volume threshold, keeping the Ready signal of the read address channel of the AXI bus in its original state.

[0014] Optionally, adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus includes: when the comparison result is that the write data volume is greater than or equal to the write data volume threshold, pulling down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the write data volume is less than the write data volume threshold, keeping the Ready signal of the write address channel of the AXI bus in its original state.

[0015] The bandwidth control method based on the AXI bus according to the embodiments of the present application obtains a pre-configured time window; determines the read data volume of the time window and the write data volume of the time window; compares the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and adjusts the Ready signal according to the comparison result to control the bandwidth of the AXI bus. Thus, by comparing the read data volume and the read data volume threshold, and the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is realized, so that the real-time control of the bandwidth can be ensured, the problem of competing for the bandwidth of the AXI bus is reduced, and the control accuracy of the bandwidth is improved.

[0016] An embodiment of the second aspect of the present application provides a bandwidth control device based on the AXI bus, including: a first acquisition module for acquiring a pre-configured time window; a first determination module for determining the read data volume of the time window and the write data volume of the time window; a comparison module for comparing the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and a control module for adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus.

[0017] As a possible implementation manner of the embodiment of the present application, the device further includes: a second determination module and a third determination module; the second determination module is configured to determine the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; the third determination module is configured to determine the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

[0018] As a possible implementation manner of the embodiment of the present application, the first determination module is specifically configured to determine the read data volume of the i-th communication transmission, and determine the read data volume of the first i communication transmissions according to the read data volume of the previous i - 1 communication transmissions and the read data volume of the i-th communication transmission; where i is an integer greater than 1; and determine the read data volume of the first i communication transmissions as the read data volume of the time window.

[0019] As a possible implementation manner of the embodiment of the present application, the first determination module is specifically configured to obtain the data length and data bit width of the read data of the i-th communication transmission; multiply the data length of the read data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the i-th communication transmission.

[0020] As a possible implementation manner of the embodiment of the present application, the first determination module is specifically configured to determine the write data volume of the i-th communication transmission; determine the write data volume of the first i communication transmissions according to the write data volume of the previous i - 1 communication transmissions and the write data volume of the i-th communication transmission; where i is an integer greater than 1; and determine the write data volume of the first i communication transmissions as the write data volume of the time window.

[0021] As a possible implementation manner of the embodiment of the present application, the first determination module is specifically configured to obtain the data length and data bit width of the write data of the i-th communication transmission; multiply the data length of the write data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the i-th communication transmission.

[0022] As a possible implementation manner of the embodiment of the present application, the control module is specifically configured to, in the case where the comparison result is that the read data volume is greater than or equal to the read data volume threshold, pull down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus; in the case where the comparison result is that the read data volume is less than the read data volume threshold, keep the Ready signal of the read address channel of the AXI bus in its original state.

[0023] As a possible implementation of the embodiment of the present application, the control module is specifically configured to, in the case where the comparison result is that the write data volume is greater than or equal to the write data volume threshold, pull down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus; in the case where the comparison result is that the write data volume is less than the write data volume threshold, keep the Ready signal of the write address channel of the AXI bus in its original state.

[0024] The bandwidth control device based on the AXI bus according to the embodiment of the present application obtains a preconfigured time window; determines the read data volume of the time window and the write data volume of the time window; compares the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and adjusts the Ready signal according to the comparison result to control the bandwidth of the AXI bus. Thus, by comparing the read data volume and the read data volume threshold, and the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is realized, so that the bandwidth can be controlled in real time, the problem of competing for the bandwidth of the AXI bus is reduced, and the control accuracy of the bandwidth is improved.

[0025] The embodiment of the third aspect of the present application provides a bandwidth control module, which includes: a time counting unit, a data statistics unit, and a data limiting unit; the time counting unit is respectively connected to the data statistics unit and the data limiting unit, and generates a flag signal at the end of each time window to mark each time window; the data statistics unit is respectively connected to the time counting unit and the data limiting unit, and is used to count the read data volume and the write data volume of the time window; the data limiting unit is used to compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result, and adjust the Ready signal according to the comparison result to control the bandwidth of the AXI bus.

[0026] The embodiment of the fourth aspect of the present application provides a chip, which includes: a bandwidth control module for executing the bandwidth control method based on the AXI bus proposed in the embodiment of the first aspect of the present application.

[0027] The embodiment of the fifth aspect of the present application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the bandwidth control method based on the AXI bus proposed in the embodiment of the first aspect of the present application.

[0028] A sixth - aspect embodiment of the present application provides a non - transitory computer - readable storage medium storing computer instructions, and the computer instructions are used to cause the computer to execute the AXI - bus - based bandwidth control method proposed in the first - aspect embodiment of the present application.

[0029] A seventh - aspect embodiment of the present application provides a computer program product. When the instruction processor in the computer program product executes, it executes the AXI - bus - based bandwidth control method proposed in the first - aspect embodiment of the present application. Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above - mentioned and / or additional aspects and advantages of the present application will become apparent and be easily understood from the following description of the embodiments in conjunction with the drawings, where:

[0031] Figure 1 is a flowchart of the AXI - bus - based bandwidth control method provided in Embodiment 1 of the present application;

[0032] Figure 2 is a flowchart of the AXI - bus - based bandwidth control method provided in Embodiment 2 of the present application;

[0033] Figure 3 is a schematic diagram of an AXI - bus - based bandwidth control method;

[0034] Figure 4 is a schematic structural diagram of the AXI - bus - based bandwidth control device provided in Embodiment 3 of the present application;

[0035] Figure 5 is a block diagram of an electronic device for an AXI - bus - based bandwidth control method shown according to an exemplary embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application, and should not be construed as limiting the present application.

[0037] The present application proposes an AXI - bus - based bandwidth control method, device, and electronic device.

[0038] Figure 1The flowchart of the bandwidth control method based on the AXI bus provided by Embodiment 1 of this application. It should be noted that the bandwidth control method based on the AXI bus can be applied to a bandwidth control device based on the AXI bus. Among them, the bandwidth control device based on the AXI bus can be, for example, an electronic device or software installed in the electronic device. Taking the execution entity as the bandwidth control device based on the AXI bus as an example for illustration.

[0039] Among them, the electronic device can be any device with computing power. Devices with computing power can be, for example, a personal computer (PC for short), a server, etc.

[0040] As Figure 1 shown, the bandwidth control method based on the AXI bus includes the following steps:

[0041] Step 101, obtain a pre-configured time window.

[0042] Among them, the pre-configured time window can be represented as t, and the range of t can be limited according to actual needs and is not limited here.

[0043] For example, the period of a clock with a unit of 24 MHz (megahertz) can be 41.67 ns (nanoseconds). Shifting 41.67 ns to the left by 4 bits, that is, 666.7 ns, the configuration range of the time window t can be 666.7 ns to 42666.7 ns.

[0044] Among them, the time window can be 1 or multiple, which is not limited here.

[0045] It should be noted that the AXI bus communicates through the AXI protocol. The AXI protocol includes five channels. Different channels are independent of each other and have differences. Before communicating through the channels, the Valid signal (handshake signal) and the Ready signal (handshake signal) need to be used for handshaking. Among them, the five channels are the read address channel, the read data channel, the write address channel, the write data channel, and the write response channel.

[0046] Step 102, determine the read data volume of the time window and the write data volume of the time window.

[0047] Among them, there is a flag signal at the end of each time window, which is used to mark each time window. At the flag signal of each time window, the read data volume and the write data volume of this time window will be cleared so that the read data volume and the write data volume can be re-determined in the next time window.

[0048] Among them, in each time window, one communication transmission can be performed, or multiple communication transmissions can be performed. That is to say, in each time window, multiple handshakes can be performed, and the number of successful handshakes can be one or multiple, which is not specifically limited here.

[0049] In some embodiments, as a possible implementation manner, the process of the bandwidth control device based on the AXI bus to determine the read data volume of the time window can be, for example, to determine the read data volume of the i-th communication transmission; according to the read data volume of the previous i - 1 communication transmissions and the read data volume of the i-th communication transmission, determine the read data volume of the previous i communication transmissions; where i is an integer greater than 1; and determine the read data volume of the previous i communication transmissions as the read data volume of the time window.

[0050] In some embodiments, the process of the bandwidth control device based on the AXI bus to determine the read data volume of the i-th communication transmission can be to obtain the data length and data bit width of the read data of the i-th communication transmission; multiply the data length of the read data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the i-th communication transmission.

[0051] Among them, when i is 1, the bandwidth control device based on the AXI bus can obtain the data length and data bit width of the read data of the first communication transmission; multiply the data length of the read data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the first communication transmission.

[0052] Among them, the number of times the sender (each subsystem) and the receiver (storage device) can communicate within a single time window can be one or multiple, which is not specifically limited here.

[0053] Among them, the subsystem can include: a camera module, an image acceleration module, an artificial intelligence module, etc.

[0054] Among them, the data length and data bit width of the read data for each communication transmission can be the same or different, which is not specifically limited here.

[0055] Among them, the read data volume of the time window is the cumulative result of the read data volumes of multiple communication transmissions.

[0056] It should be noted that when the Vaild signal and the Ready signal of the read address channel of the AXI bus are both high, it is recorded as a successful handshake of the read address channel, that is, communication can be performed.

[0057] For example, based on the read data volume of the previous i-1 communication transmissions and the read data volume of the i-th communication transmission, the read data volume of the previous i communication transmissions is determined, and the calculation formula can be as shown in formula (1).

[0058] r_data i = r_data i-1 +(arlen + 1)*2 arsize Formula (1)

[0059] Among them, r_data i represents the read data volume of the previous i communication transmissions, with the unit of Byte (byte), r_data i-1 represents the read data volume of the previous i-1 communication transmissions, "arlen + 1" represents the data length of the read data in the i-th communication transmission, and arsize represents the width of the read data in the i-th communication transmission.

[0060] In some embodiments, as another possible implementation manner, the process of the AXI bus-based bandwidth control device determining the write data volume of the time window can be, for example, determining the write data volume of the i-th communication transmission; based on the write data volume of the previous i-1 communication transmissions and the write data volume of the i-th communication transmission, determining the write data volume of the previous i communication transmissions; where i is an integer greater than 1; and determining the write data volume of the previous i communication transmissions as the write data volume of the time window.

[0061] In some embodiments, the process of the AXI bus-based bandwidth control device determining the write data volume of the i-th communication transmission can be to obtain the data length and data bit width of the write data in the i-th communication transmission; perform a multiplication process on the data length of the write data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the i-th communication transmission.

[0062] Among them, when i is 1, the AXI bus-based bandwidth control device can obtain the data length and data bit width of the write data in the first communication transmission; perform a multiplication process on the data length of the write data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the first communication transmission.

[0063] Among them, the data length and data bit width of the write data in each communication transmission can be the same or different, and no specific limitation is made here.

[0064] Among them, the write data volume of the time window is the accumulated result of the write data volumes of multiple communication transmissions.

[0065] It should be noted that when the Vaild and Ready signals of the write address channel of the AXI bus are both high, it is recorded as a successful handshake of the write address channel, that is, communication can be carried out.

[0066] For example, according to the amount of write data transmitted in the previous i - 1 communications and the amount of write data transmitted in the i-th communication, determine the amount of write data transmitted in the previous i communications. The calculation formula can be as shown in formula (2).

[0067] w_data i = w_data i-1 +(awlen + 1)*2 awsize Formula (2)

[0068] Among them, w_data i represents the amount of write data transmitted in the previous i communications, with the unit of Byte. w_data i-1 represents the amount of write data transmitted in the previous i - 1 communications. "awlen + 1" represents the data length of the write data transmitted in the i-th communication, and awsize represents the width of the write data transmitted in the i-th communication.

[0069] Step 103: Compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result.

[0070] Among them, the read data volume threshold can be pre-configured according to actual needs. For example, the read data volume threshold can be 1 Byte to 2 16 (65535) Byte (bytes), which is not limited here. Among them, the write data volume threshold can be pre-configured according to actual needs. For example, the write data volume threshold can be 1 Byte to 2 16 (65535) Byte (bytes), which is not limited here.

[0071] In the embodiments of the present application, in each time window, the bandwidth control device based on the AXI bus will compare the read data volume with the corresponding read data volume threshold and compare the write data volume with the corresponding write data volume threshold, and a comparison result can be obtained. Among them, there can be multiple comparison results, and the specific quantity is not limited here.

[0072] In the embodiments of the present application, in each time window, every time a communication transmission is performed, the bandwidth control device based on the AXI bus will compare the read data volume with the corresponding read data volume threshold once and compare the write data volume with the corresponding write data volume threshold once.

[0073] Step 104: Adjust the Ready signal according to the comparison result to control the bandwidth of the AXI bus.

[0074] In some embodiments, by adjusting the Ready signal, the bandwidth of the AXI bus is controlled, and the obtained bandwidth thresholds (read bus bandwidth threshold, write bus bandwidth threshold) can be calculated.

[0075] As a possible implementation, the bandwidth control device based on the AXI bus can also determine the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; and determine the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

[0076] Among them, the calculation formula of the read bus bandwidth threshold can be as shown in formula (3).

[0077]

[0078] Among them, r_bandwidth is the read bus bandwidth threshold, with the unit of MB / s, r_thr is the read data volume threshold, and MB (MByte, megabyte) is the unit of the read data volume threshold, and t is the time window, with the unit of s (second).

[0079] Among them, the calculation formula of the read bus bandwidth threshold can be as shown in formula (4).

[0080]

[0081] Among them, w_bandwidth is the write bus bandwidth threshold, with the unit of MB / s, and w_thr is the write data volume threshold.

[0082] In summary, by obtaining the pre-configured time window; determining the read data volume of the time window and the write data volume of the time window; comparing the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus. Thus, by comparing the read data volume and the read data volume threshold, as well as the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is achieved, which can ensure real-time control of the bandwidth, reduce the occurrence of problems of competing for the bandwidth of the AXI bus, and improve the control accuracy of the bandwidth.

[0083] Figure 2 This is a schematic flowchart of the bandwidth control method based on the AXI bus provided in the second embodiment of this application. As Figure 2 shown, the bandwidth control method based on the AXI bus includes the following steps:

[0084] Step 201, obtain the pre-configured time window.

[0085] Step 202: Determine the read data volume of the time window and the write data volume of the time window.

[0086] Step 203: Compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result.

[0087] It should be noted that the detailed content of Steps 201 to 203 can refer to the relevant content in the above embodiments, which will not be elaborated here.

[0088] Step 204: In the case where the comparison result is that the read data volume is greater than or equal to the read data volume threshold, pull down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus.

[0089] In the embodiment of the present application, in the case where the read data volume of the time window is greater than or equal to the read data volume threshold, the bandwidth control device based on the AXI bus can pull down the Ready signal of the read address channel of the AXI bus of this time window, backpressure the data transmission of the AXI bus, that is, block the transmission of read data, so as to achieve the control of the bandwidth of the AXI bus.

[0090] In the embodiment of the present application, in each time window, every time a communication transmission is performed, the bandwidth control device based on the AXI bus will compare the read data volume with the corresponding read data volume threshold once. In the case where the read data volume is greater than or equal to the read data volume threshold, the Ready signal is pulled down until the next time window, that is to say, until the next time window, there will be no successful handshake and no further accumulation operation of the read data volume.

[0091] Step 205: In the case where the comparison result is that the read data volume is less than the read data volume threshold, keep the Ready signal of the read address channel of the AXI bus in its original state.

[0092] In the embodiment of the present application, in the case where the read data volume of the time window is less than the read data volume threshold, the bandwidth control device based on the AXI bus does not need to pull down the Ready signal of the read address channel of the AXI bus of this time window, that is, it can keep the original state.

[0093] Step 206: In the case where the comparison result is that the write data volume is greater than or equal to the write data volume threshold, pull down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus.

[0094] In an embodiment of the present application, when the write data volume in a time window is greater than or equal to the write data volume threshold, the bandwidth control device based on the AXI bus can pull down the Ready signal of the write address channel of the AXI bus in this time window, backpressure the data transmission of the AXI bus, that is, block the transmission of write data, so as to achieve the control of the bandwidth of the AXI bus.

[0095] In an embodiment of the present application, in each time window, every time a communication transmission is performed, the bandwidth control device based on the AXI bus will compare the write data volume with the corresponding write data volume threshold once. When the write data volume is greater than or equal to the write data volume threshold, the Ready signal is pulled down until the next time window. That is to say, until the next time window, there will be no successful handshake and no further accumulation operation of the write data volume.

[0096] Step 207, when the comparison result is that the write data volume is less than the write data volume threshold, keep the Ready signal of the write address channel of the AXI bus in its original state.

[0097] In an embodiment of the present application, when the write data volume in a time window is less than the write data volume threshold, the bandwidth control device based on the AXI bus does not need to pull down the Ready signal of the write address channel of the AXI bus in this time window, that is, it can keep the original state.

[0098] In summary, by obtaining a pre-configured time window; determining the read data volume of the time window and the write data volume of the time window; comparing the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; when the comparison result is that the read data volume is greater than or equal to the read data volume threshold, pulling down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the read data volume is less than the read data volume threshold, keeping the Ready signal of the read address channel of the AXI bus in its original state; when the comparison result is that the write data volume is greater than or equal to the write data volume threshold, pulling down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the write data volume is less than the write data volume threshold, keeping the Ready signal of the write address channel of the AXI bus in its original state. Thus, by comparing the read data volume and the read data volume threshold, as well as the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is achieved, which can ensure real-time control of the bandwidth, reduce the occurrence of problems of competing for the bandwidth of the AXI bus, and improve the control accuracy of the bandwidth.

[0099] For example, Figure 3Schematic diagram of a bandwidth control method based on the AXI bus. In Figure 3 , bandwidth control modules are added at the AXI bus exits of each subsystem. The number of bandwidth control modules can be multiple. The bandwidth control module can include a time calculation unit, a data statistics unit, and a data limiting unit. The bandwidth control device based on the AXI bus can implement bandwidth control for each subsystem to access the storage device through the bandwidth control module. The CPU (software) is used to configure information, which can include a time window t, a read data volume threshold, a write data volume threshold, and an enable signal for the bandwidth control module.

[0100] The bandwidth control device based on the AXI bus can generate a flag signal at the end of each time window through the time counting unit to mark each time window; during each communication (when the handshake of the read address channel is successful), the bandwidth control device based on the AXI bus can obtain the read data volume of the communication transmission through the data statistics unit, accumulate the read data volume of each communication transmission, and obtain the read data volume within a time window; during each communication (when the handshake of the write address channel is successful), the bandwidth control device based on the AXI bus can obtain the write data volume of the communication transmission through the data statistics unit, accumulate the write data volume of each communication transmission, and obtain the write data volume within a time window; the bandwidth control device based on the AXI bus can compare the read data volume with the read data volume threshold through the data limiting unit. When the read data volume is greater than or equal to the read data volume threshold, it pulls down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus until the next time window; the bandwidth control device based on the AXI bus can compare the write data volume with the write data volume threshold through the data limiting unit. When the write data volume is greater than or equal to the write data volume threshold, it pulls down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus until the next time window.

[0101] Figure 4 Schematic diagram of the structure of the bandwidth control device based on the AXI bus provided in Embodiment 3 of the present application.

[0102] As Figure 4 shown, the bandwidth control device 400 based on the AXI bus includes: a first acquisition module 410, a first determination module 420, a comparison module 430, and a control module 440.

[0103] Among them, the first acquisition module 410 is used to acquire a pre-configured time window; the first determination module 420 is used to determine the read data volume of the time window and the write data volume of the time window; the comparison module 430 is used to compare the read data volume and the write data volume with corresponding read data volume thresholds and write data volume thresholds respectively to obtain comparison results; the control module 440 is used to adjust the Ready signal according to the comparison results to control the bandwidth of the AXI bus.

[0104] As a possible implementation manner of an embodiment of the present application, the device further includes: a second determination module and a third determination module; the second determination module is used to determine the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; the third determination module is used to determine the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

[0105] As a possible implementation manner of an embodiment of the present application, the first determination module 420 is specifically used to determine the read data volume of the i-th communication transmission; determine the read data volume of the previous i communication transmissions according to the read data volume of the previous i - 1 communication transmissions and the read data volume of the i-th communication transmission; where i is an integer greater than 1; and determine the read data volume of the previous i communication transmissions as the read data volume of the time window.

[0106] As a possible implementation manner of an embodiment of the present application, the first determination module 420 is specifically used to acquire the data length and data bit width of the read data of the i-th communication transmission; perform a multiplication process on the data length of the read data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the i-th communication transmission.

[0107] As a possible implementation manner of an embodiment of the present application, the first determination module 420 is specifically used to determine the write data volume of the i-th communication transmission; determine the write data volume of the previous i communication transmissions according to the write data volume of the previous i - 1 communication transmissions and the write data volume of the i-th communication transmission; where i is an integer greater than 1; and determine the write data volume of the previous i communication transmissions as the write data volume of the time window.

[0108] As a possible implementation manner of an embodiment of the present application, the first determination module 420 is specifically used to acquire the data length and data bit width of the write data of the i-th communication transmission; perform a multiplication process on the data length of the write data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the i-th communication transmission.

[0109] As a possible implementation manner of the embodiment of the present application, the control module 440 is specifically configured to, when the comparison result is that the read data volume is greater than or equal to the read data volume threshold, pull down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the read data volume is less than the read data volume threshold, keep the Ready signal of the read address channel of the AXI bus in its original state.

[0110] As a possible implementation manner of the embodiment of the present application, the control module 440 is specifically configured to, when the comparison result is that the write data volume is greater than or equal to the write data volume threshold, pull down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus; when the comparison result is that the write data volume is less than the write data volume threshold, keep the Ready signal of the write address channel of the AXI bus in its original state.

[0111] The bandwidth control device based on the AXI bus according to the embodiment of the present application obtains a preconfigured time window; determines the read data volume of the time window and the write data volume of the time window; compares the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; and adjusts the Ready signal according to the comparison result to control the bandwidth of the AXI bus. Thus, by comparing the read data volume and the read data volume threshold, and the write data volume and the write data volume threshold within the time window, and adjusting the Ready signal according to the comparison result, the control of the bandwidth of the AXI bus is realized, so that the real-time control of the bandwidth can be ensured, the problem of competing for the bandwidth of the AXI bus can be reduced, and the control accuracy of the bandwidth can be improved.

[0112] To implement the above embodiment, the present application also proposes a bandwidth control module, which is characterized by including: a time counting unit, a data statistics unit, and a data limiting unit; the time counting unit is respectively connected to the data statistics unit and the data limiting unit, and generates a flag signal at the end of each time window to mark each time window; the data statistics unit is respectively connected to the time counting unit and the data limiting unit, and is used to count the read data volume and the write data volume of the time window; the data limiting unit is used to compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result, and adjust the Ready signal according to the comparison result to control the bandwidth of the AXI bus.

[0113] To implement the above embodiments, the present application further provides a chip, which is characterized by including: a bandwidth control module for executing the AXI bus-based bandwidth control method described in the embodiments of the present application.

[0114] To implement the above embodiments, the present application further provides an electronic device, as Figure 5 shown, Figure 5 is a block diagram of an electronic device for an AXI bus-based bandwidth control method shown according to an exemplary embodiment.

[0115] As Figure 5 shown, the above electronic device 1100 includes:

[0116] A memory (main memory) 1110 and a processor 1120, a bus 1130 connecting different components (including the memory 1110 and the processor 1120), and the memory 1110 stores a computer program, and when the processor 1120 executes the program, it implements the AXI bus-based bandwidth control method described in the embodiments of the present application.

[0117] The bus 1130 represents one or more of several types of bus architectures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus architecture in a variety of bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0118] The electronic device 1100 typically includes a variety of electronic device-readable media. These media can be any available media accessible by the electronic device 1100, including volatile and non-volatile media, removable and non-removable media.

[0119] The memory 1110 may further include a computer system-readable medium in the form of volatile memory, such as random access memory (RAM) 1140 and / or cache memory 1150. The electronic device 1100 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 1160 may be used to read and write non-removable, non-volatile magnetic media ( Figure 5 not shown, commonly referred to as a "hard disk drive"). Although Figure 5Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical medium) can be provided. In these cases, each drive can be connected to the bus 1130 through one or more data medium interfaces. The memory 1110 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present application.

[0120] A program / utility 1180 having a set (at least one) of program modules 1170 can be stored, for example, in the memory 1110. Such program modules 1170 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment. The program modules 1170 generally perform the functions and / or methods in the embodiments described in the present application.

[0121] The electronic device 1100 can also communicate with one or more external devices 1190 (such as a keyboard, a pointing device, a display 1091, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 1100, and / or communicate with any device that enables the electronic device 1100 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 1192. Moreover, the electronic device 1100 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 1193. As Figure 5 shown, the network adapter 1193 communicates with other modules of the electronic device 1100 through the bus 1130. It should be understood that although Figure 5 not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0122] The processor 1120 executes various functional applications and data processing by running the programs stored in the memory 1110.

[0123] It should be noted that for the implementation process and technical principle of the electronic device in this embodiment, refer to the foregoing explanation of the monitoring processing method of the embodiments of the present application, and details are not described herein again.

[0124] To implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute Figures 1 to 3 the AXI-bus-based bandwidth control method described in the embodiments.

[0125] To implement the above embodiments, the present application also provides a computer program product that, when executed by an instruction processor in the computer program product, executes Figures 1 to 3 the AXI-bus-based bandwidth control method described in the embodiments.

[0126] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0127] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0128] Any process or method description in a flowchart or described in other ways herein can be understood to represent a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0129] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.

[0130] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or combinations thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0131] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0132] In addition, each functional unit in various embodiments of the present application may be integrated into a processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0133] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A bandwidth control method based on the AXI bus, characterized in that, Including: Obtain a pre-configured time window; Determine the read data volume of the time window and the write data volume of the time window; Compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; In response to the comparison result that the read data volume is greater than or equal to the read data volume threshold, pull down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus, or, in response to the comparison result that the read data volume is less than the read data volume threshold, keep the Ready signal of the read address channel of the AXI bus in its original state; In response to the comparison result that the write data volume is greater than or equal to the write data volume threshold, pull down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus, or, in response to the comparison result that the write data volume is less than the write data volume threshold, keep the Ready signal of the write address channel of the AXI bus in its original state.

2. The method according to claim 1, characterized in that, The method further includes: Determine the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; Determine the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

3. The method according to claim 1, characterized in that, The determining the read data volume of the time window includes: Determine the read data volume of the i-th communication transmission; Determine the read data volume of the first i communication transmissions according to the read data volume of the first i - 1 communication transmissions and the read data volume of the i-th communication transmission; where i is an integer greater than 1; Determine the read data volume of the first i communication transmissions as the read data volume of the time window.

4. The method according to claim 3, characterized in that, The determining the read data volume of the i-th communication transmission includes: Obtain the data length and data bit width of the read data of the i-th communication transmission; Multiply the data length of the read data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the i-th communication transmission.

5. The method according to claim 1, characterized in that, The determining the write data volume of the time window includes: Determine the write data volume of the i-th communication transmission; Determine the write data volume of the first i communication transmissions according to the write data volume of the first i - 1 communication transmissions and the write data volume of the i-th communication transmission; where i is an integer greater than 1; Determine the write data volume of the first i communication transmissions as the write data volume of the time window.

6. The method according to claim 5, characterized in that, The determining the write data volume of the i-th communication transmission includes: Obtain the data length and data bit width of the write data of the i-th communication transmission; Multiply the data length of the write data by 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the i-th communication transmission.

7. A bandwidth control device based on the AXI bus, characterized in that, Including: A first obtaining module, configured to obtain a pre-configured time window; A first determining module, configured to determine the read data volume of the time window and the write data volume of the time window; A comparison module, configured to compare the read data volume and the write data volume with the corresponding read data volume threshold and write data volume threshold respectively to obtain a comparison result; A control module, configured to, in response to the comparison result indicating that the read data volume is greater than or equal to the read data volume threshold, pull down the Ready signal of the read address channel of the AXI bus to control the bandwidth of the AXI bus; or, in response to the comparison result indicating that the read data volume is less than the read data volume threshold, keep the Ready signal of the read address channel of the AXI bus in its original state; in response to the comparison result indicating that the write data volume is greater than or equal to the write data volume threshold, pull down the Ready signal of the write address channel of the AXI bus to control the bandwidth of the AXI bus; or, in response to the comparison result indicating that the write data volume is less than the write data volume threshold, keep the Ready signal of the write address channel of the AXI bus in its original state.

8. The device according to claim 7, characterized in that, The apparatus further includes: a second determination module and a third determination module; The second determination module is configured to determine the ratio of the read data volume threshold to the time window as the read bus bandwidth threshold; The third determination module is configured to determine the ratio of the write data volume threshold to the time window as the write bus bandwidth threshold.

9. The device according to claim 7, characterized in that, The first determination module is specifically configured to determine the read data volume of the i-th communication transmission; determine the read data volume of the first i communication transmissions according to the read data volume of the previous i - 1 communication transmissions and the read data volume of the i-th communication transmission; where i is an integer greater than 1; determine the read data volume of the first i communication transmissions as the read data volume of the time window.

10. The device according to claim 9, characterized in that, The first determination module is specifically configured to obtain the data length and data bit width of the read data of the i-th communication transmission; perform a multiplication process on the data length of the read data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the read data volume of the i-th communication transmission.

11. The device according to claim 7, characterized in that, The first determination module is specifically configured to determine the write data volume of the i-th communication transmission; determine the write data volume of the first i communication transmissions according to the write data volume of the previous i - 1 communication transmissions and the write data volume of the i-th communication transmission; where i is an integer greater than 1; determine the write data volume of the first i communication transmissions as the write data volume of the time window.

12. The device according to claim 11, characterized in that, The first determination module is specifically configured to obtain the data length and data bit width of the write data of the i-th communication transmission; perform a multiplication process on the data length of the write data and 2 to the power of the data bit width to obtain a multiplication result, and determine the multiplication result as the write data volume of the i-th communication transmission.

13. A bandwidth control module, characterized in that, including: a time counting unit, a data statistics unit, and a data limiting unit; The time counting unit is respectively connected to the data statistics unit and the data limiting unit, and generates a flag signal at the end of each time window for marking each time window; The data statistics unit is respectively connected to the time counting unit and the data limiting unit, and is configured to count the read data volume and write data volume of the time window; The data limiting unit is configured to compare the read data volume and the write data volume with corresponding read data volume thresholds and write data volume thresholds respectively to obtain comparison results. In response to the comparison result that the read data volume is greater than or equal to the read data volume threshold, the Ready signal of the read address channel of the AXI bus is pulled low to control the bandwidth of the AXI bus; or, in response to the comparison result that the read data volume is less than the read data volume threshold, the Ready signal of the read address channel of the AXI bus is kept in its original state. In response to the comparison result that the write data volume is greater than or equal to the write data volume threshold, the Ready signal of the write address channel of the AXI bus is pulled low to control the bandwidth of the AXI bus; or, in response to the comparison result that the write data volume is less than the write data volume threshold, the Ready signal of the write address channel of the AXI bus is kept in its original state.

14. A chip, characterized in that, Comprising: A bandwidth control module for executing the method according to any one of claims 1-6.

15. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-6.

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