An integrated circuit layout detection method, device and storage medium

Abstract

The application provides a kind of integrated circuit layout detection method, device and storage medium;Method includes: in layout, determine multi-finger structure, wherein multi-finger structure includes: at least one upper continuous source-drain and at least one upper continuous via, upper continuous source-drain is electrically connected with upper layer metal line by upper continuous via;The number of upper continuous source-drain and the number of upper continuous via are calculated;For multi-finger structure, if the number of its upper continuous source-drain is greater than the number of its upper continuous via, then determine that the multi-finger structure is unqualified multi-finger structure.The application can find design defects in time, thereby improving the yield of chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to an integrated circuit layout detection method and device and storage medium. BACKGROUND

[0002] With the continuous development of semiconductor technology, the number of electronic components in integrated circuits is increasing, and the internal structure is becoming more and more complex, which brings greater challenges to the design of integrated circuit layout.

[0003] In the integrated circuit layout, there are often multi-finger structures. Multi-finger structures need to be connected to enough vias, otherwise the parasitic resistance will be too large, which will reduce the yield of the chip. SUMMARY

[0004] The embodiments of the present application propose an integrated circuit layout detection method, device and storage medium, which can detect unqualified multi-finger structures with insufficient upper connection vias in the layout, and find design defects in time, thereby improving the yield of the chip.

[0005] The technical solution of the present application is as follows:

[0006] The embodiments of the present application provide an integrated circuit layout detection method, which comprises:

[0007] In the layout, a multi-finger structure is determined; the multi-finger structure comprises at least one upper connection source-drain end and at least one upper connection via; the upper connection source-drain end is electrically connected to an upper metal line through the upper connection via;

[0008] The number of the upper connection source-drain ends and the number of the upper connection vias are calculated;

[0009] For the multi-finger structure, if the number of its upper connection source-drain ends is greater than the number of its upper connection vias, it is determined that the multi-finger structure is an unqualified multi-finger structure.

[0010] The embodiments of the present application also provide an integrated circuit layout detection device, which comprises:

[0011] A determination unit is configured to determine a multi-finger structure in a layout; the multi-finger structure comprises at least one upper connection source-drain end and at least one upper connection via; the upper connection source-drain end is electrically connected to an upper metal line through the upper connection via;

[0012] A calculation unit is configured to calculate the number of the upper connection source-drain ends and the number of the upper connection vias;

[0013] A determination unit is configured to determine, for the multi-finger structure, if the number of its upper connection source-drain ends is greater than the number of its upper connection vias, the multi-finger structure is an unqualified multi-finger structure.

[0014] The embodiment of the present application further provides an integrated circuit layout detection device, the device comprises:

[0015] a memory, used for storing executable instructions;

[0016] a processor, used for executing the executable instructions stored in the memory, so as to realize the integrated circuit layout detection method in the above-mentioned scheme.

[0017] The embodiment of the present application further provides a storage medium, which stores executable instructions, and is used for causing the processor to execute, so as to realize the integrated circuit layout detection method in the above-mentioned scheme.

[0018] Therefore, the embodiment of the present application provides an integrated circuit layout detection method, device and storage medium, which can determine the multi-finger structure in the layout, calculate the number of the upper connection source-drain end and the number of the upper connection via in the multi-finger structure respectively, and compare the multi-finger structure, if the number of the upper connection source-drain end is greater than the number of the upper connection via, determine that the multi-finger structure is an unqualified multi-finger structure. In this way, the unqualified multi-finger structure with insufficient upper connection via in the layout is detected, the design defects are found in time for correction, the quality of the layout is improved, and the yield of the chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1A is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application;

[0020] Figure 1B is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application;

[0021] Figure 2A is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application Figure 3 ;

[0022] Figure 2B is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application Figure 4 ;

[0023] Figure 3 is a flowchart of an integrated circuit layout detection method provided by the embodiment of the present application;

[0024] Figure 4 is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application;

[0025] Figure 5A is a schematic diagram of an integrated circuit layout detection method provided by the embodiment of the present application Figure 6 ;

[0026] Figure 5B is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 7 ;

[0027] Figure 5C is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 8 ;

[0028] Figure 6 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 9 ;

[0029] Figure 7 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application

[0030] Figure 8 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 3 ;

[0031] Figure 3 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 2B ;

[0032] Figure 4 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application

[0033] Figure 4 is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 4 ;

[0034] Figure 5A is a schematic flow chart of a method for detecting an integrated circuit layout according to an embodiment of the present application Figure 5B ;

[0035] Figure 5C is a schematic structural diagram of a device for detecting an integrated circuit layout according to an embodiment of the present application

[0036] Figure 5A is a schematic structural diagram of a device for detecting an integrated circuit layout according to an embodiment of the present application DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application is further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0038] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets as each other and as other embodiments described herein, and that references to "some embodiments" are made merely for the purpose of convenience and without imputing to any or all of the referents any degree of preference or relation to the other referents.

[0039] If there are similar descriptions of "first / second" in the application file, the following explanations are added. In the following description, the terms "first / second / third" referred to merely distinguish similar objects and do not represent a specific order of the objects. Understandably, "first / second / third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

[0041] With the continuous development and evolution of the integrated circuit industry, layout design is the basis for the physical implementation of integrated circuits, and the quality of the design will directly affect the power consumption and performance of the basic circuit.

[0042] The multi-finger structure, also known as the multi-finger gate structure, is a structure in the layout, which represents the parallel connection of multiple MOS (Metal-Oxide-Semiconductor) tubes. It has a different shape from the conventional parallel connection structure. Figure 5B And Figure 5C The conventional parallel connection structure and the multi-finger structure in the layout are respectively illustrated, both of which represent the parallel connection of 6 MOS tubes. Figure 2A The conventional parallel connection structure in has 1 gate 01, while Figure 2B The multi-finger structure in has 6 gates 03. Figure 2A The width W1 of the MOS tube in is Figure 2B The width W2 of the MOS tube in is 6 times that of W1, while Figure 2A And Figure 2B The length of the MOS tube in is the same. The saturation current of the MOS tube is calculated as shown in the following formula (1):

[0043]

[0044] In the above formula (1), I D,SAT represents the saturation current of the MOS tube, μ represents the electron mobility, C OX represents the unit area gate oxide layer capacitance, W / L represents the width-length ratio of the MOS tube, and (V GS -VT ) represents the driving voltage. From equation (1) above, it can be seen that, under otherwise unchanged conditions, the saturation current I of the MOSFET... D,SAT and width-to-length ratio Proportional, width-to-length ratio The larger the value, the higher the saturation current I. D,SAT The larger.

[0045] Compared to Figure 2A The multi-fingered structure in the middle, Figure 2B The conventional parallel structure of the MOSFET in the circuit has a larger width W1 (W1 is 6 times W2). Therefore, Figure 6 The conventional parallel structure of MOSFETs in the circuit also has a relatively large width-to-length ratio, resulting in excessively high saturation current. Therefore, in layout design, designers can design MOSFETs with a multi-finger structure according to layout requirements, such as the cell height requirements of standard cells and the requirements of manufacturing process rule checks (DRC), to avoid excessively high saturation current.

[0046] However, the multi-finger structure includes an upper source-drain terminal, which needs to be electrically connected to the upper metal line through an upper via. If the number of upper vias is too small, the parasitic resistance of the source-drain terminal will increase, affecting the performance of the MOSFET.

[0047] like Figure 2A As shown, the upper source / drain terminals 101, 102, and 103 are electrically connected to the upper metal line 401 through only one upper connecting hole 301. This has a significant negative impact on the reliability of the layout.

[0048] a. If the equivalent cross-section of the conductor is too small, it will generate extremely high resistance, affecting the original timing requirements of the circuit designer;

[0049] b. Uneven current flow causes severe overheating at the through-hole;

[0050] c. If a single top-connecting via 301 fails during manufacturing, no other top-connecting vias will work, directly causing the MOSFET to stop working; in severe cases, it may even affect the operation of the entire circuit, causing the entire chip to fail to be fabricated.

[0051] And such Figure 2B As shown, the upper source and drain terminals 101, 102, and 103 are electrically connected to the upper metal line 402 through three upper connecting holes 302, 303, and 304. In this way, the parasitic resistance of the source and drain terminals is small, and even if one of the upper connecting holes fails, the MOSFET can still use the other upper connecting holes, thus not affecting the use of the entire MOSFET.

[0052] Since the analog layout needs to be manually edited, i.e. millions of transistors are manually connected according to the circuit diagram, it is inevitable that the upper connection via is set too few. The upper connection via set too few will not affect the passing of the layout circuit consistency check (LVS) and the manufacturing process rule check, so it is difficult to find in time through the two checks. Therefore, a new method is needed to check the unqualified multi-finger structure of the insufficient upper connection via in the layout, to find the design defects in time and improve the quality of the layout.

[0053] Figure 6 is an optional flowchart of the integrated circuit layout detection method provided by the embodiment of the present application, which will be described in combination with the steps shown in the figure. Figure 7

[0054] S101, in the layout, determine a multi-finger structure; the multi-finger structure includes at least one upper connection source-drain end and at least one upper connection via; the upper connection source-drain end is electrically connected with the upper layer metal line through the upper connection via.

[0055] In the embodiment of the present application, the detection device can first determine the multi-finger structure in the layout. As shown in the example, the multi-finger structure includes the upper connection source-drain ends 101, 102 and 103, and the upper connection vias 302, 303 and 304, wherein the upper connection source-drain ends 101, 102 and 103 are electrically connected with the upper layer metal line 402 through the upper connection vias 302, 303 and 304, respectively. Figure 3

[0056] In the embodiment of the present application, the detection device can first determine the target layer pattern in the layout based on the preset identification layer information, wherein the preset identification layer information is obtained by respectively mapping different digital identification layers to the layer of the process flow sheet, and the target layer pattern contains all the design patterns of the layer to be detected.

[0057] Then, the detection device can identify the MOS structure in the target layer pattern through Boolean operation. Figure 7 is a flowchart of identifying the MOS structure, referring to Figure 8 , the detection device can first identify the active area 501 in the target layer pattern; then filter out the target active area 502 intersecting with at least one gate structure 503 in the active area 501, wherein the material of the gate structure is usually polysilicon (Poly); and then remove the guard ring and diode structure in the target active area 502, so as to obtain the PMOS structure 504 and the NMOS structure 505.

[0058] It should be noted that Figure 4 ​​The diagram illustrates the layout representing a P-type substrate, where PMOS structure 504 surrounds P-type injection region 506 and N-well region 507, and NMOS structure 505 surrounds N-type injection region 508. If the layout represents an N-type substrate, then the PMOS structure surrounds the P-type injection region, and the NMOS structure surrounds both the N-type injection region and the P-well region.

[0059] After identifying the MOS structure, the detection device can calculate the number of side-by-side gate structures in the MOS structure, thereby determining a multi-fingered structure. These side-by-side gate structures are arranged in parallel within the layout. For any MOS structure, if the number of side-by-side gate structures is greater than or equal to 2, the MOS structure is determined to be a multi-fingered structure. Figure 4 , Figure 4 and Figure 4 The example, Figure 9 The MOS structure in the image has only one gate structure, so it will not be classified as a multi-finger structure. Figure 7 The MOS structure in the image has two side-by-side gate structures. Figure 5A The MOS structure in the image has three side-by-side gate structures, so all of them are classified as multi-finger structures.

[0060] S102. Calculate the number of upper source and drain terminals and the number of upper connecting holes.

[0061] In this embodiment of the application, after determining the multi-finger structure, the detection device can calculate the number of source-drain terminals and the number of connecting holes in the multi-finger structure.

[0062] In the embodiments of this application, such as Figure 5B and Figure 5C As shown in the example, the upper multi-finger metal wire 20 in the multi-finger structure is electrically connected to the upper source and drain terminals 101, 102 and 103, and the upper connecting holes 301, 302, 303 and 304 are located above the upper multi-finger metal wire 20. The detection device can determine the upper multi-finger metal wire 20 in the multi-finger structure based on these connection characteristics.

[0063] Then, the detection device can calculate the number of upper connecting holes located above the upper multi-finger metal wire and store it in count1; then, through Boolean operations, it can calculate the number of upper source / drain terminals intersecting the upper multi-finger metal wire and store it in count2. Figure 5A and Figure 5B For example, Figure 5C The number of upper and middle connecting holes 301 is 1, and the number of upper source and drain terminals 101, 102 and 103 is 3; Figure 10 The number of upper and middle connecting holes 302, 303 and 304 is 3, and the number of upper source and drain terminals 101, 102 and 103 is 3.

[0064] S103. For a multi-finger structure, if the number of source and drain terminals connected to it is greater than the number of connecting holes on it, then the multi-finger structure is determined to be a non-compliant multi-finger structure.

[0065] In this embodiment of the application, after determining the number of source-drain terminals and the number of connecting holes in any multi-finger structure, the detection device can compare the two. If the number of source-drain terminals is greater than the number of connecting holes, the multi-finger structure is determined to be a defective multi-finger structure.

[0066] In this embodiment, the detection device can compare the variables count1 and count2 stored in the system, where count1 stores the number of upper connecting holes and count2 stores the number of upper source-drain terminals. If count2 is greater than count1, the corresponding multi-finger structure is determined to be a defective multi-finger structure, and the defective multi-finger structure is located; if count2 is less than or equal to count1, the multi-finger structure is well-designed and will not be determined to be a defective multi-finger structure. (Reference) Figure 3 , Figure 2A and Figure 2B ,exist Figure 2A In the above, the number of source-drain terminals 101, 102, and 103 (count2) is 3, the number of connecting holes 301 (count1) is 1, and count2 is greater than count1. Therefore, the multi-finger structure is determined to be a defective multi-finger structure. Figure 2B In the given information, the number of upper source / drain terminals 101, 102, and 103 (count2) is 3, and the number of upper connecting holes 302, 303, and 304 (count1) is 3. Since count2 equals count1, this multi-finger structure will not be considered a defective multi-finger structure. Figure 2A In the above, the number of source and drain terminals 101, 102 and 103, count2, is 3, and the number of connecting holes 305, 306, 307, 308, 309 and 310, count1, is 6. Since count2 is less than count1, the multi-finger structure will not be judged as a defective multi-finger structure.

[0067] It is understandable that by using Boolean operations to identify and determine the multi-finger structure in the layout layer by layer, and then determining and comparing the number of source / drain terminals and the number of vias in the multi-finger structure, it is possible to accurately identify defective multi-finger structures with design flaws for correction, thereby improving the quality of the layout and thus improving the yield of the chip.

[0068] In some embodiments of this application, it can be achieved through Figure 2B The shown S1011 to S1012 implement this. Figure 3 S101, shown below, will be explained in conjunction with each step.

[0069] S1011, identify the MOS structure in the layout.

[0070] In the embodiment of the present application, the detection device can first identify the MOS structure in the layout. The MOS structure includes the PMOS structure and the NMOS structure.

[0071] S1012, determine the multi-finger structure in the MOS structure.

[0072] In the embodiment of the present application, after identifying the MOS structure, the detection device can determine the multi-finger structure in the MOS structure.

[0073] In some embodiments of the present application, S1013-S1014 can be used to achieve Figure 3 S101 shown will be described in combination with each step.

[0074] S1013, determine the target layer pattern in the layout based on the preset identification layer information.

[0075] In the embodiment of the present application, the detection device can first determine the target layer pattern in the layout based on the preset identification layer information, wherein the preset identification layer information is obtained by respectively mapping different digital identification layers to the layer of the process flow sheet, and the target layer pattern contains all design patterns of the layer to be detected.

[0076] S1014, identify the MOS structure in the target layer pattern through Boolean operation.

[0077] In the embodiment of the present application, the detection device can identify the MOS structure in the target layer pattern through Boolean operation.

[0078] It can be understood that, according to the preset identification layer information, the target layer pattern of the layer to be detected is first determined, and then the MOS structure is identified in the target layer pattern. In this way, the identification range can be reduced, and the identification efficiency can be improved.

[0079] In some embodiments of the present application, S1013-S1014 can be used to achieve Figure 11 S201-S203 shown can be used to achieve S1014 in the above-mentioned embodiments, which will be described in combination with each step.

[0080] S201, identify the active region in the target layer pattern.

[0081] In the embodiment of the present application, referring to Figure 2A The detection device can first identify the active region 501 in the target layer pattern.

[0082] S202, determine the target active region in the active region; the target active region intersects with at least one gate structure.

[0083] In the embodiments of the present application, continuing to refer to Figure 2B , the detection device can screen out the target active region 502 intersecting with the at least one gate structure 503 in the active region 501 after identifying the active region 501, wherein the material of the gate structure is generally polysilicon.

[0084] S203, removing the guard ring and the diode structure in the target active region, so as to obtain the MOS structure.

[0085] In the embodiments of the present application, continuing to refer to Figure 2A , the detection device can remove the guard ring and the diode structure in the target active region after determining the target active region 502, so as to obtain the PMOS structure 504 and the NMOS structure 505.

[0086] It should be noted that Figure 2B The layout characteristic of the P-type substrate is shown, the PMOS structure 504 encloses the P-type implantation region 506 and the N-well region 507, and the NMOS structure 505 encloses the N-type implantation region 508. If the layout characteristic is an N-type substrate, the PMOS structure encloses the P-type implantation region, and the NMOS structure encloses the N-type implantation region and the P-well region.

[0087] It can be understood that according to the characteristics of the MOS structure in the layout, the MOS structure is gradually identified by using Boolean operation, so that the problems of low efficiency and omission caused by manual searching are avoided, automatic identification and confirmation are realized, and the efficiency and accuracy are improved.

[0088] In some embodiments of the present application, the S1013-S1014 shown can be used to realize Figure 12 The S1012 shown will be described in combination with each step. Figure 12 The S1012 shown will be described in combination with each step.

[0089] S1013, calculating the number of side-by-side gate structures in the MOS structure; the side-by-side gate structures are arranged in parallel in the layout.

[0090] In the embodiments of the present application, the detection device can calculate the number of side-by-side gate structures in the MOS structure after identifying the MOS structure, so as to determine the multi-finger structure, wherein the side-by-side gate structures are arranged in parallel in the layout.

[0091] S1014, for the MOS structure, if the number of side-by-side gate structures thereof is greater than or equal to 2, it is determined that the MOS structure is a multi-finger structure.

[0092] In the embodiments of the present application, for any MOS structure, if the number of side-by-side gate structures thereof is greater than or equal to 2, the detection device can determine that the MOS structure is a multi-finger structure. For example Figure 4 , Figure 13and Figure 13 The example, Figure 14 The MOS structure in the image has only one gate structure, so it will not be classified as a multi-finger structure. Figure 14 The MOS structure in the image has two side-by-side gate structures. ​ The MOS structure in the image has three side-by-side gate structures, so all of them are classified as multi-finger structures.

[0093] In some embodiments of this application, it can be achieved through ​ The shown S301 to S302 implement this. ​ S102, shown below, will be explained in conjunction with each step.

[0094] S301. Based on the connection characteristics, determine the upper multi-finger metal wire in the multi-finger structure; the connection characteristics include: the upper multi-finger metal wire is electrically connected to the upper source and drain terminals, and the upper connecting hole is located above the upper multi-finger metal wire.

[0095] In the embodiments of this application, such as ​ and ​ As shown in the example, the upper multi-finger metal wire 20 in the multi-finger structure is electrically connected to the upper source and drain terminals 101, 102 and 103, and the upper connecting holes 301, 302, 303 and 304 are located above the upper multi-finger metal wire 20. The detection device can determine the upper multi-finger metal wire 20 in the multi-finger structure based on these connection characteristics.

[0096] S302. Based on the multi-finger metal wires connected above, calculate the number of connected holes and the number of source and drain terminals connected above through Boolean operations.

[0097] In this embodiment of the application, after the detection device identifies the multi-finger metal wire, it can calculate the number of upper connecting holes located above the multi-finger metal wire and store it in count1; then, through Boolean operations, it can calculate the number of upper source / drain terminals intersecting the multi-finger metal wire and store it in count2. ​ and ​ For example, ​ The number of upper and middle connecting holes 301 is 1, and the number of upper source and drain terminals 101, 102 and 103 is 3; ​ The number of upper and middle connecting holes 302, 303 and 304 is 3, and the number of upper source and drain terminals 101, 102 and 103 is 3.

[0098] Understandably, by comparing the number of source / drain terminals and the number of connecting holes on the upper part of the multi-finger structure based on its physical characteristics and connection relationships, unqualified multi-finger structures can be quickly identified, thus improving detection efficiency.

[0099] In some embodiments of this application, ​The S103 shown further includes S104, which will be described in combination with each step.

[0100] S104, display the unqualified multi-finger structure in the layout.

[0101] In the embodiments of the present application, after the detection device determines the unqualified multi-finger structure, the unqualified multi-finger structure can be displayed in the layout. For example, all unqualified multi-finger structures are highlighted in the layout at the same time; or the information of all unqualified multi-finger structures is recorded as a list, and after receiving the clicking operation of the designer on the list, the corresponding unqualified multi-finger structure is highlighted in the layout.

[0102] It can be understood that after the unqualified multi-finger structure is confirmed, the unqualified multi-finger structure is displayed in the layout, so that the designer can conveniently view the unqualified multi-finger structure in the layout, and the human-computer interaction performance is improved.

[0103] In some embodiments of the present application, ​ The S103 shown further includes S105, which will be described in combination with each step.

[0104] S105, correct the unqualified multi-finger structure to a qualified multi-finger structure.

[0105] In the embodiments of the present application, after the detection device determines the unqualified multi-finger structure, the unqualified multi-finger structure can be corrected to a qualified multi-finger structure.

[0106] In some embodiments of the present application, the upper multi-finger metal line includes at least one source-drain connection line, and the source-drain connection line is electrically connected to the upper source-drain one by one. ​ The S401-S402 shown realize the S105 in the above-mentioned embodiments, which will be described in combination with each step.

[0107] S401, for the unqualified multi-finger structure, if no upper connection via hole is set on any source-drain connection line, a newly set via hole is added on the source-drain connection line.

[0108] In the embodiments of the present application, after the detection device determines the unqualified multi-finger structure, the detection device can determine whether the upper connection via hole is set on the source-drain connection line of the unqualified multi-finger structure. If no upper connection via hole is set on any source-drain connection line, the detection device can add a newly set via hole on the source-drain connection line.

[0109] S402, extend the upper metal line to connect all newly set via holes, so as to obtain a qualified multi-finger structure.

[0110] In the embodiments of the present application, the detection device can extend the upper metal line to connect all the newly added through holes after the newly added through holes are added, so as to obtain a qualified multi-finger structure. Referring to ​ and ​ , the detection device can add two newly added through holes on the source-drain end connection line 20 in ​ , and extend the upper metal line 401 to connect all the newly added through holes, so as to obtain a similar qualified multi-finger structure as in ​ .

[0111] It can be understood that, for the design defect of too few upper connection through holes existing in the unqualified multi-finger structure, the upper connection through holes are added and the upper metal line is extended to be connected, so that the number of the upper connection through holes is greater than or equal to the number of the upper source-drain ends, thereby the design defect is corrected in a targeted manner, the quality of the layout is improved, and the yield of the product is improved.

[0112] ​ is an optional flowchart of the integrated circuit layout detection method provided by the embodiments of the present application, which will be described in combination with the steps shown in ​ .

[0113] S501, based on the existing layout data, the regions of PMOS and NMOS are checked out.

[0114] In the embodiments of the present application, the detection device can identify the regions of PMOS and NMOS according to layer.

[0115] In the embodiments of the present application, the detection device can first map different digital identification layers to the layer of the process flow separately. Then, using the EDA software identification command, Boolean operation is used for compilation: first, the Active region is found out; then, the part of the Active region that is affected by the Poly is filtered out and stored as A; the part of A that is a guard ring and a diode is filtered out, and the remaining part is the region of PMOS and NMOS. As shown in ​ , the part of A surrounded by the N well 507 and the P type implantation region 506 is PMOS, and the part of A surrounded by the N type implantation region 508 is NMOS.

[0116] S502, the multi-finger structure with the number of fingers greater than 2 in the PMOS and NMOS is checked out, and the number of the upper connection source-drain ends and the corresponding number of the upper connection through holes are determined.

[0117] In the embodiments of the present application, after the PMOS and NMOS are checked out, the detection device can check out the multi-finger structure with the number of fingers greater than or equal to 2 to filter out the case with the number of fingers less than 2. The detection device can select the case with the number of fingers greater than 2 to save in the system for subsequent operation.

[0118] Then, the detecting device can find the source-drain connection line connected with the Active upper source-drain end, and then determine the number of the upper connection via connected with the source-drain connection line and the upper metal line, and store the number of the upper connection via as count1. Then, the number of the intersection of the source-drain connection line and the Active upper source-drain end is calculated by Boolean operation, and recorded as count2.

[0119] It should be noted that the upper source-drain end and the upper multi-finger metal line also need to be connected by a via, however, these vias are the vias of the next layer, which are generally designed in the parameter cell (Pcell) and do not need to be manually added by the layout designer, but only need to be given specific parameters of the Pcell to obtain.

[0120] S503, if it is determined that the number of the upper connection via is less than the number of the source-drain end, the corresponding MOS region is located.

[0121] In the embodiment of the application, the detecting device can compare the variables count1 and count2 stored in the system, and if the count1 of a multi-finger structure is less than the count2, the multi-finger structure will be located.

[0122] S504, receiving the editing and adding of the engineer.

[0123] In the embodiment of the application, after the detecting device locates the unqualified multi-finger structure, the engineer can be reminded to modify and receive the editing and adding of the engineer. The engineer can add the missing upper connection via in the unqualified multi-finger structure to modify the unqualified multi-finger structure to be qualified.

[0124] It can be understood that the application can help the layout engineer to quickly locate the unqualified multi-finger structure that does not meet the reliability check connection. In this way, when the via is missed due to negligence during the design process, it can be checked out in time for modification, thereby greatly improving the quality of the layout.

[0125] ​ An optional structural schematic diagram of the integrated circuit layout detecting device provided in the embodiment of the application is provided. As shown in ​ The embodiment of the application further provides an integrated circuit layout detecting device 800, which comprises a determination unit 804, a calculation unit 805 and a determination unit 806, wherein:

[0126] The determination unit 804 is used to determine a multi-finger structure in a layout; the multi-finger structure comprises at least one upper source-drain end and at least one upper connection via; the upper source-drain end is electrically connected with an upper metal line through the upper connection via;

[0127] The computing unit 805 is configured to calculate the number of the upper-connected source-drain ends and the number of the upper-connected vias.

[0128] The determining unit 806 is configured to determine, for the multi-finger structure, that the multi-finger structure is an unqualified multi-finger structure if the number of the upper-connected source-drain ends is greater than the number of the upper-connected vias.

[0129] In some embodiments of the present application, the determining unit 804 is further configured to identify the MOS structure in the layout, and determine the multi-finger structure in the MOS structure.

[0130] In some embodiments of the present application, the determining unit 804 is further configured to determine the target layer pattern in the layout based on preset identification layer information, and identify the MOS structure in the target layer pattern through Boolean operation.

[0131] In some embodiments of the present application, the determining unit 804 is further configured to identify the active region in the target layer pattern, and determine a target active region in the active region, wherein the target active region intersects with at least one gate structure, and remove the protection ring and the diode structure in the target active region, thereby obtaining the MOS structure.

[0132] In some embodiments of the present application, if the layout represents a P-type substrate, the PMOS structure encloses the P-type implant region and the N-well region outside, and the NMOS structure encloses the N-type implant region outside.

[0133] In some embodiments of the present application, the computing unit 805 is further configured to calculate the number of the side-by-side gate structures in the MOS structure, wherein the side-by-side gate structures are arranged in parallel in the layout.

[0134] The determining unit 806 is further configured to determine, for the MOS structure, that the MOS structure is a multi-finger structure if the number of the side-by-side gate structures is greater than or equal to 2.

[0135] In some embodiments of the present application, the determining unit 804 is further configured to determine, based on connection characteristics, the upper-connected multi-finger metal line in the multi-finger structure, wherein the connection characteristics include that the upper-connected multi-finger metal line is electrically connected to the upper-connected source-drain end, and the upper-connected via is located above the upper-connected multi-finger metal line.

[0136] The computing unit 805 is further configured to calculate, based on the upper-connected multi-finger metal line, the number of the upper-connected vias and the number of the upper-connected source-drain ends through Boolean operation.

[0137] In some embodiments of the present application, the integrated circuit layout detection apparatus 800 further includes a display unit 807, wherein:

[0138] The display unit 807 is configured to display the unqualified multi-finger structure in the layout.

[0139] In some embodiments of the present application, the integrated circuit layout detection apparatus 800 further comprises a correction unit 808, wherein:

[0140] The correction unit 808 is configured to correct the unqualified multi-finger structure into a qualified multi-finger structure.

[0141] In some embodiments of the present application, the upper connection multi-finger metal line comprises at least one source-drain connection line, and the source-drain connection line is electrically connected to the upper connection source-drain one by one; the correction unit 808 is further configured to, for the unqualified multi-finger structure, if no upper connection via hole is arranged on any source-drain connection line, add a new via hole on the source-drain connection line; and extend the upper layer metal line to connect all the new via holes, so as to obtain a qualified multi-finger structure.

[0142] It should be noted that, ​ An optional structural schematic diagram of the integrated circuit layout detection apparatus provided by the embodiments of the present application is shown in FIG. 8, which shows that the hardware entities of the integrated circuit layout detection apparatus 800 comprise a processor 801, a communication interface 802 and a memory 803, wherein: ​

[0143] The processor 801 generally controls the overall operation of the integrated circuit layout detection apparatus 800.

[0144] The communication interface 802 can enable the integrated circuit layout detection apparatus 800 to communicate with other apparatuses or devices through a network.

[0145] The memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed by the processor 801 and modules in the integrated circuit layout detection apparatus 800 (for example, image data, audio data, voice communication data and video communication data) or data that has been processed, which can be realized by a FLASH or a Random Access Memory (RAM).

[0146] ​It should be noted that, in the embodiments of the present application, if the method for executing the timing task is implemented in the form of a software function module and is sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a plurality of instructions for causing the integrated circuit layout detection device 800 (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read Only Memory, ROM), a magnetic disk or an optical disk, and various program code storage media. Thus, the embodiments of the present application are not limited to any specific hardware and software combination.

[0147] Correspondingly, the embodiments of the present application provide a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the method corresponding to the integrated circuit layout detection device are implemented.

[0148] It should be noted that: the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects to the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0149] It should be noted that, in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0150] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0151] The units described as separate components above can or can not be physically separate, and the components displayed as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0152] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional units.

[0153] The above is only an embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for inspecting integrated circuit layouts, characterized in that, The method includes: In the layout, a multi-finger structure is defined; the multi-finger structure includes: at least one upper source / drain terminal and at least one upper connecting hole; the upper source / drain terminal is electrically connected to the upper metal wire through the upper connecting hole; Calculate the number of the upper source / drain terminals and the number of the upper connecting holes; For the multi-finger structure, if the number of source and drain terminals on it is greater than the number of connecting holes on it, then the multi-finger structure is determined to be a defective multi-finger structure. The calculation of the number of upper source / drain terminals and the number of upper connecting holes includes: Based on the connection characteristics, the upper connecting multi-finger metal wire in the multi-finger structure is determined; the connection characteristics include: the upper connecting multi-finger metal wire is electrically connected to the upper connecting source and drain terminals, and the upper connecting hole is located above the upper connecting multi-finger metal wire. Based on the aforementioned multi-fingered metal wires, the number of the aforementioned upper connecting holes and the number of the aforementioned upper source / drain terminals are calculated using Boolean operations.

2. The integrated circuit layout inspection method according to claim 1, characterized in that, In the layout, determining the multi-finger structure includes: In the layout, identify the MOS structure; In the MOS structure, the multi-finger structure is defined.

3. The integrated circuit layout inspection method according to claim 2, characterized in that, The process of identifying the MOS structure in the layout includes: Based on the preset identification layer information, the target layer pattern is determined in the layout; The MOS structure is identified in the target layer pattern using Boolean operations.

4. The integrated circuit layout inspection method according to claim 3, characterized in that, The step of identifying the MOS structure in the target layer pattern through Boolean operations includes: Identify active regions in the target layer pattern; A target active region is determined within the active region; the target active region intersects with at least one gate structure; The guard ring and diode structure in the target active region are removed to obtain the MOS structure.

5. The integrated circuit layout inspection method according to claim 4, characterized in that, The MOS structure includes: PMOS structure and NMOS structure; If the layout represents a P-type substrate, then the PMOS structure surrounds the P-type injection region and the N-well region, and the NMOS structure surrounds the N-type injection region.

6. The integrated circuit layout inspection method according to claim 2, characterized in that, In the MOS structure, determining the multi-finger structure includes: Calculate the number of side-by-side gate structures in the MOS structure; the side-by-side gate structures are arranged in parallel in the layout; For the MOS structure, if the number of its side-by-side gate structures is greater than or equal to 2, then the MOS structure is determined to be a multi-finger structure.

7. The integrated circuit layout inspection method according to claim 1, characterized in that, After determining that the multi-finger structure is a defective multi-finger structure if the number of source / drain terminals on it is greater than the number of connecting holes on it, the method further includes: The defective multi-fingered structure is shown in the layout.

8. The integrated circuit layout inspection method according to claim 1, characterized in that, After determining that the multi-finger structure is a defective multi-finger structure if the number of source / drain terminals on it is greater than the number of connecting holes on it, the method further includes: The defective multi-fingered structure is corrected into a qualified multi-fingered structure.

9. The integrated circuit layout inspection method according to claim 8, characterized in that, The upper multi-finger metal wire includes: at least one source-drain terminal connection line; the source-drain terminal connection line is electrically connected to the upper source-drain terminal in a one-to-one correspondence; The step of correcting the defective multi-fingered structure into a qualified multi-fingered structure includes: For the aforementioned non-conforming multi-finger structure, if no upper through hole is provided on any source-drain connection line, a new through hole is added to that source-drain connection line. Extend the upper metal wire to connect all the newly created through holes, thereby obtaining the qualified multi-finger structure.

10. An integrated circuit layout inspection device, characterized in that, include: Define the unit, used to define the multi-finger structure in the layout; The multi-finger structure includes: at least one upper source / drain terminal and at least one upper connecting hole; the upper source / drain terminal is electrically connected to the upper metal wire through the upper connecting hole; A calculation unit is used to calculate the number of the upper source / drain terminals and the number of the upper connecting holes; The determination unit is used to determine that the multi-finger structure is a defective multi-finger structure if the number of source and drain terminals on it is greater than the number of connecting holes on it. The calculation of the number of upper source / drain terminals and the number of upper connecting holes includes: Based on the connection characteristics, the upper connecting multi-finger metal wire in the multi-finger structure is determined; the connection characteristics include: the upper connecting multi-finger metal wire is electrically connected to the upper connecting source and drain terminals, and the upper connecting hole is located above the upper connecting multi-finger metal wire. Based on the aforementioned multi-fingered metal wires, the number of the aforementioned upper connecting holes and the number of the aforementioned upper source / drain terminals are calculated using Boolean operations.

11. The integrated circuit layout inspection device according to claim 10, characterized in that, The device further includes: A display unit is used to display the defective multi-finger structure in the layout.

12. The integrated circuit layout inspection device according to claim 10, characterized in that, The device further includes: The correction unit is used to correct the defective multi-finger structure into a qualified multi-finger structure.

13. An integrated circuit layout inspection device, characterized in that, include: Memory, used to store executable instructions; A processor, when executing executable instructions stored in the memory, implements the method according to any one of claims 1 to 9.

14. A storage medium, characterized in that, It stores executable instructions for causing a processor to execute, thereby implementing the method of any one of claims 1 to 9.

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