A reading system and method

Abstract

The application provides a reading system and method. A register unit stores a fault address of a faulty storage unit. A comparison unit compares the fault address of the faulty storage unit stored in the register unit with a read operation address generated by a controller, generates a comparison result, and when the comparison result indicates that the read operation address is consistent with the fault address, sends the comparison result to a redundant address generator, so that the redundant address generator generates a redundant address and sends the redundant address to the controller, so that the controller reads a corresponding storage unit according to the redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the storage unit corresponding to the read operation address can be read, and when the storage unit corresponding to the read operation address cannot be read, the read operation address is replaced by the redundant address, so that the controller can obtain data in time and improve the reading efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a reading system and method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an internal memory that directly exchanges data with the CPU, allowing data to be read and written at any time.

[0003] DRAM has millions of memory cells. When a memory cell fails, the data in that cell cannot be read in a timely manner, affecting read efficiency. Summary of the Invention

[0004] This application provides a reading system and method to solve the problem that the storage unit cannot be read in a timely manner when the storage unit fails.

[0005] According to some embodiments, a first aspect of this disclosure provides a reading system, comprising:

[0006] A register is used to store the fault address of a memory cell that has failed.

[0007] A comparison unit, connected to the register unit and the controller, is used to compare the fault address stored in the register unit with the read operation address sent by the controller and generate a comparison result.

[0008] A redundant address generator, connected to the comparison unit, is used to generate a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller can read the corresponding memory unit according to the redundant address.

[0009] Optionally, the comparison unit is further configured to output the read operation address when the comparison result indicates that the read operation address and the fault address are inconsistent, so that the controller reads the storage unit corresponding to the read operation address.

[0010] Optionally, the register unit includes multiple registers, and the comparison unit includes multiple comparators, with each register corresponding to one of the comparators;

[0011] Each of the registers is specifically used to store the fault address of a memory cell that has failed;

[0012] Each of the comparators is specifically used to compare the read operation address with the fault address stored in the corresponding register.

[0013] Optionally, the redundant address generator is specifically used to generate a redundant address based on the address corresponding to the comparator that generated the comparison result when the comparison result indicates that the read operation address and the fault address are consistent.

[0014] Optionally, the redundant address generator is specifically used to generate a redundant address and a matching instruction when the comparison result indicates that the read operation address and the fault address are consistent.

[0015] Optionally, the system further includes:

[0016] A data selector, connected to the redundant address generator and the controller, is used to send the redundant address to the controller when it receives a redundant address from the redundant address generator.

[0017] Optionally, the data selector is specifically used to send the redundant address to the controller when it receives the redundant address and matching instruction sent by the redundant address generator.

[0018] Optionally, the system further includes:

[0019] A verification unit is used to verify the write data written to each storage unit and the read data read from each storage unit.

[0020] Optionally, the verification unit includes a first verifier, which is used to perform a first verification on the write data written to each storage unit.

[0021] Optionally, the system further includes:

[0022] A first latch connected to the first verifier is used to store the written data and, upon receiving a verification success signal sent by the first verifier, writes the written data into the corresponding storage unit.

[0023] Optionally, the first verifier is specifically used to issue a first warning signal after the first verification of the written data fails.

[0024] Optionally, the verification unit includes a second verifier, which is used to perform a second verification on the read data read from each storage unit.

[0025] Optionally, the system further includes:

[0026] A second latch connected to the second verifier is used to store the read data read from each storage unit and output the read data after receiving a verification success signal from the second verifier.

[0027] Optionally, the second verifier is specifically used to issue a second warning signal after a second verification of the read data fails.

[0028] According to some embodiments, a second aspect of this disclosure provides a reading method, the method being applied to a comparison unit connected to a register unit, the comparison unit also connected to a redundant address generator, and the comparison unit further connected to a controller, the method comprising:

[0029] The fault address stored in the register unit is compared with the read operation address sent by the controller, and a comparison result is generated;

[0030] If the comparison result indicates that the read operation address and the fault address are consistent, the redundant address generator is activated to generate a redundant address, so that the controller reads the corresponding memory unit according to the redundant address.

[0031] Optionally, the method further includes:

[0032] When the comparison result indicates that the read operation address and the fault address are inconsistent, the read operation address is output so that the controller can read the corresponding storage unit according to the read operation address.

[0033] The reading system provided in this application includes: a register unit, a comparison unit connected to the register unit and a controller, and a redundant address generator connected to the comparison unit. The comparison unit compares the fault address of a faulty memory cell stored in the register unit with the read operation address generated by the controller, generates a comparison result, and when the comparison result indicates that the read operation address and the fault address match, sends the comparison result to the redundant address generator. The redundant address generator then generates a redundant address and sends it to the controller, enabling the controller to read the corresponding memory cell based on the redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the memory cell corresponding to the read operation address can be read. When the memory cell corresponding to the read operation address cannot be read, the redundant address replaces the read operation address, allowing the controller to acquire data promptly and improving reading efficiency. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a reading system provided in one embodiment of this application;

[0035] Figure 2 This is a schematic diagram of the structure of a reading system provided in one embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the structure of a reading system provided in one embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the structure of a reading system provided in one embodiment of this application;

[0038] Figure 5 This is a flowchart of a reading method provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] Random Access Memory (RAM) is an internal memory that directly exchanges data with the CPU. Data can be written to or read from any specified memory location. It is volatile, meaning that stored data is lost when power is off. Based on the operating principle of its memory cells, RAM is divided into Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM).

[0041] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM consists of multiple storage cells, each representing a binary bit. Each binary bit comprises a transistor and a capacitor. During a read operation, the bitline (BL) is first charged to half the operating voltage. The transistor is then turned on, causing a charge sharing phenomenon between the bitline and the capacitor. If the stored value is 1, the bitline voltage is raised above half the operating voltage; if the stored value is 0, the bitline voltage is pulled down below half the operating voltage. The stored value (1 or 0) can then be determined based on the bitline voltage. During a write operation, the transistor is turned on. To write a 1, the bitline voltage is raised to the operating voltage, causing the capacitor to store the operating voltage. To write a 0, the bitline voltage is lowered to zero, leaving the capacitor empty of charge.

[0042] Typically, before performing a read operation on a memory cell in Dynamic Random Access Memory (DRAM), a read verification is performed to determine if the cell is safe for reading. Similarly, before performing a write operation on a memory cell in DRAM, a write verification is performed to determine if the cell is safe for writing. For example, DDR4-SDRAM (Double Data Rate Synchronous Dynamic Random-access Memory) supports write data verification, while DDR5-SDRAM supports both write and read data verification.

[0043] However, existing methods, after determining that a storage unit cannot be read during read verification, lack an effective way to repair the storage unit, resulting in the inability to read the storage unit in a timely manner and affecting read efficiency.

[0044] To address this, this application proposes a reading system, comprising: a register unit, a comparison unit connected to the register unit and a controller, and a redundant address generator connected to the comparison unit. The register unit stores the fault address of a faulty memory cell. The comparison unit compares the fault address of the faulty memory cell stored in the register unit with the read operation address generated by the controller, generates a comparison result, and sends the comparison result to the redundant address generator when the comparison result indicates that the read operation address and the fault address match. The redundant address generator then generates a redundant address and sends it to the controller, enabling the controller to read the corresponding memory cell based on the redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the memory cell corresponding to the read operation address can be read. When the memory cell corresponding to the read operation address cannot be read, the redundant address replaces the read operation address, allowing the controller to acquire data promptly and improving reading efficiency.

[0045] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0046] Figure 1 A schematic diagram of a reading system according to an embodiment of this application is shown. The system of this embodiment includes:

[0047] Register unit 101 is used to store the fault address of the faulty memory unit;

[0048] The comparison unit 102, which is connected to the register unit 101 and the controller 103, is used to compare the fault address stored in the register unit 101 with the read operation address sent by the controller 103 and generate a comparison result.

[0049] A redundant address generator 104, connected to a comparison unit 102, is used to generate a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller 103 can read the corresponding memory unit according to the redundant address.

[0050] A memory consists of multiple storage cells, each with an address consisting of a row address (word line address) and a column address (bit line address). The row or column address is an integer code. For example, if a memory has 128 storage cells, the row addresses would be 0-127, and the column addresses would also be 0-127.

[0051] Register (or fuse, ROF) 101 stores damage addresses. A damage address can be understood as the address or row address of a memory cell that failed a read verification. Since the memory contains multiple memory cells, each of which can be read and verified, there may be multiple memory cells that failed verification, meaning multiple damage addresses need to be stored in register 101. Therefore, register 101 can include multiple registers, each storing one damage address. Each register includes multiple flip-flops with storage functions. One flip-flop stores one bit of binary code; a register storing n bits of binary code requires n flip-flops.

[0052] The comparison unit 102 is connected to the register unit 101 and the controller 103. It compares the read operation address sent by the controller 103 with the fault address stored in the register unit 101 and generates a comparison result. When the controller 103 needs to read a memory cell, it sends the address of that memory cell, i.e., the read operation address, to the comparison unit 102. The comparison unit 102 compares the read operation address sent by the controller 103 with the fault address stored in the register unit 101. If the fault address is the address of a memory cell, the comparison unit 102 compares the read operation address generated by the controller 103 with the fault address stored in the register unit 101. If the fault address is the row address of a memory cell, the comparison unit 102 compares the row address of the read operation address generated by the controller 103 with the fault address stored in the register unit 101. If they match, it indicates that the register unit 101 stores the read operation address, meaning that a read operation cannot be performed on the memory cell corresponding to that read operation address. If there is a discrepancy, it indicates that the read operation address is not stored in register 101, meaning that the memory cell corresponding to the read operation address can be read.

[0053] It is understandable that if register 101 stores the read operation address, it indicates that the memory cell corresponding to the read operation address was verified and the verification failed before comparing the read operation address with the fault address. If register 101 does not store the read operation address, it indicates that the memory cell corresponding to the read operation address was verified and the verification was successful before comparing the read operation address with the fault address, or that the memory cell corresponding to the read operation address was not verified.

[0054] In some embodiments of this disclosure, after comparing the read operation address with the fault address, if the read operation address and the fault address are inconsistent, a read verification can be performed on the storage unit corresponding to the read operation address. If the read verification is successful, the storage unit corresponding to the read operation address is read directly. If the verification fails, it indicates that the storage unit corresponding to this read operation address has not been verified before this verification, and the read operation address can be stored in the register unit 101.

[0055] Comparison unit 102 compares the read operation address and the fault address and generates a comparison result. If the comparison result indicates that the read operation address and the fault address match, comparison unit 102 sends the comparison result to redundancy address generator 104, causing redundancy address generator 104 to generate a redundant address based on the comparison result. This allows controller 103 to read the memory unit corresponding to the redundant address, thereby enabling controller 103 to promptly acquire the faulty memory unit and improve read efficiency. If the comparison result indicates that the read operation address and the fault address do not match, comparison unit 102 outputs the read operation address, causing controller 103 to read the memory unit corresponding to the read operation address.

[0056] In some embodiments of this disclosure, when the comparison result indicates that the read operation address and the fault address are inconsistent, the verification unit is used to perform a read verification on the read operation address. After the read verification fails, a redundant address generation instruction is sent to the redundant address generator 104, so that the redundant address generator 104 generates a redundant address according to the redundant address generation instruction.

[0057] In some embodiments of this disclosure, the comparison unit 102 may include multiple comparators, each comparator corresponding to a register, and each register storing a fault address. Each comparator compares the read operation address sent by the controller 103 with the fault address in the corresponding register. Each comparator can generate a comparison result, which may indicate that the read operation address and the fault address are the same, or that the read operation address and the fault address are different. If the comparison result of one comparator indicates that the read operation address and the fault address are the same, it means that the memory unit corresponding to the read operation address cannot perform a normal read operation. If the comparison result of any comparator indicates that the read operation address and the fault address are different, it means that the memory unit corresponding to the read operation address can perform a read operation.

[0058] For example, refer to Figure 2As shown, the comparison unit 102 includes a first comparator 121, a second comparator 122, a third comparator 123, a fourth comparator 124, a fifth comparator 125, and a sixth comparator 126. The register unit 101 includes a first register 111, a second register 112, a third register 113, a fourth register 114, a fifth register 115, and a sixth register 116. Each of the first register 111, second register 112, third register 113, fourth register 114, fifth register 115, and sixth register 116 stores a fault address. The first comparator 121 corresponds to the first register 111, the second comparator 122 corresponds to the second register 112, the third comparator 123 corresponds to the third register 113, the fourth comparator 124 corresponds to the fourth register 114, the fifth comparator 125 corresponds to the fifth register 115, and the sixth comparator 126 corresponds to the sixth register 116. The first comparator 121 compares the read operation address with the fault address stored in the first register 111 to generate a first comparison result. The second comparator 122 compares the read operation address with the fault address stored in the second register 112 to generate a second comparison result. The third comparator 123 compares the read operation address with the fault address stored in the third register 113 to generate a third comparison result. The fourth comparator 124 compares the read operation address with the fault address stored in the fourth register 114 to generate a fourth comparison result. The fifth comparator 125 compares the read operation address with the fault address stored in the fifth register 115 to generate a fifth comparison result. The sixth comparator 126 compares the read operation address with the fault address stored in the sixth register 116 to generate a sixth comparison result. If any of the six comparison results indicates that the read operation address matches the fault address, it means that the memory cell corresponding to that read operation address cannot be read normally. If all six comparison results indicate that the read operation address does not match the fault address, it means that the memory cell corresponding to that read operation address can be read.

[0059] The redundant address generator 104 is connected to the comparison unit 102 and is used to generate a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller 103 can read the corresponding memory unit according to the redundant address. The redundant address generator 104 can also be used to generate a redundant address after receiving a redundant address generation instruction sent by the verification unit.

[0060] In some embodiments of this disclosure, the redundant address generator 104 can generate a redundant address based on the location of the comparator that generated the comparison result after receiving the comparison result. Each comparator corresponds to one address, and each comparator generates one comparison result. The address corresponding to the comparator whose comparison result shows that the read operation address and the fault address are consistent can be used as the redundant address.

[0061] In some embodiments of this disclosure, the redundant address generator 104 can generate a hit instruction while generating a redundant address, and send the redundant address and the hit instruction to the controller 103. After receiving the hit instruction and the redundant address, the controller 103 reads the storage unit corresponding to the redundant address. The controller 103 can only read the storage unit corresponding to the redundant address after receiving the hit instruction and the redundant address, ensuring the accuracy of the redundant address and thus ensuring the accuracy of data reading.

[0062] In some embodiments of this disclosure, a data selector (multiplexer, MUX) 105 connected to the redundant address generator 104 and the controller 103 is also included, see reference. Figure 3 As shown, the data selector 105 sends a redundant address to the controller 103 upon receiving a redundant address from the redundant address generator 104. The data selector 105 is a device with selection functionality, used for signal switching. For example, it can send either an operation address or a redundant address to the controller 103 during any operation such as active, precharge, read, or write. The operation address refers to the address of the memory cell to be activated, precharged, read, or written. The redundant address is a replacement address for the operation address. When the read operation address is a faulty address, the data selector 105 can automatically generate a redundant address to the controller 103 to improve operational efficiency. The data selector 105 can also send the redundant address to the controller 103 only after receiving the redundant address and a matching instruction, ensuring the accuracy of the read operation address and the redundant address.

[0063] The reading system may also include a verification unit, which verifies the data written to each storage unit and the data read from each storage unit. Verifying the data written to each storage unit ensures the reliability and accuracy of the data written to the storage unit, and verifying the data read from each storage unit ensures the reliability and accuracy of the data read.

[0064] In some embodiments of this disclosure, the verification unit includes a first verifier 201 (check1), as referenced. Figure 4 As shown, the first verifier 201 is used to perform a first verification on the write data written to each storage cell to ensure the accuracy and reliability of the write data written to each storage cell. For example, parity check can be used to verify the write data written to each storage cell.

[0065] Parity checking involves adding a parity bit to each byte. After storing data in a byte, the data stored in its eight bits is fixed. Since each bit has only two states, assuming the stored data is represented by bits 1, 1, 1, 0, 0, 1, 0, 1, adding each bit together (1 + 1 + 1 + 0 + 0 + 1 + 0 + 1) = 5 results in an odd number. For even parity, the parity bit is defined as 1; for odd parity, it is defined as 0.

[0066] For example, if you need to transmit 11001110, the data includes five 1s, and the odd parity bit is 0. When you transmit 110011100 to the receiver, the receiver recalculates the parity. 110011100 still contains five 1s, and the receiver's calculated odd parity bit is still 0, consistent with the sender's result, indicating that no error occurred during the data transmission. Similarly, if you need to transmit 11001110, the data includes five 1s, and the even parity bit is 1. When you transmit 110011100 to the receiver, the receiver recalculates the parity. 110011100 still contains five 1s, and the receiver's calculated even parity bit is still 1, consistent with the sender's result, indicating that no error occurred during the data transmission. For example, if you need to transmit 11101110, the data includes six 1s, and the odd parity bit is 1. When you transmit 11101110 to the receiver, the receiver recalculates the parity. 11101110 still contains six 1s, and the receiver's calculated odd parity bit is 1, consistent with the sender's result, indicating that no error occurred during the data transmission. Similarly, if you need to transmit 11101110, the data includes six 1s, and the even parity bit is 0. When you transmit 11101110 to the receiver, the receiver recalculates the parity. 11101110 still contains six 1s, and the receiver's calculated even parity bit is 0, consistent with the sender's result, indicating that no error occurred during the data transmission.

[0067] In some other embodiments of this disclosure, a first latch 202 (data latch1) connected to the first verifier 201 can be used to store the written data. The first latch 202 acts as a relay station for the written data, that is, before the written data is written to the storage unit, the written data is temporarily stored in the first latch 202. The first verifier 201 performs a first verification on the written data in the first latch 202. If the first verification is successful, a first verification success signal is sent to the first latch 202, so that the first latch 202 writes the written data into the storage unit. If the first verification fails, a first warning signal is issued so that the first latch 202 will not write the written data into the storage unit.

[0068] In some embodiments of this disclosure, the verification unit includes a second verifier 203 (check2), see reference. Figure 4 As shown, the second verifier 203 performs a second verification on the read data read from each storage unit to ensure the accuracy and reliability of the read data read from each storage unit. When performing the second verification on the read data, if the second verification is successful, the read data in the storage unit is read normally; if the second verification fails, the address of the storage unit that failed the second verification is sent to the register unit 101, so that the register unit 101 stores the address of the failed storage unit.

[0069] In some embodiments of this disclosure, after a second verification of a storage unit fails, the fault address needs to be stored in a register. The storage method can be as follows: check if a fault address is stored in the register; if not, store the fault address directly in that register. If a fault address is stored, continue checking the next register until a register without a fault address is detected, and then store the fault address in that register. For example, when register 101 includes multiple registers, after a second verification of a storage unit fails, it is possible to simultaneously check whether each register stores a fault address and store the address of that storage unit in a register without a fault address; alternatively, it is possible to check each register sequentially, and when a register without a fault address is detected, store the fault address in that register.

[0070] In some other embodiments of this disclosure, a second latch (datalatch2) 204 connected to the second verifier 203 can be used to store the read data read from each storage unit. The second latch 204 acts as a relay station for the read data. That is, before normal data reading, the read data is temporarily stored in the second latch 204. After the second verifier 203 performs a second verification on the read data in the second latch 204, if the second verification is successful, the read data of the storage unit is read normally. If the second verification fails, a second warning signal is issued, making it impossible to read data from the second latch 204. At the same time, the address of the storage unit that failed the verification is sent to the register unit 101, so that the register unit 101 stores the address of the storage unit that failed the verification, that is, the fault address.

[0071] The above describes in detail the reading system provided in the embodiments of this application. By comparing the read operation address with the fault address stored in the register, it is determined whether the storage unit corresponding to the read operation address can be read. When the storage unit corresponding to the read operation address cannot be read, the read operation address is replaced with a redundant address, so that the controller can obtain data in a timely manner and improve reading efficiency.

[0072] An embodiment of this application also provides a reading method, see reference. Figure 5 As shown, Figure 5A flowchart of a reading method according to an embodiment of this application is shown. The method of this embodiment uses a comparison unit connected to a register unit, a redundant address generator, and a controller, and may include the following steps:

[0073] S101. Compare the fault address stored in the register with the read operation address sent by the controller, and generate a comparison result.

[0074] After receiving the read operation address sent by the controller, the comparison unit compares the read operation address with the fault address stored in the register unit and generates a comparison result. For example, the comparison unit may include multiple comparators, the register unit includes multiple registers, each register corresponds to one comparator, each register stores a fault address, each comparator can compare the read operation address with the fault address in the corresponding register, and each comparator can generate a comparison result.

[0075] If the comparison result indicates that the read operation address and the fault address are consistent, proceed to step S102; if the comparison result indicates that the read operation address and the fault address are inconsistent, proceed to step S103.

[0076] S102. Activate the redundant address generator to generate a redundant address, so that the controller can read the corresponding storage unit according to the redundant address.

[0077] S103. Output the read operation address so that the controller can read the corresponding memory unit according to the read operation address.

[0078] The reading method provided in this application compares the read operation address with the fault address stored in the register to determine whether the memory unit corresponding to the read operation address can be read. When the memory unit corresponding to the read operation address cannot be read, a redundant address is used to replace the read operation address, so that the controller can obtain data in a timely manner and improve reading efficiency.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A reading system, characterized in that, The system includes: A register is used to store the fault address of a memory cell that has failed. A comparison unit, connected to the register unit and the controller, is used to compare the fault address stored in the register unit with the read operation address sent by the controller and generate a comparison result. A redundant address generator, connected to the comparison unit, is used to generate a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller reads the corresponding memory unit according to the redundant address; A verification unit is used to verify the write data written to each storage unit and the read data read from each storage unit; The verification unit includes a first verifier, which is used to perform a first verification on the write data written to each storage unit; A first latch connected to the first verifier is used to store the written data and, upon receiving a verification success signal sent by the first verifier, writes the written data into the corresponding storage unit.

2. The system according to claim 1, characterized in that, The comparison unit is further configured to output the read operation address when the comparison result indicates that the read operation address and the fault address are inconsistent, so that the controller can read the storage unit corresponding to the read operation address.

3. The system according to claim 1 or 2, characterized in that, The register unit includes multiple registers, and the comparison unit includes multiple comparators, with each register corresponding to one of the comparators; Each of the registers is specifically used to store the fault address of a memory cell that has failed; Each of the comparators is specifically used to compare the read operation address with the fault address stored in the corresponding register.

4. The system according to claim 3, characterized in that, The redundant address generator is specifically used to generate a redundant address based on the address corresponding to the comparator that generated the comparison result when the comparison result indicates that the read operation address and the fault address are consistent.

5. The system according to claim 1, characterized in that, The redundant address generator is specifically used to generate a redundant address and a matching instruction when the comparison result indicates that the read operation address and the fault address are consistent.

6. The system according to claim 5, characterized in that, The system also includes: A data selector, connected to the redundant address generator and the controller, is used to send the redundant address to the controller when it receives a redundant address from the redundant address generator.

7. The system according to claim 6, characterized in that, The data selector is specifically used to send the redundant address to the controller when it receives the redundant address and matching instruction sent by the redundant address generator.

8. The system according to claim 1, characterized in that, The first verifier is specifically used to issue a first warning signal after the first verification of the written data fails.

9. The system according to claim 1, characterized in that, The verification unit includes a second verifier, which is used to perform a second verification on the read data read from each storage unit.

10. The system according to claim 9, characterized in that, The system also includes: A second latch connected to the second verifier is used to store the read data read from each storage unit and output the read data after receiving a verification success signal from the second verifier.

11. The system according to claim 10, characterized in that, The second verifier is specifically used to issue a second warning signal after the second verification of the read data fails.

12. A reading method, characterized in that, The method is applied to the reading system according to any one of claims 1-11, wherein the comparison unit is connected to the register unit, the comparison unit is also connected to the redundant address generator, and the comparison unit is also connected to the controller, and the method includes: The fault address stored in the register unit is compared with the read operation address sent by the controller, and a comparison result is generated; If the comparison result indicates that the read operation address and the fault address are consistent, the redundant address generator is activated to generate a redundant address, so that the controller reads the corresponding memory unit according to the redundant address.

13. The method according to claim 12, characterized in that, The method further includes: When the comparison result indicates that the read operation address and the fault address are inconsistent, the read operation address is output so that the controller can read the corresponding storage unit according to the read operation address.

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