Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor manufacturing, and provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate layer; forming a plurality of mask structures spaced from each other on the substrate layer, the mask structure comprising two first sidewall structures and two second sidewall structures, the two second sidewall structures being respectively located on two opposite sidewalls of the two first sidewall structures, and the second sidewall structure comprising a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the substrate layer; measuring the interval of adjacent mask structures and the interval of the two second sidewall structures for comparison; etching the substrate layer to form a first opening and a second opening, the second opening being located between the adjacent mask structures, and the first opening being located between the two second sidewall structures in the mask structure; and wherein according to the comparison result, the etching selectivity ratio of the first sidewall structure relative to the second sidewall structure in the etching process is controlled to ensure the consistency of the feature size of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and particularly, to a manufacturing method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the increasing integration of chips, the requirements for the integration and functions of semiconductor structures are increasing, which makes the critical dimension (CD) of the semiconductor structure continuously shrink, increases the process difficulty of subsequent semiconductor structures, and improves the process complexity. The pitch doubling process is a process used to control the CD size, and structures with smaller pitches than the minimum pitch and / or desired pitch realized by using a photolithography device can be formed through the process.

[0003] However, in the related pitch doubling process, the consistency of the feature size of the formed semiconductor structure is difficult to control, and the corresponding semiconductor structure cannot be formed according to specific requirements, so the related technology has defects and needs to be improved and developed. SUMMARY

[0004] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and the semiconductor structure, aiming to ensure the consistency of the feature size of the formed semiconductor structure.

[0005] According to some embodiments of the present disclosure, in one aspect, a manufacturing method of a semiconductor structure is provided, including: providing a substrate layer; forming a plurality of mask structures spaced from each other on the substrate layer, each mask structure of the plurality of mask structures including two first sidewall structures spaced from each other and two second sidewall structures spaced from each other, the two second sidewall structures being respectively located on two opposite sidewalls of the two first sidewall structures, the second sidewall structure including a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the substrate layer; measuring the pitch of adjacent mask structures and the pitch of two second sidewall structures in the mask structure for comparison; etching the substrate layer to form a first opening and a second opening, the second opening being located between adjacent mask structures, and the first opening being located between two second sidewall structures in the mask structure, wherein according to the comparison result, the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process is controlled.

[0006] In some embodiments, the step of controlling the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process according to the comparison result comprises: when the spacing between adjacent mask structures is less than the spacing between two second sidewall structures within the mask structure, controlling the etching process to have a greater etching rate on the first sidewall structure than on the second sidewall layer; when the spacing between adjacent mask structures is greater than the spacing between two second sidewall structures within the mask structure, controlling the etching process to have a smaller etching rate on the first sidewall structure than on the first sidewall layer, and continuing to etch the base layer until the width of the second opening and the width of the first opening are equal, and the depth of the second opening and the depth of the first opening are equal.

[0007] In some embodiments, the step of controlling the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process according to the comparison result comprises: when the spacing between adjacent mask structures is greater than the spacing between two second sidewall structures within the mask structure, controlling the etching process to have a smaller etching rate on the first sidewall structure than on the second sidewall layer; when the spacing between adjacent mask structures is less than the spacing between two second sidewall structures within the mask structure, controlling the etching process to have a greater etching rate on the first sidewall structure than on the first sidewall layer, and continuing to etch the base layer until the width of the second opening and the width of the first opening are equal, and the depth of the second opening and the depth of the first opening are equal.

[0008] In some embodiments, the step of forming a plurality of mask structures spaced apart on the base layer, each mask structure in the plurality of mask structures comprising two first sidewall structures spaced apart and two second sidewall structures spaced apart, the two second sidewall structures being respectively located on two opposite sidewalls of the two first sidewall structures, the second sidewall structure comprising a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the base layer, comprises: forming a plurality of first mandrel structures spaced apart on the base layer; forming a second sidewall structure on both sides of each first mandrel structure in the plurality of first mandrel structures, the second sidewall structure comprising a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the base layer; forming a filling structure in the space between the plurality of first mandrel structures, and removing the plurality of first mandrel structures to form a plurality of second mandrel structures, each second mandrel structure in the plurality of second mandrel structures comprising the filling structure and the second sidewall structure located on both sides of the filling structure; forming a first sidewall structure on both sides of the second mandrel structure, and removing the filling structure.

[0009] In some embodiments, the step of forming a plurality of first mandrel structures spaced apart from each other on the substrate layer comprises: sequentially forming a sacrificial layer and a photoresist layer on the substrate layer; performing a patterning process on the photoresist layer; etching the sacrificial layer with the patterned photoresist layer as a mask to form a plurality of through holes and simultaneously form a plurality of first mandrel structures, each of the plurality of through holes sequentially penetrating the photoresist layer and the sacrificial layer, and each of the plurality of first mandrel structures comprising the sacrificial layer and the photoresist layer sequentially stacked along a thickness direction of the substrate layer.

[0010] In some embodiments, the step of forming a second sidewall structure on both sides of each of the plurality of first mandrel structures, the second sidewall structure comprising a first sidewall layer and a second sidewall layer sequentially stacked along a thickness direction away from the substrate layer, comprises: depositing an initial first sidewall layer on top of and on both sides of the plurality of first mandrel structures and on a bottom of the plurality of through holes; removing the initial first sidewall layer on the bottom of the plurality of through holes and on the top of the plurality of first mandrel structures, leaving a first initial sidewall layer; forming a filling layer in the plurality of through holes, the filling layer covering a side surface of the first initial sidewall layer; etching part of the first initial sidewall layer to form a gap between the plurality of first mandrel structures and the filling layer, leaving a first sidewall layer; forming a second sidewall layer in the gap and removing the filling layer and the patterned photoresist layer.

[0011] In some embodiments, the step of forming a second sidewall structure on both sides of each of the plurality of first mandrel structures, the second sidewall structure comprising a first sidewall layer and a second sidewall layer sequentially stacked along a thickness direction away from the substrate layer, comprises: depositing an initial second sidewall layer in the gap and on the filling layer and the patterned photoresist layer; removing the initial second sidewall layer on the filling layer and the patterned photoresist layer, leaving a second initial sidewall layer; etching part of the second initial sidewall layer until a height of the remaining second initial sidewall layer on the substrate layer is lower than a height of the sacrificial layer on the substrate layer, leaving a second sidewall layer; removing the filling layer and the patterned photoresist layer.

[0012] In some embodiments, the step of forming a filling structure in the space between the plurality of first mandrel structures and removing the plurality of first mandrel structures to form a plurality of second mandrel structures, each of the plurality of second mandrel structures comprising the filling structure and the second sidewall structure on both sides of the filling structure, comprises: forming the filling structure in a gap left after removing part of the second initial sidewall layer and the filling layer, a surface of the filling structure being flush with a surface of the sacrificial layer; removing the sacrificial layer.

[0013] In some embodiments, the material of the first spacer structure comprises amorphous carbon, the material of the first spacer layer comprises silicon nitride, silicon carbon nitride, and boron silicon nitride, and the material of the second spacer layer comprises silicon oxide.

[0014] In some embodiments, a first etching gas is used to control the etching rate of the etching process on the first spacer structure to be greater than that on the second spacer layer, the first etching gas comprising carbon tetrafluoride and / or trifluoromethane, and nitrogen, oxygen, and carbon oxysulfide; a second etching gas is used to control the etching rate of the etching process on the first spacer structure to be less than that on the first spacer layer, the second etching gas comprising carbon tetrafluoride and / or difluoromethane, and carbon oxysulfide, nitrogen, oxygen, and argon.

[0015] In some embodiments, the material of the first spacer structure comprises amorphous carbon, the material of the first spacer layer comprises silicon nitride, silicon carbon nitride, and boron silicon nitride, and the material of the second spacer layer comprises silicon oxide.

[0016] In some embodiments, a second etching gas is used to control the etching rate of the etching process on the first spacer structure to be less than that on the second spacer layer, the second etching gas comprising carbon tetrafluoride and / or difluoromethane, and carbon oxysulfide, nitrogen, oxygen, and argon; a first etching gas is used to control the etching rate of the etching process on the first spacer structure to be greater than that on the first spacer layer, the first etching gas comprising carbon tetrafluoride and / or trifluoromethane, and nitrogen, oxygen, and carbon oxysulfide.

[0017] In some embodiments, the height of the first spacer structure on the base layer is greater than or equal to the height of the second spacer structure on the base layer.

[0018] In some embodiments, the base layer comprises a substrate and a dielectric layer on the substrate, the second opening and the first opening formed by etching pass through the dielectric layer and expose the surface of the substrate; or, the second opening and the first opening formed by etching stay in the dielectric layer.

[0019] According to some embodiments of the present disclosure, the present disclosure further provides a semiconductor structure, comprising: a substrate layer; a plurality of mask structures located on the substrate layer, each mask structure of the plurality of mask structures comprising two first sidewall structures spaced apart from each other and two second sidewall structures spaced apart from each other, the two second sidewall structures being located on opposite sidewalls of the two first sidewall structures respectively, the second sidewall structure comprising a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the substrate layer; wherein the plurality of mask structures are used for an etching process on the substrate layer, and in the etching process, an etching selectivity of the first sidewall structure relative to the second sidewall structure is adjusted according to the second sidewall layer and the first sidewall layer.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] By comparing the interval of adjacent mask structures and the interval of the two second sidewall structures in a mask structure, since the interval of adjacent mask structures, i.e. the interval between the first sidewall structure in one mask structure and the closest first sidewall structure in the adjacent mask structure, directly affects the size of the second opening formed, and the interval of the two second sidewall structures in a mask structure directly affects the size of the first opening, the size relationship between the interval of adjacent mask structures and the interval of the two second sidewall structures in a mask structure can be determined by comparing the results, and the etching selectivity of the first sidewall structure relative to the second sidewall structure is dynamically adjusted in the etching process, so that the interval of the two second sidewall structures in a mask structure is expanded relative to the interval of adjacent mask structures, or the interval of adjacent mask structures is expanded relative to the interval of the two second sidewall structures in a mask structure, so that the size of the first opening and the size of the second opening can be kept consistent after the etching process is completed, thereby ensuring the consistency of the feature size in the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings that are for illustrative purposes only, and not for the purposes of limitation of the embodiments, unless otherwise explicitly stated herein. The drawings in the accompanying drawings are not necessarily to scale, unless otherwise explicitly stated herein. In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some of the embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0023] Figures 1-23 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] As can be seen from the background art, it is difficult to control the consistency of the feature size of the semiconductor structure formed by using the current pitch doubling process to control the CD size, so that the corresponding semiconductor structure cannot be formed as required.

[0025] In the current pitch doubling process, a sacrificial material layer is first deposited on the surface of the base layer, and then photolithography and etching are performed to transfer the pattern on the mask to the sacrificial material layer. The pattern on the sacrificial material layer is also called a mandrel structure. Then, a relatively uniform thin film (referred to as a side wall layer) is deposited on the surface and side surface of the mandrel structure. Then, the deposited side wall layer is etched away. Due to the geometric effect of the side wall of the mandrel structure, the material deposited on both sides of the pattern will remain to form a spacer structure. Then, the mandrel structure is removed, leaving only the spacer structure on the surface of the substrate. The period of the pattern corresponding to the spacer structure is half of the photolithographic pattern, achieving the doubling of the spatial pattern density. Finally, the pattern of the spacer structure is transferred to the base layer.

[0026] Analysis shows that the reason why it is difficult to control the consistency of the feature size of the semiconductor structure formed by using the current pitch doubling process to control the CD size is that the deposition and etching process of the spacer structure causes the line width roughness performance to decrease, so that among the plurality of spacer structures formed on the base layer, the pitch between the two spacer structures located on both sides of the original mandrel structure is not equal to the pitch between one of the two spacer structures and the adjacent other spacer structure. Therefore, after etching the base layer using the plurality of spacer structures as a mask, the consistency of the feature size of the semiconductor structure formed is poor.

[0027] The embodiments of the present disclosure provide a semiconductor structure manufacturing method. By measuring and comparing the pitch of adjacent mask structures and the pitch of two second spacer structures in a mask structure, and determining the size relationship between the pitch of adjacent mask structures and the pitch of two second spacer structures in a mask structure according to the comparison result, the etching selectivity of the first spacer structure relative to the second spacer structure is dynamically adjusted in the etching process, so that the pitch of the two second spacer structures in the mask structure is expanded relative to the pitch of the adjacent mask structures, or the pitch of the adjacent mask structures is expanded relative to the pitch of the two second spacer structures in the mask structure, so that the size of the first opening can be consistent with the size of the second opening after the etching process is completed, thereby ensuring the consistency of the feature size in the semiconductor structure.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are presented in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0029] Figures 1-23 The manufacturing method of the semiconductor structure provided in the embodiments of the present disclosure corresponds to the structure schematic diagram of each step. The following will be specifically described with reference to the drawings.

[0030] Referring to Figure 1 , a substrate layer 100 is provided. As shown in Figure 1 , the substrate layer 100 can include a substrate 101 and a dielectric layer 102, and the dielectric layer 102 is located on the substrate 101. Specifically, the material of the substrate 101 can be a semiconductor material such as silicon, germanium or silicon-on-insulator (SOI). The material of the dielectric layer 102 can be an oxide material, for example, silicon oxide. In an embodiment, the dielectric layer 102 can be formed by oxidizing the substrate 101. In other embodiments, it can also be formed on the substrate 101 by deposition.

[0031] Referring to Figures 2-16 , a plurality of mask structures spaced from each other are formed on the substrate layer 100. As shown in Figure 16 , each of the plurality of mask structures includes two first side wall structures 109' spaced from each other and two second side wall structures 110 spaced from each other, and the two second side wall structures 110 are respectively located on the opposite two side walls of the two first side wall structures 109'. The second side wall structure 110 includes a first side wall layer 105" and a second side wall layer 107" stacked in sequence along the thickness direction away from the substrate layer 100.

[0032] Referring to Figure 3 , Figure 11 , Figure 12 , Figure 13 , Figure 15 and Figure 16 , the step of forming a plurality of mask structures spaced from each other on the substrate layer 100 includes: as shown in Figure 3 , forming a plurality of first mandrel structures spaced from each other on the substrate layer 100; as shown in Figure 11 and Figure 16 , forming a second side wall structure 110 on both sides of each first mandrel structure in the plurality of first mandrel structures, and the second side wall structure 110 includes a first side wall layer 105" and a second side wall layer 107" stacked in sequence along the thickness direction away from the substrate layer 100; as shown in Figure 12The filling structure 108 is formed in the interval of the plurality of first mandrel structures, and the first side wall structure 109 is formed on both sides of the second mandrel structure, as shown in Figure 13 The plurality of first mandrel structures are removed to form a plurality of second mandrel structures, each of the plurality of second mandrel structures comprising the filling structure 108 and the second side wall structure 110 on both sides of the filling structure 108, as shown in Figure 15 The first side wall structure 109' is formed on both sides of the second mandrel structure, as shown in Figure 16 The filling structure 108 is removed, as shown in

[0033] Referring to Figures 2-3 The step of forming the plurality of first mandrel structures spaced from each other on the base layer 100 comprises: sequentially forming the sacrificial layer 103 and the photoresist layer 104 on the base layer 100, as shown in Figure 2 The photoresist layer 104 is patterned, as shown in Figure 3 The sacrificial layer 103 is etched with the patterned photoresist layer 104 as a mask to form the plurality of through holes 10 and the plurality of first mandrel structures at the same time, each of the plurality of through holes 10 sequentially penetrating the photoresist layer 104 and the sacrificial layer 103, and each of the plurality of first mandrel structures comprising the sacrificial layer 103 and the photoresist layer 104 sequentially stacked along the thickness direction of the base layer 100, as shown in

[0034] In the embodiment, the first mandrel structure can be a multi-layer structure as shown in Figure 3 In other embodiments, the first mandrel structure can also be a single-layer structure. The material of the sacrificial layer 103 can be selected from a hard mask material. The material of the sacrificial layer 103 comprises any one of silicon nitride, silicon boron nitride and silicon carbon nitride. The sacrificial layer 103 can be formed on the base layer 100 by deposition. The photoresist layer 104 can be a positive photoresist or a negative photoresist. The photoresist layer 104 can be formed on the sacrificial layer 103 by spin coating. Furthermore, the adhesion between the photoresist 104 and the sacrificial layer 103 can be further enhanced by soft baking.

[0035] Referring to Figures 4-7 and Figure 11 The step of forming the second side wall structure 110 on both sides of each of the plurality of first mandrel structures comprises: depositing an initial first side wall layer 105 on the top and both sides of the plurality of first mandrel structures and the bottom of the plurality of through holes 10, as shown in Figure 4 The initial first side wall layer 105 on the bottom of the plurality of through holes 10 and the top of the plurality of first mandrel structures is removed, and the remaining initial first side wall layer 105 serves as the first initial side wall layer 105', as shown in Figure 5 The initial first side wall layer 105 on the bottom of the plurality of through holes 10 and the top of the plurality of first mandrel structures is removed, and the remaining initial first side wall layer 105 serves as the first initial side wall layer 105', as shown in Figure 6As shown, the filling layer 106 is formed in the plurality of through holes 10, and the filling layer 106 covers the side surface of the first initial side wall layer 105’; as shown, Figure 7 As shown, the first initial side wall layer 105’ is etched to form a gap between the plurality of first mandrel structures and the filling layer 106, and the remaining first initial side wall layer 105’ is used as the first side wall layer 105”; Figure 11 As shown, the second side wall layer 107” is formed in the gap, and the filling layer 106 and the patterned photoresist layer 104 are removed.

[0036] Referring to Figures 8-11 As shown, the second side wall layer 107” is formed in the gap, and the filling layer 106 and the patterned photoresist layer 104 are removed. Figure 8 As shown, the initial second side wall layer 107 is deposited on the gap, the filling layer 106 and the patterned photoresist layer 104; as shown, Figure 9 As shown, the initial second side wall layer 107 is removed on the filling layer 106 and the patterned photoresist layer 104, and the remaining initial second side wall layer 107 is used as the second initial side wall layer 107’; as shown, Figure 10 As shown, the second initial side wall layer 107’ is etched until the height of the remaining second initial side wall layer 107’ on the base layer 100 is lower than the height of the sacrifice layer 103 on the base layer 100, and the remaining second initial side wall layer 107’ is used as the second side wall layer 107”; Figure 11 As shown, the filling layer 106 and the patterned photoresist layer 104 are removed.

[0037] In this embodiment, the method of depositing the initial second side wall layer 107 can be a chemical vapor deposition (CVD) or an atomic layer deposition process. The method of removing the initial second side wall layer 107 on the patterned photoresist layer 104 and the filling layer 106 can be a chemical mechanical polishing (CMP) process, and the CMP process stops when the surfaces of the patterned photoresist layer 104, the filling layer 106 and the remaining initial second side wall layer 107 are flush with each other. The process of etching part of the second initial side wall layer 107’ can be a dry etching process. The filling layer 106 can be selected as a photoresist material, so that the filling layer 106 can be removed synchronously with the photoresist layer 104.

[0038] Referring to Figure 12 and Figure 13 As shown, the filling structure 108 is formed in the gap between the plurality of first mandrel structures, and the plurality of first mandrel structures are removed to form the plurality of second mandrel structures; as shown, Figure 12As shown, a filling structure 108 is formed in the void left after removing part of the second initial sidewall layer 107' and the filling layer 106, and the surface of the filling structure 108 is flush with the surface of the sacrificial layer 103; as Figure 13 As shown, the sacrificial layer 103 is removed, meaning that the first mandrel structure is completely removed at this point.

[0039] In this embodiment, the filling structure 108 is formed in the void by first depositing a filling material and then by CMP. The sacrificial layer 103 can be removed by a dry etching process.

[0040] Since the height of the second sidewall layer 107” on the base layer 100 is lower than the height of the sacrificial layer 103 on the base layer 100, the filling structure 108 also covers the top of the second sidewall layer 107”. This protects the top of the second sidewall layer 107” and the sides of the second sidewall structure 110 during the removal of the sacrificial layer 103, preventing discrepancies between the actual and designed dimensions of the second sidewall structure 110. In other embodiments, a portion of the second initial sidewall layer 107” may be etched or a planarization process may be used until the height of the remaining second initial sidewall layer 107” on the base layer 100 is equal to the height of the sacrificial layer 103 on the base layer 100, ensuring that the subsequently formed filling structure 108 does not cover the top of the second sidewall layer 107”.

[0041] Reference Figures 14-15 The step of forming the first sidewall structure 109' on both sides of the second mandrel structure includes: as follows Figure 14 As shown, a first sidewall material 109 is deposited on the top and sides of the second mandrel structure and on the base layer 100; as Figure 15 As shown, the first sidewall material 109, except for the material located on both sides of the second mandrel structure, is removed by etching, and the remaining first sidewall material 109 serves as the first sidewall structure 109'.

[0042] Because the height of the second sidewall layer 107" on the base layer 100 is lower than the height of the sacrificial layer 103 on the base layer 100, the height of the formed first sidewall structure 109' is indirectly greater than the height of the second sidewall structure 110. In other embodiments, a portion of the second initial sidewall layer 107' may be etched until the height of the remaining second initial sidewall layer 107' on the base layer 100 is equal to the height of the sacrificial layer 103 on the base layer 100, so that the height of the subsequently formed first sidewall structure 109' is equal to the height of the second sidewall structure 110.

[0043] like Figure 16 As shown, the distance D2 between adjacent mask structures and the distance D1 between the two second sidewall structures 110 within the mask structure are measured for comparison.

[0044] In the embodiment, the pitch D2 of the adjacent mask structures and the pitch D1 of the two second side wall structures 110 in the mask structure can be measured by a line width measurement machine (CD-SEM) for comparison. Before the etching process starts, the measured pitch D2 can be greater than or less than D1.

[0045] Referring to Figures 17-23 , the etching of the base layer 100 forms the first opening 1021 between the adjacent mask structures and the second opening 1022 between the two second side wall structures 110 in the mask structure, wherein the etching selectivity of the first side wall structure 109' relative to the second side wall structure 110 in the etching process is controlled according to the comparison result.

[0046] In the embodiment, the process of etching the base layer 100 to form the first opening 1021 and the second opening 1022 is a dry etching process.

[0047] The pitch D2 of the adjacent mask structures and the pitch D1 of the two second side wall structures 110 in the mask structure are measured for comparison. Since the pitch D2 of the adjacent mask structures, i.e. the pitch D2 of the first side wall structure 109' in one mask structure and the first side wall structure 109' in another mask structure, directly affects the size of the second opening 1022 formed, and the pitch D1 of the two second side wall structures 110 in the mask structure directly affects the size of the first opening 1021, the size relationship between the pitch D2 and the pitch D1 determined by the comparison result can be used to dynamically adjust the etching selectivity of the first side wall structure 109' relative to the second side wall structure 110 in the etching process, so as to expand the pitch D1 of the two second side wall structures 110 in the mask structure relative to the pitch D2 of the adjacent mask structures, or expand the pitch D2 of the adjacent mask structures relative to the pitch D1 of the two second side wall structures 110 in the mask structure, so that the size of the first opening 1021 can be consistent with the size of the second opening 1022 after the etching process is completed, thereby ensuring the consistency of the feature size in the semiconductor structure.

[0048] In one embodiment, referring to Figure 17 , Figure 19 and Figure 23 , the step of controlling the etching selectivity of the first side wall structure 109' relative to the second side wall structure 110 in the etching process according to the comparison result includes: as shown in Figure 17 , when the pitch D2 of the adjacent mask structures is less than the pitch D1 of the two second side wall structures 110 in the mask structure, the etching rate of the first side wall structure 109' is controlled to be greater than the etching rate of the second side wall layer 107" in the etching process; as shown in Figure 19As shown, when the interval D2 of the adjacent mask structures is greater than the interval D1 of the two second sidewall structures 110 in the mask structure, the etching rate of the first sidewall structure 109' is controlled to be less than the etching rate of the first sidewall layer 105" in the etching process, and the substrate layer 100 is continuously etched, as shown in Figure 23 As shown, until the width of the first opening 1021 and the width of the second opening 1022 are equal, and the depth of the first opening 1021 and the depth of the second opening 1022 are equal.

[0049] In the embodiment, the material of the first sidewall structure 109' includes amorphous carbon, the material of the first sidewall layer 105" includes silicon dioxide, and the material of the second sidewall layer 107" includes any one of silicon nitride, silicon carbon nitride, and boron silicon nitride. The first etching gas is used to control the etching rate of the first sidewall structure 109' to be greater than the etching rate of the second sidewall layer 107" in the etching process, and the first etching gas includes carbon tetrafluoride and / or trifluoromethane, and nitrogen, oxygen, and carbon oxysulfide; the second etching gas is used to control the etching rate of the first sidewall structure 109' to be less than the etching rate of the first sidewall layer 105" in the etching process, and the second etching gas includes carbon tetrafluoride and / or difluoromethane, and carbon oxysulfide, nitrogen, oxygen, and argon.

[0050] It needs to be further explained that, at the beginning of the etching process, referring to Figure 17 When the interval D2 of the adjacent mask structures is less than the interval D1 of the two second sidewall structures 110 in the mask structure, if the etching rate of the first sidewall structure 109' is controlled to be greater than the etching rate of the second sidewall layer 107" in the etching process, then as shown in Figure 18 As shown, in the etching process, the etching to the width of the first opening 1022 and the width of the second opening 1022 will be equal, because the etching process not only exists in the thickness direction of the substrate layer 100 and the mask structure, but also exists in the direction of the width of the mask structure. Since the etching speed of the first sidewall structure 109' is faster, that is, the first sidewall structure 109' is etched faster in the direction of its width, the interval D2 of the adjacent mask structures is expanded relative to the interval D1 of the two second sidewall structures 110 in the mask structure, until the interval D2 is equal to D1.

[0051] In the process from the interval D1 being greater than D2 to the interval D2 being equal to the interval D1 for the first time, since the interval D2 is expanded to be equal to the interval D1, due to the influence of the etching aspect ratio, as shown in Figure 18 As shown, in this process, the depth L1 of the first opening 1021 is greater than the depth L2 of the second opening 1022. After that, the continuous etching will appear as shown in Figure 19The interval D2 of the adjacent mask structures is greater than the interval Dl of the two second sidewall structures 110 within the mask structure, and the second sidewall layer 107" is etched away completely. Then, referring to Figure 23 If the etching rate of the etching process on the first sidewall structure 109' is less than the etching rate on the first sidewall layer 105" while continuing to etch the substrate layer 100, the interval Dl of the two second sidewall structures 110 within the mask structure is enlarged relative to the interval D2 of the adjacent mask structures because the first sidewall layer 105" is etched faster in the direction of its width, i.e. the first sidewall layer 105" is etched faster, until the interval Dl is equal to the interval D2 again.

[0052] During the process of the interval Dl being less than D2 to the interval D2 being equal to the interval Dl again, because the interval Dl is enlarged to be equal to the interval D2, the depth Ll of the first opening 1021 continues to increase at a depth less than the depth L2 of the second opening 1022 continues to increase due to the etching aspect ratio factor, thus the difference between the depth Ll and the depth L2 is compensated, as shown in Figure 23 As shown, the two are finally equal. That is, the depth of the first opening 1021 and the depth of the second opening 1022 are finally equal, and the width of the first opening 1021 and the width of the second opening 1022 are finally equal, thus ensuring the consistency of the feature size in the semiconductor structure.

[0053] In another embodiment, referring to Figure 20 , Figure 22 and Figure 23 , according to the comparison result, the step of controlling the etching selectivity of the first sidewall structure 109' relative to the second sidewall structure 110 in the etching process includes: as shown in Figure 20 When the interval D2 of the adjacent mask structures is greater than the interval Dl of the two second sidewall structures 110 within the mask structure, the etching rate of the etching process on the first sidewall structure 109' is less than the etching rate on the second sidewall layer 107"; as shown in Figure 22 When the etching reaches the interval D2 of the adjacent mask structures is less than the interval Dl of the two second sidewall structures 110 within the mask structure, the etching rate of the etching process on the first sidewall structure 109' is greater than the etching rate on the first sidewall layer 105", and the substrate layer 100 is continuously etched until the width of the first opening 1021 and the width of the second opening 1022 are equal, and the depth of the first opening 1021 and the depth of the second opening 1022 are equal.

[0054] In this embodiment, the material of the first sidewall structure 109' includes amorphous carbon, the material of the first sidewall layer 105" includes any one of silicon nitride, silicon carbonitride, and silicon boron nitride, and the material of the second sidewall layer 107" includes silicon oxide. A second etching gas is used to control the etching rate of the first sidewall structure 109' to be less than the etching rate of the second sidewall layer 107"; the second etching gas includes carbon tetrafluoride and / or difluoromethane, as well as carbon oxysulfide, nitrogen, oxygen, and argon. A first etching gas is used to control the etching rate of the first sidewall structure 109' to be greater than the etching rate of the first sidewall layer 105"; the first etching gas includes carbon tetrafluoride and / or trifluoromethane, as well as nitrogen, oxygen, and carbon oxysulfide.

[0055] It should be further explained that at the beginning of the etching process, refer to Figure 20 When the spacing D2 between adjacent mask structures is greater than the spacing D1 between the two second sidewall structures 110 within the mask structure, and if the etching rate of the etching process on the first sidewall structure 109' is controlled to be less than the etching rate on the second sidewall layer 107", then... Figure 21 As shown, in the etching process, the width of the first opening 1022 and the width of the second opening 1022 will be equal. This is because the etching process not only etches the substrate layer 100 and the mask structure mainly in the thickness direction, but also etches the mask structure to a certain extent in the width direction. Since the etching speed of the second sidewall layer 107” is faster, that is, the second sidewall layer 107” is also etched faster in the width direction, the first sidewall layer 105” below the second sidewall layer 107” is also exposed faster. Similarly, the exposed first sidewall layer 105” is also etched in the width direction. Therefore, the distance D1 between the two second sidewall structures 110 in the mask structure is increased relative to the distance D2 between adjacent mask structures until the distance D1 is equal to D2.

[0056] During the etching process from when pitch D2 is greater than D1 until pitch D1 first equals pitch D2, the pitch D1 expands to equal pitch D2. Due to the influence of the etching aspect ratio, such as... Figure 21 As shown, the depth L1 of the first opening 1021 formed during this process is less than the depth L2 of the second opening 1022. Further etching will then result in... Figure 22 The spacing D2 between adjacent mask structures shown is smaller than the spacing D1 between the two second sidewall structures 110 within the mask structure, and the second sidewall layer 107” is completely etched away. Then, refer to... Figure 23If the etching rate of the control etching process to the first side wall structure 109' is greater than the etching rate to the first side wall layer 105", the etching of the base layer 100 is continued, and the interval D2 of the adjacent mask structure is enlarged relative to the interval D1 of the two second side wall structures 110 in the mask structure, because the etching speed of the first side wall structure 109' is faster, i.e. the first side wall structure 109' is etched faster in the direction of the width of the first side wall structure 109', until the interval D2 is equal to the interval D1 again.

[0057] Reference is made to Figures 22-23 During the process that the interval D2 is less than the interval D1 to the interval D2 is equal to the interval D1 again, because the interval D2 is enlarged to be equal to the interval D1, the depth L1 of the first opening 1021 continues to increase at a greater depth than the depth L2 of the second opening 1022 continues to increase due to the etching aspect ratio, and thus the difference between the depth L1 and the depth L2 is compensated, as shown in Figure 23 . Both are finally equal. That is, the depth of the first opening 1021 and the depth of the second opening 1022 are finally equal, and the width of the first opening 1021 and the width of the second opening 1022 are finally equal, thereby ensuring the consistency of the feature size in the semiconductor structure.

[0058] In the above embodiment, the height of the first side wall structure 109' on the base layer 100 is greater than or equal to the height of the second side wall structure 110 on the base layer 100.

[0059] In the above embodiment, the first opening 1021 and the second opening 1022 formed by etching penetrate the dielectric layer 102 and expose the surface of the substrate 101; or, the first opening 1021 and the second opening 1022 formed by etching stop in the dielectric layer 102.

[0060] According to some embodiments of the present disclosure, reference is made to Figure 16 , the present disclosure further provides a semiconductor structure in another aspect. The semiconductor structure includes a base layer 100 and a plurality of mask structures on the base layer 100. Each mask structure in the plurality of mask structures includes two first side wall structures 109' spaced apart from each other and two second side wall structures 110 spaced apart from each other, the two second side wall structures 110 are respectively located on the opposite two side walls of the two first side wall structures 109', and the second side wall structure 110 includes a first side wall layer 105" and a second side wall layer 107" stacked in turn along the thickness direction away from the base layer 100. Wherein, the plurality of mask structures are used for etching process, and in the etching process, the etching selectivity of the first side wall structure 109' relative to the second side wall structure 110 is adjusted according to the second side wall layer 107" and the first side wall layer 105".

[0061] In the above embodiments, the material of the first side wall layer 105", the material of the second side wall layer 107", and the material of the first side wall structure 109' can be different from each other, and the etching selectivity of the first side wall structure 109' to the second side wall structure 110 can be adjusted to be different in different stages of the etching process.

[0062] In the above embodiments, the material of the first side wall layer 105", the material of the second side wall layer 107", and the material of the first side wall structure 109' can be different from each other, and the etching selectivity of the first side wall structure 109' to the second side wall structure 110 can be adjusted to be different in different stages of the etching process. Figures 17-23 In the above embodiments, the material of the first side wall layer 105", the material of the second side wall layer 107", and the material of the first side wall structure 109' can be different from each other, and the etching selectivity of the first side wall structure 109' to the second side wall structure 110 can be adjusted to be different in different stages of the etching process.

[0063] In the above embodiments, the material of the first side wall layer 105", the material of the second side wall layer 107", and the material of the first side wall structure 109' can be different from each other, and the etching selectivity of the first side wall structure 109' to the second side wall structure 110 can be adjusted to be different in different stages of the etching process.

[0064] According to some embodiments of the present disclosure, the height of the first side wall structure 109' on the substrate layer 100 is greater than or equal to the height of the second side wall structure 110 on the substrate layer 100.

[0065] In the semiconductor structure provided in the present embodiments, the distance between adjacent mask structures, i.e. the distance between the first side wall structure in one mask structure and the first side wall structure in another mask structure, directly affects the size of the second opening formed, and the distance between the two second side wall structures in one mask structure directly affects the size of the first opening. In the etching process, the etching selectivity of the first side wall structure to the second side wall structure can be dynamically adjusted as needed, so as to expand the distance between the two second side wall structures in one mask structure relative to the distance between adjacent mask structures, or expand the distance between adjacent mask structures relative to the distance between the two second side wall structures in one mask structure, so that the feature size defined by the distance between adjacent mask structures and the feature size defined by the two second side wall structures in one mask structure can remain consistent after the etching process is completed, thereby ensuring the consistency of the feature size in the semiconductor structure.

[0066] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate layer; forming a plurality of mask structures spaced apart from each other on the substrate layer, each of the plurality of mask structures comprises two first sidewall structures spaced apart from each other and two second sidewall structures spaced apart from each other, the two second sidewall structures are respectively located on two opposite sidewalls of the two first sidewall structures, and the second sidewall structure comprises a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the substrate layer; measuring a distance between adjacent mask structures and a distance between the two second sidewall structures in the mask structure for comparison; etching the substrate layer to form a first opening and a second opening, the second opening is located between adjacent mask structures, and the first opening is located between the two second sidewall structures in the mask structure, wherein, according to the comparison result, the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process is controlled.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The step of controlling the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process according to the comparison result comprises: when the distance between adjacent mask structures is less than the distance between the two second sidewall structures in the mask structure, the etching rate of the first sidewall structure is greater than the etching rate of the second sidewall layer in the etching process; when the distance between adjacent mask structures is greater than the distance between the two second sidewall structures in the mask structure, the etching rate of the first sidewall structure is less than the etching rate of the first sidewall layer in the etching process, and the substrate layer is continuously etched until the width of the second opening and the width of the first opening are equal, and the depth of the second opening and the depth of the first opening are equal.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein The step of controlling the etching selectivity of the first sidewall structure relative to the second sidewall structure in the etching process according to the comparison result comprises: when the distance between adjacent mask structures is greater than the distance between the two second sidewall structures in the mask structure, the etching rate of the first sidewall structure is less than the etching rate of the second sidewall layer in the etching process; when the distance between adjacent mask structures is less than the distance between the two second sidewall structures in the mask structure, the etching rate of the first sidewall structure is greater than the etching rate of the first sidewall layer in the etching process, and the substrate layer is continuously etched until the width of the second opening and the width of the first opening are equal, and the depth of the second opening and the depth of the first opening are equal.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein The step of forming a plurality of mask structures spaced apart from each other on the substrate layer, each of the plurality of mask structures comprises two first sidewall structures spaced apart from each other and two second sidewall structures spaced apart from each other, the two second sidewall structures are respectively located on two opposite sidewalls of the two first sidewall structures, and the second sidewall structure comprises a first sidewall layer and a second sidewall layer stacked in sequence along a thickness direction away from the substrate layer comprises: forming a plurality of first mandrel structures spaced apart from each other on the substrate layer; forming a second side wall structure on two sides of each of the plurality of first mandrel structures, the second side wall structure comprising a first side wall layer and a second side wall layer stacked in sequence along a thickness direction away from the base layer; forming a filling structure in intervals of the plurality of first mandrel structures, and removing the plurality of first mandrel structures to form a plurality of second mandrel structures, each of the plurality of second mandrel structures comprising the filling structure and the second side wall structure on two sides of the filling structure; forming a first side wall structure on two sides of the second mandrel structure, and removing the filling structure.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein The step of forming a plurality of first mandrel structures spaced apart from each other on the base layer comprises: forming a sacrificial layer and a photoresist layer in sequence on the base layer; performing a patterning process on the photoresist layer; using the patterned photoresist layer as a mask, etching the sacrificial layer to form a plurality of through holes and a plurality of first mandrel structures at the same time, each of the plurality of through holes sequentially penetrating the photoresist layer and the sacrificial layer, and each of the plurality of first mandrel structures comprising the sacrificial layer and the photoresist layer stacked in sequence along a thickness direction of the base layer.

6. The method of manufacturing a semiconductor structure according to claim 5, wherein The step of forming a second side wall structure on two sides of each of the plurality of first mandrel structures, the second side wall structure comprising a first side wall layer and a second side wall layer stacked in sequence along a thickness direction away from the base layer comprises: depositing an initial first side wall layer on top of and on two sides of the plurality of first mandrel structures and on a bottom of the plurality of through holes; removing the initial first side wall layer on the bottom of the plurality of through holes and on the top of the plurality of first mandrel structures, and the remaining initial first side wall layer serving as a first initial side wall layer; forming a filling layer in the plurality of through holes, the filling layer covering side surfaces of the first initial side wall layer; etching part of the first initial side wall layer to form a gap between the plurality of first mandrel structures and the filling layer, and the remaining first initial side wall layer serving as a first side wall layer; forming a second side wall layer in the gap, and removing the filling layer and the patterned photoresist layer.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein The step of forming a second side wall layer in the gap, and removing the filling layer and the patterned photoresist layer comprises: depositing an initial second side wall layer in the gap and on the filling layer and the patterned photoresist layer; removing the initial second side wall layer on the filling layer and the patterned photoresist layer, and the remaining initial second side wall layer serving as a second initial side wall layer; etching part of the second initial side wall layer until a height of the remaining second initial side wall layer on the base layer is lower than a height of the sacrificial layer on the base layer, and the remaining second initial side wall layer serving as a second side wall layer; removing the filling layer and the patterned photoresist layer.

8. The method of manufacturing a semiconductor structure according to claim 7, wherein The step of forming the filling structure in the space between the first mandrel structures and removing the first mandrel structures to form second mandrel structures, each of the second mandrel structures comprising the filling structure and the second sidewall structure on both sides of the filling structure, comprises: The filling structure is formed in the space left after removing part of the second initial sidewall layer and the filling layer, and the surface of the filling structure is flush with the surface of the sacrificial layer; The sacrificial layer is removed.

9. The method of manufacturing a semiconductor structure according to claim 2, wherein The material of the first sidewall structure comprises amorphous carbon, the material of the first sidewall layer comprises silicon dioxide, and the material of the second sidewall layer comprises any one of silicon nitride, silicon carbon nitride and silicon boron nitride.

10. The method of manufacturing a semiconductor structure according to claim 9, wherein The first etching gas is used to control the etching rate of the etching process on the first sidewall structure to be greater than the etching rate on the second sidewall layer, and the first etching gas comprises carbon tetrafluoride and / or trifluoromethane, and nitrogen, oxygen and carbon oxysulfide; the second etching gas is used to control the etching rate of the etching process on the first sidewall structure to be less than the etching rate on the first sidewall layer, and the second etching gas comprises carbon tetrafluoride and / or difluoromethane, and carbon oxysulfide, nitrogen, oxygen and argon.

11. The method of manufacturing a semiconductor structure according to claim 3, wherein The material of the first sidewall structure comprises amorphous carbon, the material of the first sidewall layer comprises any one of silicon nitride, silicon carbon nitride and silicon boron nitride, and the material of the second sidewall layer comprises silicon oxide.

12. The method of manufacturing a semiconductor structure according to claim 11, wherein The second etching gas is used to control the etching rate of the etching process on the first sidewall structure to be less than the etching rate on the second sidewall layer, and the second etching gas comprises carbon tetrafluoride and / or difluoromethane, and carbon oxysulfide, nitrogen, oxygen and argon; the first etching gas is used to control the etching rate of the etching process on the first sidewall structure to be greater than the etching rate on the first sidewall layer, and the first etching gas comprises carbon tetrafluoride and / or trifluoromethane, and nitrogen, oxygen and carbon oxysulfide.

13. The method of manufacturing a semiconductor structure according to any one of claims 1 to 12, wherein The height of the first sidewall structure on the base layer is greater than or equal to the height of the second sidewall structure on the base layer.

14. The method of manufacturing a semiconductor structure according to any one of claims 1 to 12, wherein The base layer comprises a substrate and a dielectric layer on the substrate, and the etched second opening and first opening pass through the dielectric layer and expose the surface of the substrate; or the etched second opening and first opening stop in the dielectric layer.

15. A semiconductor structure, characterized by The base layer comprises: The base layer comprises: The plurality of mask structures on the base layer, each of the plurality of mask structures comprises two first sidewall structures spaced from each other and two second sidewall structures spaced from each other, the two second sidewall structures are respectively located on the opposite two sidewalls of the two first sidewall structures, and the second sidewall structure comprises a first sidewall layer and a second sidewall layer stacked in turn along the thickness direction away from the base layer; The plurality of mask structures are used for etching the base layer, and in the etching process, the etching selectivity ratio of the first side wall structure relative to the second side wall structure is adjusted according to the interval of adjacent mask structures and the interval of the two second side wall structures in the mask structure.

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