Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a plurality of correction reference components arranged along a first direction on a substrate; and a plurality of rows of first active components and a plurality of rows of second active components arranged on both sides of the correction reference components, wherein each row of the first active components is arranged along a second direction and comprises a plurality of first active components arranged along the first direction, and the first direction is not parallel to the second direction; and each row of the second active components is arranged along the second direction and comprises a plurality of second active components arranged along the first direction, and the correction reference components, the first active components and the second active components are arranged on the same layer and are part of the substrate.

Description

Technical Field

[0001] The present invention relates to semiconductor structures, and more particularly to semiconductor structures having a calibration reference component and methods for forming the same. Background Technology

[0002] In the manufacturing process of semiconductor devices (such as memory devices or transistor devices), various patterning processes (including photolithography and etching, etc.) are frequently used to transfer component patterns within the structure to form the desired semiconductor structure. However, as device dimensions continue to shrink, many challenges arise. For example, misalignments or errors may exist between various patterning processes, which can adversely affect the semiconductor structure, thereby reducing device reliability or performance. Summary of the Invention

[0003] This invention provides a semiconductor structure, including: a plurality of calibration reference components located on a substrate and spaced apart along a first direction; and a plurality of rows of first active components and a plurality of rows of second active components respectively disposed on both sides of the calibration reference components, wherein each row of first active components is spaced apart from each other in a second direction and each row of first active components includes a plurality of first active components spaced apart along the first direction, wherein the first direction is not parallel to the second direction; each row of second active components is spaced apart from each other in the second direction and each row of second active components includes a plurality of second active components spaced apart along the first direction; wherein the calibration reference components, first active components, and second active components are disposed on the same layer and are part of the substrate; wherein the width of the calibration reference component is greater than the width of the first active component and greater than the width of the second active component; and the length of the calibration reference component is greater than the length of the first active component and greater than the length of the second active component.

[0004] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate having an active layer thereon, wherein the active layer is part of the substrate; forming a mask layer stacked on the active layer; forming a sacrificial layer on the mask layer stack; forming a patterned spacer on the sacrificial layer, the patterned spacer including a correction reference pattern and an active region front pattern; performing a first patterning process to transfer the correction reference pattern and active region front pattern of the patterned spacer to the mask layer stack; after the first patterning process, performing a second patterning process to pattern the mask layer stack having the active region front pattern into an active region pattern; and after the second patterning process, performing a third patterning process to transfer the correction reference pattern and active region pattern of the mask layer stack to the active layer, thereby forming a plurality of correction reference components and a plurality of rows of active components, respectively. Attached Figure Description

[0005] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0006] Figures 1A to 8A , Figure 9 and Figure 10 This is a top view of a semiconductor structure according to some embodiments of the present invention.

[0007] Figures 1A-1 to 8A-1 According to some embodiments of the present invention, the following are respectively drawn along Figures 1A to 8A A cross-sectional view of the semiconductor structure along the A-A' line.

[0008] Figures 1A-2 to 8A-2 According to some embodiments of the present invention, respectively along Figures 2A to 8A A cross-sectional view of the semiconductor structure of the B-B' line.

[0009] Figure 11 and Figure 12 This is a top view of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0010] Figure 1A A top view of the semiconductor structure 10 is shown. Figure 1A-1 and Figure 1A-2 The semiconductor structure 10 is drawn along... Figure 1A The cross-sectional views of lines A-A' and B-B'. To simplify the diagram, Figure 1A Only a top view of the multiple rows of first active components G1, multiple rows of second active components G2, and multiple correction reference components 102C is shown. The semiconductor structure 10 includes a substrate 100, multiple rows of first active components G1, multiple rows of second active components G2, and multiple correction reference components 102C.

[0011] Reference Figure 1AA plurality of calibration reference components 102C are located on a substrate 100 and are spaced apart along a first direction d1. In some embodiments, the calibration reference components 102C have an annular shape. In some embodiments, the width W4 of one side of the annular shape may be equal to the width W1 of the first active component 102A and equal to the width W2 of the second active component 102B. Multiple rows of first active components G1 and multiple rows of second active components G2 are respectively disposed on both sides of the calibration reference components 102C. Each row of first active components G1 is spaced apart from each other in a second direction d2 and each row of first active components G1 includes a plurality of first active components 102A spaced apart along the first direction d1. In some embodiments, the first direction d1 is not parallel to the second direction d2. Each row of second active components G2 is spaced apart from each other in the second direction d2 and each row of second active components G2 includes a plurality of second active components 102B spaced apart along the first direction d1. (Refer to...) Figure 1A-1 and Figure 1A-2 The calibration reference component 102C, the first active component 102A, and the second active component 102B are disposed on the same layer. In some embodiments, the first active component 102A, the second active component 102B, and the calibration reference component 102C may comprise the same material. For example, the first active component 102A, the second active component 102B, and the calibration reference component 102C are part of the substrate 100, wherein the formation of the first active component 102A, the second active component 102B, the calibration reference component 102C, and the substrate 100 are all performed by patterning the substrate 100. Therefore, the first active component 102A, the second active component 102B, the calibration reference component 102C, and the substrate 100 are continuous and composed of the same material.

[0012] The calibration reference component 102C can be used to measure the offset between different processes to improve device reliability and / or process margin. For example, the patterns of the calibration reference component 102C and the active components (such as the first active component 102A and the second active component 102B) are formed in different patterning processes. Therefore, by measuring the offset between the calibration reference component 102C and the active components (such as the first active component 102A and the second active component 102B), it can be determined whether there is an offset between the patterning process forming the active components and the patterning process forming the calibration reference component 102C. Then, based on the measured offset, the parameters of the patterning process to be performed on the next step of the semiconductor structure can be optimized or subsequent process parameters can be adjusted, thereby improving device reliability and / or process margin. In some embodiments, the calibration reference component 102C and active components (such as the first active component 102A and the second active component 102B) may be integrated into the alignment mark region of the semiconductor device or disposed within the memory array region, such that the pattern of the active components (such as the first active component 102A and the second active component 102B) is formed in the same process as the active region of the semiconductor device, while it is formed in a different process than the pattern of the calibration reference component 102C. In some embodiments, by measuring the offset between the calibration reference component 102C and the active components (such as the first active component 102A and the second active component 102B), it can be determined whether the active region of the semiconductor device is offset, and the process parameters for forming the active region of the semiconductor device can be optimized or subsequent process parameters can be adjusted based on the measured offset. In some embodiments of the present invention, the semiconductor device is a dynamic random access memory (DRAM).

[0013] In some embodiments, the width W3 of the correction reference component 102C is greater than the width W1 of the first active component 102A and greater than the width W2 of the second active component 102B, and the length L3 of the correction reference component 102C is greater than the length L1 of the first active component 102A and greater than the length L2 of the second active component 102B. In some embodiments, the width W3 of the correction reference component 102C is at least twice the width W1 of the first active component 102A and at least twice the width W2 of the second active component 102B, and the length L3 of the correction reference component 102C is at least twice the length L1 of the first active component 102A and at least twice the length L2 of the second active component 102B, that is, W3 ≥ 2 * W1, W3 ≥ 2 * W2, L3 ≥ 2 * L1, and L3 ≥ 2 * L2.

[0014] In some embodiments, adjacent rows of first active components 102A are staggered, and adjacent rows of second active components 102B are staggered. For example, adjacent rows of first active components 102A have a first offset distance S1 in the first direction d1, and adjacent rows of second active components 102B have a second offset distance S2 in the first direction d1. The offset distance here is defined as the distance between corresponding positions of adjacent rows of active components in the first direction d1, for example... Figure 1A The distance S1 between the corresponding positions of the two adjacent rows of first active components 102A, indicated by the middle arrows 114 and 116, in the first direction d1. In some embodiments, the first offset distance S1 may be equal to the second offset distance S2.

[0015] In some embodiments, the longitudinal lengths of the correction reference component 102C, the first active component 102A, and the second active component 102B are all along a first direction. For example, the length L3 of the correction reference component 102C, the length L1 of the first active component 102A, and the length L2 of the second active component 102B are all along the first direction d1 and are parallel to each other.

[0016] In some embodiments, the outer contours of the calibration reference component 102C, the first active component 102A, and the second active component 102B have the same or similar shapes, which can make the offset measurement between the calibration reference component 102C and the active component faster or more accurate. For example, the outer contours of the calibration reference component 102C, the first active component 102A, and the second active component 102B can all be parallelograms, such as... Figure 1A As shown.

[0017] Reference Figure 1A In some embodiments, the distance E1 between the correction reference component 102C and the multiple rows of first active components G1 is equal to the distance E2 between the reference component 102C and the multiple rows of second active components G2. In some embodiments, two adjacent rows of first active components 102A have the same distance D3 and two adjacent rows of second active components 102B have the same distance D4. In other embodiments, the distance D3 is equal to the distance D4. In some embodiments, the distance D5 between two adjacent first active components 102A in each row of first active components G1 is equal to the distance D6 between two adjacent second active components 102B in each row of second active components G2. In some embodiments, the distance D7 between two adjacent correction reference components 102C is neither equal to the distance D5 nor equal to the distance D6.

[0018] Figures 2A to 8A A schematic diagram illustrating the process of forming the semiconductor structure 10 is shown. Figures 2A-1 to 8A-1 Draw along Figures 2A to 8A A cross-sectional view of the semiconductor structure along the A-A' line; Figures 2A-2 to 8A-2 Draw along Figures 2A to 8A A cross-sectional view of the semiconductor structure of the B-B' line. (Refer to...) Figure 2A-1 and Figure 2A-2 A substrate 100 is provided, on which an active layer 102 is provided. In some embodiments, the active layer 102 is part of the substrate 100, and therefore the active layer 102 and the substrate 100 comprise the same material. In one embodiment, the material of the active layer 102 comprises silicon.

[0019] Next, a masking layer stack 104 is formed on the active layer 102. In some embodiments, the masking layer stack 104 is a stack of multiple film layers, the materials of which may each include: oxides (e.g., tetraethyl orthosilicate (TEOS) oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride (SiON)), polycrystalline silicon, amorphous silicon, carbon-containing masking materials, or combinations thereof. In some embodiments, the masking layer stack 104 includes: a first masking layer 104A, a second masking layer 104B on the first masking layer 104A, and a third masking layer 104C on the second masking layer 104B, and the first masking layer 104A, the second masking layer 104B, and the third masking layer 104C may include different materials. In such embodiments, the material of the first masking layer 104A may include tetraethyl orthosilicate (TEOS) oxide, the material of the second masking layer 104B may include polysilicon or amorphous silicon, and the material of the third masking layer 104C may include a carbon-containing hard masking material. In other embodiments, the masking layer stack 104 is a single-layer structure, such as a polysilicon layer, an amorphous silicon layer, or a single-layer structure of the aforementioned materials.

[0020] Subsequently, a sacrificial layer 106 is formed on the mask layer stack 104. The material of the sacrificial layer 106 may include: oxynitride (e.g., silicon oxynitride (SiON)), nitride, polycrystalline silicon, amorphous silicon, carbide, or a combination thereof. In some embodiments, the sacrificial layer 106 is a multilayer structure, including a first sacrificial material layer 106A and a second sacrificial material layer 106B on the first sacrificial material layer 106A. In such embodiments, the material of the first sacrificial material layer 106A may include silicon oxynitride (SiON), and the material of the second sacrificial layer 106B may differ from that of the first sacrificial material layer 106A, and may include polycrystalline silicon or amorphous silicon. In other embodiments, the sacrificial layer 106 is a single-layer structure.

[0021] Reference Figure 2A , Figure 2A-1 and Figure 2A-2A patterned layer 108 is formed on the sacrificial layer 106. The patterned layer 108 has a railroad track profile. Specifically, the patterned layer 108 includes a plurality of strips 108A and a plurality of connecting members 108B between adjacent strips 108A. The connecting members 108B connect two adjacent strips 108A. The adjacent strips 108A and the connecting members 108B define a plurality of openings 109 that expose the sacrificial layer 106. According to some embodiments, the patterned layer 108 includes a photoresist layer, an antireflective layer (e.g., an organic dielectric layer (ODL)), or a combination thereof.

[0022] Reference Figure 3A , Figure 3A-1 and Figure 3A-2 A spacer layer 110' is formed on the patterned layer 108 and the sacrificial layer 106. The material of the spacer layer 110' may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. In some embodiments, the spacer layer 110' is compliantly formed on the patterned layer 108 and the sacrificial layer 106.

[0023] Reference Figure 4A , Figure 4A-1 and Figure 4A-2 The spacer layer 110' is etched back to expose the top surface of the patterned layer 108 and the top surface of the sacrificial layer 106. In some embodiments, the etching process includes reactive ion etching (RIE), neutral particle beam etching (NBE), or inductively coupled plasma etching.

[0024] Reference Figure 5A , Figure 5A-1 and Figure 5A-2 Remove the patterned layer 108. The remaining spacer layer 110' forms a patterned spacer 110. The patterned spacer 110 includes a correction reference pattern P1 and an active area front pattern P2. The correction reference pattern P1 includes multiple annular shapes.

[0025] Reference Figure 6A , Figure 6A-1 , Figure 6A-2 , Figure 7A , Figure 7A-1 and Figure 7A-2 Next, the first patterning process is performed to transfer the correction reference pattern P1 of the patterned spacer 110 and the active area front pattern P2 to the mask layer stack 104. For example... Figure 6A , Figure 6A-1 and Figure 6A-2As shown, the patterned spacer 110 is used as a mask to etch the sacrificial layer 106, and then the patterned spacer 110 is removed. In an embodiment where the sacrificial layer 106 includes a first sacrificial material layer 106A and a second sacrificial material layer 106B, the first sacrificial material layer 106A can serve as an etching stop layer, and the etched sacrificial layer 106 is etched through the second sacrificial material layer 106B but not through the first sacrificial material layer 106A. In such an embodiment, the first sacrificial material layer 106A can serve as an etching stop layer. In an embodiment where the sacrificial layer 106 is a single-layer structure, the etched sacrificial layer 106 is etched through the sacrificial layer 106, and the underlying mask structure 104 can serve as an etching stop layer. The etching process for the sacrificial layer 106 may include wet etching, dry etching (such as reactive ion etching, neutral particle beam etching, inductively coupled plasma etching, or other suitable etching processes).

[0026] like Figure 7A , Figure 7A-1 and Figure 7A-2 As shown, using a sacrificial layer 106 as an etching mask, etching is performed through the first sacrificial material layer 106A (if present, i.e., if the sacrificial layer 106 is a multilayer structure), the third mask layer 104C, and the second mask layer 104B. After etching, the sacrificial layer 106 and the third mask layer 104C are removed, thereby transferring the correction reference pattern P1 of the patterned spacer 110 and the active region pre-pattern P2 to the mask layer stack 104 (e.g., to the second mask layer 104B). The first mask layer 104A can serve as an etching stop layer and can protect the underlying active layer from damage during the etching process. In some embodiments, the process for etching the mask layer stack 104 can be the same as or similar to the etching process described above. In other embodiments, the first patterning process uses patterned spacer 110 as a mask, etches sacrificial layer 106 and mask layer stack 104 to transfer the correction reference pattern P1 and active region front pattern P2 of patterned spacer 110 to mask layer stack 104, and removes patterned spacer 110 and sacrificial layer 106 after etching.

[0027] Reference Figure 8A , Figure 8A-1 , Figure 8A-2 and Figure 9 After the first patterning process, a second patterning process is performed to form a patterned photoresist layer 112 on the second mask layer 104B having a correction reference pattern P1 and the exposed portion of the second mask layer 104B.

[0028] Reference Figure 9Next, the exposed portion of the second masking layer 104B is removed to pattern the second masking layer 104B having the active region front pattern P2 into the active region pattern P3, followed by the removal of the patterned photoresist layer 112. Performing the second patterning process involves cutting the masking layer stack 104 having the active region front pattern P2 into active region patterns P3 having multiple portions spaced apart from each other in the first direction d1. In such embodiments, the patterned photoresist layer 112 can be modified to adjust the shape of the exposed portion of the second masking layer 104B to achieve the desired active region pattern P3. In some embodiments, during the removal of the exposed portion of the second masking layer 104B, the patterned photoresist layer 112 protects the second masking layer 104B having the correction reference pattern P1 from the effects of the process because it is on the second masking layer 104B having the correction reference pattern P1. Therefore, the correction reference pattern P1 defined prior to the second patterning process (e.g., by patterned spacers and / or the first patterning process) can be well preserved in the second masking layer 104B. After performing the second patterning process, the second mask layer 104B has a correction reference pattern P1 and an active area pattern P3. In other embodiments, such as embodiments where the mask layer stack 104 is a single-layer structure, the correction reference pattern P1 and the active area pattern P3 can be transferred to the single-layer mask layer stack 104, with the active layer 102 below this mask layer stack 104.

[0029] Reference Figure 10Following the second patterning process, a third patterning process is performed to transfer the correction reference pattern P1 and active region pattern P3 of the mask layer stack 104 to the active layer 102, thereby forming a plurality of correction reference components 102C and a plurality of rows of active components G1 and G2, respectively. The mask layer stack 104 is then removed. The semiconductor structure 10 includes: correction reference components 102C having a correction reference pattern P1 defined prior to the second patterning process (e.g., by patterned spacers and / or the first patterning process), and a plurality of rows of active components G1 and G2 having an active region pattern P3 defined in the second patterning process. By measuring the offset between the correction reference components 102C and the plurality of rows of active components G1 and G2 and comparing it with a predetermined offset value (ideally, the offset value is 0), it can be determined whether there is an offset between the second patterning process and the process prior to the second patterning process (e.g., the process of forming patterned spacers and / or the first patterning process). For example, if the measured offset between the calibration reference component 102C and the multi-row active components G1 and G2 is equal to 0, it indicates that there is no offset between the processes; if the measured offset between the calibration reference component 102C and the multi-row active components G1 and G2 is not equal to 0, it indicates that there may be an offset between the processes and that the positions of the multi-row active components G1 and G2 may be deviated. In some embodiments, the process parameters of the first patterning process and / or the second patterning process can be optimized based on the measured offset, thereby improving device reliability and / or process margin. In some embodiments, the semiconductor structure 10 can be integrated into the semiconductor device. For example, the calibration reference component 102C, the multi-row active components G1 and G2, and their processes (e.g., including the second patterning process) can be integrated with the active region of the semiconductor device and its processes. After the components are formed, the offset between the calibration reference component 102C and the multi-row active components G1 and G2 is measured. This allows it to be determined whether the multi-row active components G1 and G2 and the active region are offset, and the process can be optimized based on the offset to improve device reliability and / or performance.

[0030] In some embodiments, the outer contours of the correction reference pattern P1 and the active area pattern P3 have the same or similar shapes, for example, they may have a parallelogram outer contour, an elliptical outer contour, or a rounded rectangular outer contour. For example, in Figure 11 In the illustrated embodiment, the outer contours of the first active component 102A, the second active component 102B, and the correction reference component 102C are all elliptical. Figure 12 In the illustrated embodiment, the outer contours of the first active component 102A, the second active component 102B, and the correction reference component 102C are all rounded rectangular.

[0031] Some embodiments of the present invention provide a semiconductor structure with a calibration reference component and a method for forming the same, which can be used to measure inter-process offsets to improve device reliability and / or process margin. In some embodiments, the measured offset can be used to determine whether an active component has an offset, thereby further optimizing the process and improving device reliability and / or process margin. Furthermore, the semiconductor structure provided in the embodiments of the present invention can be integrated into a semiconductor device, using the measured offset to improve device reliability and / or performance.

[0032] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple calibration reference components are located on a substrate and spaced apart along a first direction; as well as Multiple rows of first active components and multiple rows of second active components are respectively disposed on both sides of the correction reference component, wherein... Each row of first active components is spaced apart from each other along a second direction, and each row of first active components includes a plurality of first active components spaced apart along the first direction, wherein the first direction is not parallel to the second direction. Each row of second active components is spaced apart from each other in the second direction, and each row of second active components includes a plurality of second active components spaced apart along the first direction. The calibration reference component, the first active component, and the second active component are disposed on the same layer and are part of the substrate. The width of the calibration reference component is greater than the width of the first active component and the width of the second active component. The length of the calibration reference component is greater than the length of the first active component and the length of the second active component.

2. The semiconductor structure as described in claim 1, characterized in that, The width of the correction reference component is at least twice the width of the first active component and at least twice the width of the second active component, and the length of the correction reference component is at least twice the length of the first active component and at least twice the length of the second active component.

3. The semiconductor structure as described in claim 1, characterized in that, Two adjacent rows of first active components are staggered with each other, and two adjacent rows of second active components are staggered with each other, wherein the distance between two adjacent first active components in each row of first active components is equal to the distance between two adjacent second active components in each row of second active components, wherein the width of one side of the correction reference component is equal to the width of the first active component and equal to the width of the second active component.

4. The semiconductor structure as described in claim 1, characterized in that, The outer contours of the correction reference component, the first active component, and the second active component have the same shape.

5. The semiconductor structure as described in claim 4, characterized in that, The shape of the outer contour includes a parallelogram, an ellipse, or a rounded rectangle.

6. The semiconductor structure as described in claim 1, characterized in that, The calibration reference component has a ring shape.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having an active layer thereon, wherein the active layer is a part of the substrate; A masking layer is formed and stacked on the active layer; A sacrificial layer is formed on the masking layer stack; A patterned spacer is formed on the sacrificial layer, the patterned spacer including a correction reference pattern and an active region front pattern; A first patterning process is performed to transfer the correction reference pattern and the active area front pattern of the patterned spacer to the mask layer stack; After the first patterning process, a second patterning process is performed to stack and pattern the mask layer having the active area front pattern into an active area pattern. as well as After the second patterning process, a third patterning process is performed to transfer the correction reference pattern and the active area pattern stacked on the mask layer to the active layer, so as to form a plurality of correction reference components and a plurality of rows of active components respectively.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The reference components are spaced apart along one direction, and the multi-row active components include multiple rows of first active components and multiple rows of second active components, which are respectively disposed on both sides of the correction reference components.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, Forming the patterned spacers on the sacrificial layer includes: A patterned layer is formed on the sacrificial layer, wherein the patterned layer includes a plurality of strips and a plurality of connecting members between adjacent strips, the adjacent strips and the connecting members defining a plurality of openings and the openings exposing the sacrificial layer; A spacer layer is formed on the patterned layer and the sacrificial layer; Etch the spacer layer to expose the top surface of the patterned layer and the top surface of the sacrificial layer; and Remove the patterned layer.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, Performing the first patterning process includes: The patterned spacers are used as a mask to etch the sacrificial layer; Remove the patterned spacers; and Using the sacrificial layer as a mask, the mask layer stack is etched.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, Performing the second patterning process includes: A patterned photoresist layer is formed on the mask layer stack having the correction reference pattern, with the exposed portion of the mask layer stack; and Remove the exposed portion of the mask layer stack.

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