Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a device unit area, wherein a stack structure is formed in the device unit area, the stack structure including a first channel layer, a sacrificial layer and a second channel layer, first and second pre-embedded power layers are formed on both sides of the device unit area, and a dummy gate structure is formed on the substrate; forming a protection wall on a sidewall of the stack structure closest to the second pre-embedded power layer; after forming the protection wall, removing the stack structure on both sides of the dummy gate structure to form a first source-drain doped layer; forming a first source-drain interconnection layer covering the first source-drain doped layer, extending to the top of the first pre-embedded power layer and electrically connected; forming an isolation layer covering the first source-drain interconnection layer; forming a second source-drain doped layer on the isolation layer; and forming a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall, extending to the top of the second pre-embedded power layer and electrically connected. The present application reduces the probability of short circuit between the second source-drain interconnection layer and the first source-drain doped layer or the first source-drain interconnection layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the decrease of the feature size, the channel length of MOSFET is also shortened accordingly. However, with the shortening of the device channel length, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, i.e. the so-called short-channel effects (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the decrease of the feature size, the semiconductor process gradually begins to transition from the planar MOSFET to the three-dimensional transistor with higher efficiency.

[0004] Among them, the complementary field effect transistor (CFET) composed of vertical stacking is a kind of revolutionary three-dimensional transistor. In the CFET structure, the PMOS transistor and the NMOS transistor vertically stacked with each other constitute a complementary device, but the working performance of the CFET still needs to be further improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the working performance of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate, comprising a device unit area for forming a first transistor and a second transistor stacked from bottom to top; a pre-embedded power supply layer, located in the substrate on both sides of the device unit area in a second direction, comprising a first pre-embedded power supply layer located on one side of the device unit area, and a second pre-embedded power supply layer located on the other side of the device unit area; the first transistor, located on the substrate of the device unit area, comprising a first channel layer extending along a first direction, a first gate structure crossing the first channel layer and covering the top and sidewall of the first channel layer, and a first source-drain doped layer located on the substrate on both sides of the first gate structure, the first source-drain doped layer being in contact with the end of the first channel layer located below the first gate structure, the second direction being perpendicular to the first direction; a first source-drain interconnection layer covering the first source-drain doped layer, the first source-drain interconnection layer also extending from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and being electrically connected with the first pre-embedded power supply layer; an isolation layer located on the top of the first source-drain interconnection layer; the second transistor, stacked above the first transistor, comprising a second channel layer extending along the first direction, a second gate structure crossing the second channel layer and covering the second channel layer, and a second source-drain doped layer located on the isolation layer on both sides of the second gate structure, the second source-drain doped layer being in contact with the end of the second channel layer located below the second gate structure; a protection wall located in the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer and extending downward to cover the sidewall of the first source-drain doped layer; a second source-drain interconnection layer covering the second source-drain doped layer and part of the sidewall of the protection wall, the second source-drain interconnection layer also extending from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and being electrically connected with the second pre-embedded power supply layer.

[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, including a device unit area for forming a first transistor and a second transistor stacked from bottom to top in sequence, a stack structure extending along a first direction is formed on the substrate of the device unit area, the stack structure includes a first channel layer, a sacrifice layer located on the first channel layer, and a second channel layer located on the sacrifice layer, in a second direction, a first pre-embedded power layer and a second pre-embedded power layer are respectively formed in the substrate on both sides of the device unit area, the second direction is perpendicular to the first direction, a pseudo gate structure is also formed on the substrate and crosses the stack structure, the pseudo gate structure covers part of the sidewall and part of the top of the stack structure; a protection wall is formed on the sidewall of the stack structure closest to the second pre-embedded power layer; after the protection wall is formed, the stack structure on both sides of the pseudo gate structure is removed to form a source-drain recess; a first source-drain doped layer is formed in the source-drain recess, the first source-drain doped layer is in contact with the end of the first channel layer located below the pseudo gate structure; a first source-drain interconnection layer covering the first source-drain doped layer is formed, the first source-drain interconnection layer also extends to the top of the corresponding first pre-embedded power layer in the longitudinal direction and is electrically connected with the first pre-embedded power layer; an isolation layer covering the top of the first source-drain interconnection layer is formed, the isolation layer exposes the end of the second channel layer; a second source-drain doped layer is formed on the isolation layer on both sides of the pseudo gate structure, the second source-drain doped layer is in contact with the end of the second channel layer located below the pseudo gate structure; a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall located on the sidewall of the second source-drain doped layer is formed, the second source-drain interconnection layer also extends to the top of the corresponding second pre-embedded power layer in the longitudinal direction and is electrically connected with the second pre-embedded power layer.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present application, the first transistor and the second transistor are stacked from top to bottom, which is beneficial to save the occupied area of the semiconductor structure, and the first source-drain interconnection layer extends to the top of the corresponding first pre-embedded power layer in the longitudinal direction and is electrically connected with the first pre-embedded power layer, the second source-drain interconnection layer covers part of the sidewall of the protection wall and extends to the top of the corresponding second pre-embedded power layer in the longitudinal direction and is electrically connected with the second pre-embedded power layer, the protection wall is located on the sidewall of the second source-drain doped layer closest to the second pre-embedded power layer and extends downward to cover the sidewall of the first source-drain doped layer, which is beneficial to better protect the first source-drain doped layer and the first source-drain interconnection layer on the side of the second source-drain interconnection layer in the step of forming the second source-drain interconnection layer, reduce the probability of contact of the second source-drain interconnection layer with the first source-drain doped layer and the first source-drain interconnection layer due to too close distance, thereby reducing the probability of short circuit of the second source-drain interconnection layer with the first source-drain doped layer or the first source-drain interconnection layer, and further guaranteeing the working performance of the semiconductor structure.

[0010] The forming method provided by the embodiment of the present application comprises the following steps: forming a protection wall on a side wall of a second pre-buried power supply layer in a stack structure; removing the stack structure on both sides of a pseudo gate structure to form a source-drain groove; forming a first source-drain doped layer and a second source-drain doped layer in the source-drain groove; the protection wall covers the side wall of the second source-drain doped layer closest to the second pre-buried power supply layer and extends downward to cover the side wall of the first source-drain doped layer; a second source-drain interconnection layer covering the second source-drain doped layer is formed; the second source-drain interconnection layer covers part of the side wall of the protection wall and extends to the top of the second pre-buried power supply layer in the longitudinal direction and is electrically connected with the second pre-buried power supply layer; in the step of forming the second source-drain interconnection layer, the protection wall better protects the first source-drain doped layer and the first source-drain interconnection layer on the side of the second source-drain interconnection layer, reduces the probability that the second source-drain interconnection layer contacts the first source-drain doped layer or the first source-drain interconnection layer due to being too close to the first source-drain doped layer or the first source-drain interconnection layer when the second source-drain interconnection layer is formed, thereby reducing the probability that the second source-drain interconnection layer is short-circuited with the first source-drain doped layer or the first source-drain interconnection layer, and further ensuring the working performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1-3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0012] Figures 4-5 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application;

[0013] Figures 6-20 is a structure diagram corresponding to each step in a forming method of a semiconductor structure of the present application. DETAILED DESCRIPTION

[0014] The working performance of the semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a forming method of a semiconductor structure.

[0015] Figures 1-3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0016] COMBINED REFERENCE Figure 1 and Figure 2 , Figure 1 is a top view of the channel layer and the pseudo gate structure, Figure 2 (a) is Figure 1 is a sectional view along the AA direction, Figure 2 (b) is Figure 1 A substrate 10 is provided, including a device unit area 10Q for forming a first transistor and a second transistor stacked from bottom to top in sequence, a pseudo gate structure is formed on the substrate 10 of the device unit area 10Q, and a first pre-buried power supply layer is formed on the substrate 10 of the device unit area 10Q. Figure 1The stack structure 20 extends in the X direction (as shown by the arrow in the X direction), and includes a first channel layer 21, a sacrificial layer 23 located on the first channel layer 21, and a second channel layer 22 located on the sacrificial layer 23. The device unit region 10Q is located in the Y direction (as shown by the arrow in the Y direction) on the substrate 10, and the substrate 10 includes a first pre-embedded power supply layer 14 and a second pre-embedded power supply layer 15 located on both sides of the device unit region 10Q. The Y direction is perpendicular to the X direction. The substrate 10 further includes a dummy gate structure 16 crossing the stack structure 20, and the dummy gate structure 16 covers part of the sidewall and part of the top of the stack structure 20. Figure 1 The stack structure 20 extends in the X direction (as shown by the arrow in the X direction), and includes a first channel layer 21, a sacrificial layer 23 located on the first channel layer 21, and a second channel layer 22 located on the sacrificial layer 23. The device unit region 10Q is located in the Y direction (as shown by the arrow in the Y direction) on the substrate 10, and the substrate 10 includes a first pre-embedded power supply layer 14 and a second pre-embedded power supply layer 15 located on both sides of the device unit region 10Q. The Y direction is perpendicular to the X direction. The substrate 10 further includes a dummy gate structure 16 crossing the stack structure 20, and the dummy gate structure 16 covers part of the sidewall and part of the top of the stack structure 20.

[0017] Continuing to refer to Figure 1 and Figure 2 , the first source / drain doped layer 41 is formed in the stack structure 20 on both sides of the dummy gate structure 16, and the first source / drain doped layer 41 is in contact with the end of the first channel layer 21 under the dummy gate structure 16. The first source / drain interconnection layer 42 covering the first source / drain doped layer 41 is formed on both sides of the dummy gate structure 16, and the first source / drain interconnection layer 42 further extends in the longitudinal direction (as shown by the arrow in the Z direction) to the top of the corresponding first pre-embedded power supply layer 14 and is electrically connected to the first pre-embedded power supply layer 14. Figure 2

[0018] Referring to Figure 3 , Figure 3 (a) is a cross-sectional view based on Figure 2 (a), and Figure 3 (b) is a cross-sectional view based on Figure 2 (b). The isolation layer 17 is formed on the first source / drain interconnection layer 42, and the isolation layer 17 exposes the end of the second channel layer 22. The second source / drain doped layer 61 is formed on the isolation layer 17 on both sides of the dummy gate structure 16, and the second source / drain doped layer 61 is in contact with the end of the second channel layer 22 under the dummy gate structure 16. The second source / drain interconnection layer 62 covering the second source / drain doped layer 61 is formed on both sides of the dummy gate structure 16, and the second source / drain interconnection layer 62 further extends in the longitudinal direction to the top of the corresponding second pre-embedded power supply layer 15 and is electrically connected to the second pre-embedded power supply layer 15.

[0019] The second source / drain interconnection layer 62 extends downward from the side of the second source / drain doped layer 61. Since the first transistor and the second transistor are stacked, the second source / drain interconnection layer 62 also extends downward from the side of the first source / drain interconnection layer 42 and the first source / drain doped layer 41. Therefore, when the second source / drain interconnection layer 62 is formed, the part of the second source / drain interconnection layer 62 extending downward is likely to be too close to the first source / drain interconnection layer 41 or the first source / drain doped layer 41, which may cause the second source / drain interconnection layer 62 to be short-circuited with the first source / drain interconnection layer 41 or the first source / drain doped layer 41, and further affect the working performance of the semiconductor structure.

[0020] ​To address the technical problem, this invention provides a method for forming a semiconductor structure. After forming a protective wall on the sidewall closest to the second embedded power layer in the stacked structure, the stacked structures on both sides of the dummy gate structure are removed to form source / drain grooves. Then, a first source / drain doped layer and a second source / drain doped layer are formed in the source / drain grooves. The protective wall covers the sidewall of the second source / drain doped layer closest to the second embedded power layer and extends downwards to cover the sidewall of the first source / drain doped layer. A second source / drain interconnect layer is then formed, covering the second source / drain doped layer. The second source / drain interconnect layer covers a portion of the protective wall's sidewall and extends vertically towards the top of the second embedded power layer, electrically connecting to it. In the step of forming the second source / drain interconnect layer, the protective wall effectively protects the first source / drain doped layer and the first source / drain interconnect layer on the side of the second source / drain interconnect layer, reducing the probability of the second source / drain interconnect layer contacting the first source / drain doped layer or the first source / drain interconnect layer due to excessive proximity during its formation. This reduces the probability of short circuits between the second source / drain interconnect layer and the first source / drain doped layer or the first source / drain interconnect layer, thereby ensuring the working performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figure 4 and Figure 5 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention. Figure 4 This is a top view of the gate structure and the source / drain doped layers. Figure 5 (a) is Figure 4 Cross-sectional view based on the AA direction, Figure 5 (b) is Figure 4 Sectional view based on the BB direction.

[0023] The semiconductor structure includes: a substrate 101, including device cell regions 101Q for forming a first transistor and a second transistor stacked sequentially from bottom to top; and a buried power layer (not shown) located in the device cell region 101Q in a second direction (e.g., Figure 4 The substrates 101 on both sides of the device cell region 101Q (as shown in the Y direction) include a first buried power layer 141 located on one side of the device cell region 101Q and a second buried power layer 151 located on the other side of the device cell region 101Q; a first transistor is located on the substrate 101 of the device cell region 101Q, and the first transistor includes components along a first direction (as shown in the Y direction). Figure 4The first channel layer 211 extends (as shown in the X direction), the first gate structure 711 spans the first channel layer 211 and covers the top and sidewalls of the first channel layer 211, and the first source / drain doped layer 421 is located on the substrate 101 on both sides of the first gate structure 711. The first source / drain doped layer 421 is in contact with the end of the first channel layer 211 located below the first gate structure 711, and the second direction is perpendicular to the first direction; the first source / drain interconnect layer 421 covers the first source / drain doped layer 411, and the first source / drain interconnect layer 421 also extends from the side of the first source / drain doped layer 411 in the longitudinal direction (as shown in the X direction). Figure 5 (As shown in the Z-direction) Extends upward to the top of the corresponding first embedded power layer 141 and is electrically connected to the first embedded power layer 141; an isolation layer 171 is located on top of the first source-drain interconnect layer 421; a second transistor is stacked above the first transistor, the second transistor including a second channel layer 221 extending along the first direction, a second gate structure 721 spanning the second channel layer 221 and covering the second channel layer 221, and a second source-drain doped layer 611 located on the isolation layer 171 on both sides of the second gate structure 721, the second source-drain doped layer 611 and The ends of the second channel layer 221 located below the second gate structure 721 are in contact; the guard wall 311 is located on the sidewall of the second source / drain doped layer 611 closest to the second buried power layer 151 and extends downward to cover the sidewall of the first source / drain doped layer 411; the second source / drain interconnect layer 621 covers the second source / drain doped layer 611 and part of the sidewall of the guard wall 311, and the second source / drain interconnect layer 611 also extends longitudinally from the side of the guard wall 311 to the top of the corresponding second buried power layer 151 and is electrically connected to the second buried power layer 151.

[0024] In this embodiment, the first transistor and the second transistor are stacked one on top of the other, which helps to save the area occupied by the semiconductor structure.

[0025] The semiconductor structure is a complementary field-effect transistor (CFET) structure, where PMOS and NMOS transistors stacked perpendicularly to each other constitute a complementary device. The first transistor is the bottom transistor in the CFET structure, and the second transistor is the top transistor in the CFET structure. The first and second transistors have different channel conductivity types. Depending on the structural type of the first and second transistors, both the first and second transistors include either a FinFET or a Gate-All-Around (GAA) transistor. This embodiment uses FinFETs as an example where both the first and second transistors are FinFETs.

[0026] The substrate 101 is used to provide a process platform for the formation of semiconductor structures.

[0027] The substrate 101 includes a device cell region 101Q for forming a stacked first transistor and a second transistor.

[0028] In this embodiment, the base 101 includes a substrate 111, a bottom fin 121 standing on the substrate 111 in the device unit region 101Q, and an isolation layer 131 located on the substrate 111 and surrounding the bottom fin 121.

[0029] In this embodiment, the material of the substrate 111 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. As an example, the bottom fin 121 is an integral structure with the substrate 111.

[0030] In this embodiment, the isolation layer 131 can be a shallow trench isolation structure (STI). The material of the isolation layer 131 is an insulating material. As an example, the material of the isolation layer 131 is silicon oxide.

[0031] The buried power rail (BPR) layer is used to electrically connect the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621, and load corresponding voltages for the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621. The buried power rail layer includes an embedded power supply wiring (VDD) and an embedded ground wiring (VSS).

[0032] In this embodiment, the buried power rail layer is located in the substrate 111 and covered by the isolation layer 131, so that the buried power rail layer is buried in the base, and thus the buried power rail layer has a good isolation effect with other film layers above the buried power rail layer.

[0033] In the first transistor, the first channel layer 211 is used to provide a channel of the first transistor. In this embodiment, the first channel layer 211 is a first fin standing on the bottom fin 121.

[0034] In this embodiment, the material of the first channel layer 211 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the first channel layer 211 is silicon. In other embodiments, the material of the first channel layer is determined according to the type and performance of the first transistor.

[0035] The first gate structure 711 is used to control the opening and closing of the channel of the first transistor.

[0036] The first gate structure 711 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0037] The gate dielectric layer is used to isolate the gate electrode layer from the first channel layer 211 and the base 101.

[0038] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0039] It should be noted that the gate dielectric layer can also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the first channel layer 211. Specifically, the material of the gate oxide layer can be silicon oxide.

[0040] In this embodiment, the first gate structure 711 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0041] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0042] In other embodiments, the gate electrode layer can also include only the work function layer.

[0043] In other embodiments, the first gate structure can also be a poly-silicon gate structure according to process requirements.

[0044] The first source / drain doped layer 411 is used as a source region or a drain region of the first transistor.

[0045] Specifically, the doping type of the first source / drain doped layer 411 is the same as the channel conduction type of the corresponding first transistor. In this embodiment, the first transistor is an NMOS transistor, and the doping ions in the first source / drain doped layer 411 are N-type ions, which include P ions, As ions, or Sb ions.

[0046] In the second transistor, the second channel layer 221 is used to provide a channel of the second transistor. In this embodiment, the second channel layer 221 is a second fin.

[0047] In this embodiment, the material of the second channel layer 221 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the second channel layer 221 is silicon. In other embodiments, the material of the second channel layer is determined according to the type and performance of the second transistor.

[0048] The second gate structure 721 is configured to control the turn-on and turn-off of the channel of the second transistor.

[0049] The second gate structure 721 comprises a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.

[0050] The gate dielectric layer is configured to isolate the gate electrode layer from the second channel layer 221 and the first gate structure 711.

[0051] For the specific description of the second gate structure 721, reference can be made to the foregoing description of the first gate structure 711, which will not be repeated here.

[0052] The second source-drain doped layer 611 is configured to serve as a source region or a drain region of the second transistor.

[0053] Specifically, the doping type of the second source-drain doped layer 611 is the same as the channel conduction type of the corresponding second transistor. In the embodiment, the second transistor is a PMOS transistor, and the doping ions in the second source-drain doped layer 611 are P-type ions, including B ions, Ga ions or In ions.

[0054] In the embodiment, the semiconductor structure further comprises a first interlayer dielectric layer 501 on the substrate 101, covering the sidewalls of the first source-drain interconnection layer 421, the sidewalls of the first gate structure 711, the sidewalls of the second gate structure 721, and part of the sidewalls of the protection wall 311.

[0055] The first interlayer dielectric layer 501 is configured to play an isolation role between adjacent devices, and is further configured to provide a process basis for forming the first gate structure 711, the second gate structure 721, the first source-drain interconnection layer 421, and the second source-drain interconnection layer 621.

[0056] The material of the first interlayer dielectric layer 501 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0057] The first source-drain interconnection layer 421 is configured to electrically connect the first pre-embedded power supply layer 141 and the first source-drain doped layer 411, and to apply a voltage to the first source-drain doped layer 411.

[0058] The first source-drain interconnection layer 421 is electrically connected with the pre-embedded power supply layer (not shown) on one side of the device unit area 101Q. In this embodiment, according to the design of the circuit layout, the first source-drain interconnection layer 421 extends to the top of the corresponding first pre-embedded power supply layer 141 and is electrically connected with the first pre-embedded power supply layer 141. Specifically, the first source-drain interconnection layer 421 extends from the side of the first source-drain doped layer 411 facing the first pre-embedded power supply layer 141 to the top of the first pre-embedded power supply layer 141 in the longitudinal direction.

[0059] In other embodiments, according to the process requirements, the first source-drain interconnection layer can also extend to the top of the second pre-embedded power supply layer and be electrically connected with the second pre-embedded power supply layer.

[0060] In this embodiment, the first source-drain interconnection layer 421 includes: a first lateral portion 441 extending in the second direction, located in the first interlayer dielectric layer 501, and covering the first source-drain doped layer 411; and a first longitudinal portion 431 extending in the longitudinal direction, located in the substrate 101 on the side of the first source-drain doped layer 411, and having a top connected with the bottom of the first lateral portion 441 and a bottom connected with the top of the first pre-embedded power supply layer 141.

[0061] The first lateral portion 441 electrically connects the first source-drain doped layer 411, the first longitudinal portion 431 is located between the bottom of the first lateral portion 441 and the top of the first pre-embedded power supply layer 141, the first longitudinal portion 431 electrically connects the first lateral portion 441 and the first pre-embedded power supply layer 141, and the first pre-embedded power supply layer 141 is located in the substrate 101. Therefore, the first source-drain interconnection layer 421 is electrically connected with the first pre-embedded power supply layer 141 through the first longitudinal portion 431 extending in the longitudinal direction.

[0062] To this end, in this embodiment, the first source-drain interconnection layer 421 penetrates the isolation layer 131 on the top of the first pre-embedded power supply layer 141 in the longitudinal direction.

[0063] In this embodiment, the material of the first source-drain interconnection layer 421 includes W or Co.

[0064] W or Co is a metal material and has good electrical conductivity, which is conducive to the good electrical connection between the first source-drain doped layer 411 and the first pre-embedded power supply layer 141.

[0065] In this embodiment, the isolation layer 171 is located on the top of the first source-drain interconnection layer 421 and is used to isolate the first source-drain interconnection layer 421 and the second source-drain doped layer 611 located on the isolation layer 171, and to isolate the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621 located on the isolation layer 171.

[0066] In this embodiment, the first source-drain interconnection layer 421 is located in the first interlayer dielectric layer 501, and the isolation layer 171 is located in the first interlayer dielectric layer 501 and covers the top of the first source-drain interconnection layer 421.

[0067] In this embodiment, the material of the isolation layer 171 includes SiN, SiON, SiOCN, SiOC, or SiOCH.

[0068] SiN, SiON, SiOCN, SiOC, or SiOCH has good insulation and can achieve good isolation effect.

[0069] The second source-drain interconnection layer 621 is used to electrically connect the second pre-buried power supply layer 151 and the second source-drain doped layer 611, and apply voltage to the second source-drain doped layer 611.

[0070] The second source-drain interconnection layer 621 is electrically connected with the pre-buried power supply layer (not labeled) on the other side of the device unit area 101Q. In this embodiment, according to the design of the circuit layout, the second source-drain interconnection layer 621 extends to the top of the corresponding second pre-buried power supply layer 151 and is electrically connected with the second pre-buried power supply layer 151. Specifically, the second source-drain interconnection layer 621 extends from the side of the second source-drain doped layer 611 facing the second pre-buried power supply layer 151 to the top of the second pre-buried power supply layer 151 in the longitudinal direction.

[0071] In other embodiments, according to process requirements, the second source-drain interconnection layer can also extend to the top of the first pre-buried power supply layer and be electrically connected with the first pre-buried power supply layer, and correspondingly, the protection wall is located on the sidewall of the second source-drain doped layer closest to the first pre-buried power supply layer and extends downward to cover the sidewall of the first source-drain doped layer.

[0072] In this embodiment, the protection wall 311 covers the sidewall of the second source-drain doped layer 611 closest to the second pre-buried power supply layer 151, and therefore, the second source-drain interconnection layer 621 correspondingly covers part of the sidewall of the protection wall 311.

[0073] Therefore, the second source-drain interconnection layer 621 extends from the side of the protection wall 311 facing away from the second source-drain doped layer 611 to the top of the second pre-buried power supply layer 151 in the longitudinal direction.

[0074] In this embodiment, the second source-drain interconnection layer 621 includes a second lateral part 641 extending in the second direction, located in the first interlayer dielectric layer 501, the second lateral part 641 covering the second source-drain doped layer 611 and the protection wall 311; a second longitudinal part 631 extending in the longitudinal direction, located in the first interlayer dielectric layer 501 and the substrate 101 at the bottom of the second lateral part 641, the bottom of the second longitudinal part 631 being connected with the top of the second pre-buried power supply layer 151.

[0075] The second transverse portion 641 electrically connects the second source-drain doped layer 611. The second longitudinal portion 631 is between the bottom of the second transverse portion 641 and the top of the second pre-embedded power supply layer 151. The second longitudinal portion 631 electrically connects the second transverse portion 641 and the second pre-embedded power supply layer 151. The second pre-embedded power supply layer 151 is in the substrate 101. The second longitudinal portion 631 is longitudinally extended to contact the second pre-embedded power supply layer 151, so that the second source-drain interconnection layer 621 is electrically connected to the second pre-embedded power supply layer 151.

[0076] In this embodiment, the second source-drain interconnection layer 621 longitudinally extends through the isolation layer 131 and the first interlayer dielectric layer 501 on the top of the second pre-embedded power supply layer 151.

[0077] In this embodiment, the material of the second source-drain interconnection layer 621 includes W or Co.

[0078] W or Co is a metal material, which has good electrical conductivity and is conducive to the electrical connection between the second source-drain doped layer 611 and the second pre-embedded power supply layer 151.

[0079] In this embodiment, the semiconductor structure further includes a second interlayer dielectric layer 521 between the second transverse portion 641 and the first interlayer dielectric layer 501, and on the top of the isolation layer 171.

[0080] The second interlayer dielectric layer 521 is used to isolate adjacent devices, and also provides a process basis for forming the second gate structure 721 and the second source-drain interconnection layer 621.

[0081] The material of the second interlayer dielectric layer 521 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0082] The protective wall 311 is used to protect the sidewall of the first source-drain doped layer 411.

[0083] In the semiconductor structure provided by the embodiment, the first source-drain interconnection layer 421 extends to the top of the corresponding first pre-buried power supply layer 141 in the longitudinal direction and is electrically connected with the first pre-buried power supply layer 141, the second source-drain interconnection layer 621 covers part of the sidewall of the protection wall 311 and extends to the top of the corresponding second pre-buried power supply layer 151 in the longitudinal direction and is electrically connected with the second pre-buried power supply layer 151, the protection wall 311 is located on the sidewall of the second source-drain doped layer 611 closest to the second pre-buried power supply layer 151 and extends downward to cover the sidewall of the first source-drain doped layer 411, which is beneficial to better protect the first source-drain doped layer 411 and the first source-drain interconnection layer 421 at the side of the second source-drain interconnection layer 621 in the step of forming the second source-drain interconnection layer 621, reduces the probability of contact of the second source-drain interconnection layer 621 with the first source-drain doped layer 411 and the first source-drain interconnection layer 421 due to too close distance, thereby reducing the probability of short circuit of the second source-drain interconnection layer 621 with the first source-drain doped layer 411 or the first source-drain interconnection layer 421, and further ensuring the working performance of the semiconductor structure.

[0084] In the embodiment, in order to increase the distance between the second longitudinal part 631 and the first source-drain doped layer 411 and the first source-drain interconnection layer 421, further reduce the probability of contact of the second source-drain interconnection layer 621 with the first source-drain doped layer 411 and the first source-drain interconnection layer 421 due to too close distance, thereby further reduce the probability of short circuit of the second source-drain interconnection layer 621 with the first source-drain doped layer 411 or the first source-drain interconnection layer 421, the second longitudinal part 631 is spaced apart from the protection wall 311.

[0085] In the embodiment, the material of the protection wall 311 is SiN.

[0086] SiN has high hardness, which is beneficial to better maintain the sidewall of the first source-drain doped layer 411 and the second source-drain doped layer 621 in the manufacturing process, and SiN has good insulation, which can better isolate the second source-drain interconnection layer 621 from the first source-drain doped layer 411 or the first source-drain interconnection layer 421.

[0087] It should be noted that the width of the protection wall 311 along the second direction should not be too large or too small. If the width of the protection wall 311 along the second direction is too large, the second source-drain interconnection layer 621 extends too far along the second direction, which is easy to cause the overall volume of the semiconductor structure to be too large, and the occupation area of the semiconductor structure is wasted. If the width of the protection wall 311 along the second direction is too small, the protection wall 311 is easy to have a weak protection effect on the first source-drain doped layer 411 and the first source-drain interconnection layer 421, thereby easily causing the second source-drain interconnection layer 621 to be too close to the first source-drain doped layer 411 and the first source-drain interconnection layer 421 and short-circuit, which affects the working performance of the semiconductor structure. Therefore, in the embodiment, the width of the protection wall along the second direction is 2nm to 10nm.

[0088] In the embodiment, the semiconductor structure further comprises a gate side wall 321 located on the side wall of the second gate structure 721.

[0089] The gate side wall 321 is used to protect the side wall of the second gate structure 721, and has an isolation effect on the second gate structure 721 and the second source-drain doped layer 611 and the second source-drain interconnection layer 621.

[0090] In the embodiment, the protection wall 311 is formed at the same time in the step of forming the gate side wall 321, and the protection wall 311 and the gate side wall 321 are an integrated structure, thereby improving the process compatibility, simplifying the process flow, and improving the process efficiency.

[0091] Therefore, in the embodiment, the material of the gate side wall 321 is the same as that of the protection wall 311, and the material of the gate side wall 321 is SiN.

[0092] In the embodiment, the semiconductor structure further comprises an inner side wall (not marked) located on the side wall of the first gate structure 711, which is used to protect the side wall of the first gate structure 711 and has an isolation effect on the first gate structure 711 and the first source-drain doped layer 411 and the first source-drain interconnection layer 421.

[0093] Figures 6-20 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure.

[0094] Combined with reference Figure 6 and Figure 7 , Figure 6 is a cross-sectional view of the laminated structure and the pseudo-gate structure, Figure 7 (a) is Figure 6 is a cross-sectional view along the AA direction, Figure 7 (b) is Figure 6A cross-sectional view along the BB direction provides a substrate 100, including a device cell region 100Q for forming a first transistor and a second transistor stacked in sequence from bottom to top, the substrate 100 of the device cell region 100Q is formed with a stack structure 200 extending along a first direction (as indicated by the X direction in the middle) Figure 6 The stack structure 200 includes a first channel layer 210, a sacrificial layer 230 located on the first channel layer 210, and a second channel layer 220 located on the sacrificial layer 230, and in a second direction (as indicated by the Y direction in the middle) Figure 6 The substrate 100 on both sides of the device cell region 100Q is formed with a first pre-embedded power supply layer 140 and a second pre-embedded power supply layer 150, respectively, and the substrate 100 is further formed with a pseudo gate structure 160 across the stack structure 200, and the pseudo gate structure 160 covers part of the sidewall and part of the top of the stack structure 200.

[0095] In this embodiment, the first transistor and the second transistor are stacked from top to bottom, which is beneficial to save the area occupied by the semiconductor structure.

[0096] The semiconductor structure is a complementary field effect transistor structure, in the CFET structure, the PMOS transistor and the NMOS transistor stacked vertically with each other form a complementary device. The first transistor is a bottom transistor in the CFET structure, and the second transistor is a top transistor in the CFET structure. According to the structure type of the first transistor and the second transistor, the first transistor and the second transistor both include fin field effect transistors or all-enclosed gate transistors. Specifically, the GAA transistor can be a horizontal nanosheet transistor. This embodiment takes the first transistor and the second transistor as both FinFETs as an example.

[0097] The substrate 100 is used to provide a process platform for the formation of the semiconductor structure.

[0098] The substrate 100 includes a device cell region 100Q for forming a stacked first transistor and a second transistor.

[0099] In this embodiment, the substrate 101 includes a substrate 110, a bottom fin 120 protruding from the substrate 110 of the device cell region 100Q, and an isolation layer 130 located on the substrate 110 and surrounding the bottom fin 120.

[0100] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials such as indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. As an example, the bottom fin 120 and the substrate 110 are an integral structure.

[0101] In this embodiment, the isolation layer 130 can be a shallow trench isolation structure (STI). The material of the isolation layer 130 is an insulating material. As an example, the material of the isolation layer 130 is silicon oxide.

[0102] The pre-embedded power layers are formed in the substrate 100 on both sides of the device unit region 100Q, which are respectively a first pre-embedded power layer 140 and a second pre-embedded power layer 150.

[0103] The pre-embedded power layers are used for subsequent electrical connection of the first source-drain interconnection layer and the second source-drain interconnection layer respectively, and loading of corresponding voltages for the first source-drain interconnection layer and the second source-drain interconnection layer. The pre-embedded power layer includes an embedded power wiring (VDD) and an embedded ground wiring (VSS).

[0104] In this embodiment, according to the design of the circuit layout, the first pre-embedded power layer 140 is subsequently electrically connected with the first source-drain interconnection layer, and the second pre-embedded power layer 150 is subsequently electrically connected with the second source-drain interconnection layer. In other embodiments, according to process requirements, the first pre-embedded power layer can also be electrically connected with the second source-drain interconnection layer, and the second pre-embedded power layer can also be electrically connected with the first source-drain interconnection layer.

[0105] In this embodiment, the first pre-embedded power layer 140 and the second pre-embedded power layer 150 are located in the substrate 110 and covered by the isolation layer 130, so that the pre-embedded power layer is buried in the substrate 100, and the pre-embedded power layer has a good isolation effect with other film layers above the pre-embedded power layer.

[0106] The stack structure 200 is used to form the first channel layer 210 and the second channel layer 220 which are spaced apart in the longitudinal direction.

[0107] In this embodiment, a plurality of stack structures 200 can be formed in a plurality of regions at the same time, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0108] In this embodiment, the stack structure 200 is formed in the same process as the bottom fin 120, and for this purpose, the stack structure 200 is formed on the bottom fin 120.

[0109] The first channel layer 210 is used to provide a channel of the first transistor.

[0110] In this embodiment, the first channel layer 210 is a first fin standing on the bottom fin 120.

[0111] In this embodiment, the material of the first channel layer 210 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the first channel layer 210 is silicon. In other embodiments, the material of the first channel layer is determined according to the type and performance of the first transistor.

[0112] The second channel layer 220 is configured to provide a channel of the second transistor.

[0113] In this embodiment, the second channel layer 220 is a second fin.

[0114] In this embodiment, the material of the second channel layer 220 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the second channel layer 220 is silicon. In other embodiments, the material of the second channel layer is determined according to the type and performance of the second transistor.

[0115] The sacrificial layer 230 is configured to provide a space between the first channel layer 210 and the second channel layer 220 for forming the stacked first transistor and second transistor, and to provide a space for the first gate structure.

[0116] In this embodiment, the material of the sacrificial layer 230 includes silicon germanium.

[0117] Silicon germanium and silicon can form a large etching selectivity ratio, which is beneficial for subsequent removal of the sacrificial layer 230 and reduces damage to the first channel layer 210 and the second channel layer 220.

[0118] In other embodiments, according to the materials of the first channel layer and the second channel layer, the sacrificial layer can be selected to have a suitable material with etching selectivity ratio with the channel layer, so as to reduce damage to the first channel layer and the second channel layer when the sacrificial layer is subsequently removed.

[0119] The dummy gate structure 160 is configured to provide a space for the second gate structure.

[0120] Specifically, the dummy gate structure 260 is a laminated structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.

[0121] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0122] Continuing to refer to Figure 6 and Figure 7 and referring to Figure 8 , Figure 8 (a) is a cross-sectional view based on Figure 7 (a), Figure 8 (b) is a cross-sectional view based on Figure 7 (b), in which a protective wall 310 is formed closest to the sidewall of the second embedded power layer 150 in the laminated structure 200.

[0123] In the forming method provided in this embodiment, after the protective wall 310 is formed on the sidewall of the second pre-buried power supply layer 150 in the stack structure 200, the stack structure 200 on both sides of the dummy gate structure 160 is removed to form a source-drain recess, then the first source-drain doped layer and the second source-drain doped layer located above the first source-drain doped layer are formed in the source-drain recess, the protective wall 310 covers the sidewall of the second source-drain doped layer closest to the second pre-buried power supply layer 150 and extends downward to cover the sidewall of the first source-drain doped layer, and then the second source-drain interconnection layer covering the second source-drain doped layer is formed, the second source-drain interconnection layer covers part of the sidewall of the protective wall 310 and extends to the top of the second pre-buried power supply layer 150 in the longitudinal direction and is electrically connected with the second pre-buried power supply layer 150. In the step of forming the second source-drain interconnection layer, the protective wall 310 can better protect the first source-drain doped layer and the first source-drain interconnection layer at the side of the second source-drain interconnection layer, thereby reducing the probability of contact between the second source-drain interconnection layer and the first source-drain doped layer or the first source-drain interconnection layer when the second source-drain interconnection layer is formed, and further reducing the probability of short circuit between the second source-drain interconnection layer and the first source-drain doped layer or the first source-drain interconnection layer, thereby ensuring the working performance of the semiconductor structure.

[0124] Correspondingly, in other embodiments, when the second source-drain interconnection layer is electrically connected with the first pre-buried power supply layer, the protective wall is formed on the sidewall of the first pre-buried power supply layer in the stack structure.

[0125] In this embodiment, the material of the protective wall 310 is SiN.

[0126] SiN has high hardness, which is conducive to better maintaining the sidewall of the first source-drain doped layer and the second source-drain doped layer in the subsequent manufacturing process, and SiN has good insulation, which can better isolate the second source-drain interconnection layer from the first source-drain doped layer or the first source-drain interconnection layer.

[0127] It should be noted that the width of the protective wall 310 along the second direction should not be too large or too small. If the width of the protective wall 310 along the second direction is too large, the second source-drain interconnection layer formed subsequently extends too far along the second direction, which is easy to cause the overall volume of the semiconductor structure to be too large and waste the occupied area of the semiconductor structure. If the width of the protective wall 310 along the second direction is too small, the protective wall 310 is easy to have a weak protective effect on the first source-drain doped layer and the first source-drain interconnection layer, thereby causing the second source-drain interconnection layer to be too close to the first source-drain doped layer and the first source-drain interconnection layer to contact, which affects the working performance of the semiconductor structure. Therefore, in this embodiment, the width of the protective wall 310 along the second direction is 2 nm to 10 nm.

[0128] In the embodiment, the forming method further comprises: forming a gate side wall 320 on the sidewall of the dummy gate structure 160, and in the step of forming the gate side wall 320, forming a protection wall 310 on the sidewall of the stack structure 200 closest to the second pre-embedded power supply layer 150, and forming a sacrificial side wall 330 on the remaining sidewalls of the stack structure 200.

[0129] The gate side wall 320 is used to protect the sidewall of the dummy gate structure 160, so as to guarantee the forming quality of the subsequent second gate structure, and after the second gate structure is formed, the sidewall of the second gate structure is protected.

[0130] The sacrificial side wall 330 will be removed subsequently, so as to form the first source-drain interconnection layer.

[0131] In the embodiment, the gate side wall 320 and the protection wall 310 are formed in the same process, so as to improve the process compatibility, simplify the process flow, and improve the process efficiency.

[0132] Therefore, in the embodiment, the material of the gate side wall 320 is the same as that of the protection wall 310, and the material of the gate side wall 320 is SiN; the material of the sacrificial side wall 330 is the same as that of the protection wall 310, and the material of the gate side wall 320 is SiN.

[0133] Specifically, in combination with the description of Figure 10 and Figure 11 , the step of forming the gate side wall 320, the protection wall 310 and the sacrificial side wall 330 comprises: forming a sidewall material layer 300 covering the stack structure 200 and the dummy gate structure 160.

[0134] The sidewall material layer 300 is used to directly form the gate side wall 320, the protection wall 310 and the sacrificial side wall 330.

[0135] In the embodiment, the sidewall material layer 300 also covers the top of the isolation layer 130.

[0136] In the embodiment, the sidewall material layer 300 is formed by using an atomic layer deposition process.

[0137] The sidewall material layer 300 formed by using the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the sidewall material layer 300 can well conformally cover the stack structure 200 and the dummy gate structure 160, and the isolation layer 130.

[0138] For reference Figure 8, the side wall material layer 300 on the top of the stack structure 200 and the top of the dummy gate structure 160 is removed, the side wall material layer 300 covering the side wall of the stack structure 200 closest to the second pre-embedded power supply layer 150 is reserved as a protection wall 310, and the side wall material layer 300 covering the side wall of the dummy gate structure 160 is reserved as a gate side wall 320.

[0139] Correspondingly, in the embodiment, the side wall material layer 300 on the top of the isolation layer 130 is also removed.

[0140] In the embodiment, the side wall material layer 300 covering the remaining side wall of the stack structure 200 is reserved as a sacrifice side wall 330.

[0141] In the embodiment, the side wall material layer 300 on the top of the stack structure 200 and the top of the dummy gate structure 160 is removed by using an anisotropic etching process.

[0142] The anisotropic etching process is an anisotropic dry etching process. By selecting the anisotropic dry etching process, damage to the stack structure 200, the dummy gate structure 160, and the isolation layer 130 can be reduced. In addition, the anisotropic dry etching process has directionality, which can improve the side wall profile quality and size accuracy of the protection wall 310 and the gate side wall 320.

[0143] Correspondingly, in the embodiment, the material of the side wall material layer 300 includes SiN.

[0144] Reference Figure 9 , Figure 9 (a) is a sectional view based on Figure 8 (a), Figure 9 (b) is a sectional view based on Figure 8 (b), after the formation of the protection wall 310, the stack structure 200 on both sides of the dummy gate structure 160 is removed to form a source-drain recess 400.

[0145] The source-drain recess 400 provides a spatial position for subsequent formation of a first source-drain doped layer and a first source-drain interconnection layer.

[0146] In the embodiment, the stack structure 200 exposed by the protection wall 310 and the sacrifice side wall 330 is removed, the source-drain recess 400 is surrounded by the oppositely arranged protection wall 310 and sacrifice side wall 330, and the source-drain recess 400 is also surrounded by the oppositely arranged sacrifice side wall 330.

[0147] The source-drain recess 400 is surrounded by the oppositely arranged protection wall 310 and sacrifice side wall 330, so that the protection wall 310 can cover the side wall of the subsequently formed first source-drain doped layer and second source-drain doped layer.

[0148] In the embodiment, the anisotropic etching process is used to remove the exposed stack structure 200 of the protection wall 310 and the sacrifice wall 330.

[0149] The anisotropic etching process is an anisotropic dry etching process. By selecting the anisotropic dry etching process, the damage to the protection wall 310 can be reduced. In addition, the anisotropic dry etching process has directionality, which can help to maintain the good morphology and size accuracy of the side wall of the protection wall 310 and the end of the stack structure 200 after the exposed stack structure 200 of the protection wall 310 and the sacrifice wall 330 is removed.

[0150] In the embodiment, after the source-drain recess 400 is formed, an inner side wall (not shown) is formed on the side wall of the sacrifice layer 230 through the source-drain recess 400, which is used to protect the side wall of the sacrifice layer 230, so as to ensure the formation quality of the first gate structure, and the side wall of the first gate structure is protected after the first gate structure is formed.

[0151] Specifically, the step of forming the inner side wall includes: removing part of the width of the sacrifice layer 230 along the first direction to form a recess; and forming the inner side wall in the recess.

[0152] Reference Figure 10 , Figure 10 (a) is a sectional view based on Figure 9 (a), Figure 10 (b) is a sectional view based on Figure 9 (b), and the first source-drain doped layer 410 is formed in the source-drain recess 400 and is in contact with the end of the first channel layer 210 located below the dummy gate structure 160.

[0153] The first source-drain doped layer 410 is used as a source region or a drain region of the first transistor.

[0154] The end refers to the end of the first channel layer 210 along the first direction. In the source-drain recess 400, the first source-drain doped layer 410 is epitaxially grown based on the first channel layer 210. Therefore, in the embodiment, the first source-drain doped layer 410 is in contact with the end of the first channel layer 210 in the step of forming the first source-drain doped layer 410.

[0155] It should be noted that in the step of forming the first source-drain doped layer 410, the material used to form the first source-drain doped layer 410 also grows on the end of the second channel layer 220. Then, a protection layer (for example, a spin-on carbon layer) is formed in the source-drain recess 400 to cover the first source-drain doped layer 410. Then, the material on the end of the second channel layer 220 is removed, and then the protection layer is removed, and finally the first source-drain doped layer 410 is formed.

[0156] The doping type of the first source-drain doping layer 410 is the same as the channel conduction type of the corresponding transistor, specifically, the first transistor is an NMOS transistor, and the doping ions in the first source-drain doping layer 410 are N-type ions, including P ions, As ions or Sb ions.

[0157] Referring to Figure 11 , Figure 11 (a) is a cross-sectional view based on Figure 10 (a), Figure 11 (b) is a cross-sectional view based on Figure 10 (b), after forming the first source-drain doping layer 410, before subsequently removing the sacrificial side wall 330, further comprising: forming a first interlayer dielectric layer 500 covering the protection wall 310, the sacrificial side wall 330 and the first source-drain doping layer 410, the first interlayer dielectric layer 500 also covering the sidewall of the gate side wall 320.

[0158] The first interlayer dielectric layer 500 serves to isolate adjacent devices, and also serves to provide a process basis for subsequently forming the first gate structure, the second gate structure, the first source-drain interconnection layer, and the second source-drain interconnection layer.

[0159] The material of the first interlayer dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0160] Referring to Figure 12 , Figure 12 is a cross-sectional view based on Figure 11 (a), on both sides of the dummy gate structure 160, the first interlayer dielectric layer 500 at the position of the protection wall 310 is removed, forming a first opening 510 exposing the first source-drain doping layer 410 and the sacrificial side wall 330.

[0161] The first opening 510 provides a spatial position for the subsequent formation of the first source-drain interconnection layer, and exposes the first source-drain doping layer 410, so that the subsequently formed first source-drain interconnection layer is in contact with the first source-drain doping layer 410, the first opening 510 also exposes the sacrificial side wall 330, providing a process basis for removing the sacrificial side wall 330, and protecting the protection wall 310 in the subsequent step of removing the sacrificial side wall 330.

[0162] In this embodiment, the first opening 510 extends along the second direction and extends above the top of the first embedded power supply layer 140, so that the subsequently formed first source-drain interconnection layer can extend longitudinally to the top of the first embedded power supply layer 140.

[0163] Referring to Figure 13 , Figure 13 (a) is a cross-sectional view based on Figure 12 , Figure 13(b) is based on Figure 11 (b) is based on

[0164] The removal of the sacrificial side wall 330 prepares for the subsequent formation of the first source-drain interconnection layer.

[0165] In this embodiment, the isotropic etching process is used to remove the sacrificial side wall 330.

[0166] The isotropic etching process has etching rates in both longitudinal and transverse directions, so it is easy to remove the protruding sacrificial side wall 330 completely. Moreover, the isotropic etching process includes an isotropic wet etching process, which has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which is conducive to reducing damage to the first source-drain doped layer 410 during the removal of the sacrificial side wall 330.

[0167] In this embodiment, the first opening 510 exposes the sacrificial side wall 330.

[0168] The first interlayer dielectric layer 500 covers the protection wall 310, and the first opening 510 only exposes the sacrificial side wall 330. By removing the sacrificial side wall 330 through the first opening 510, it is beneficial to protect the protection wall 310 and avoid damage to the protection wall 310 as much as possible.

[0169] Referring to Figure 13 (b), in this embodiment, after the formation of the first opening 510, the first interlayer dielectric layer 500 also covers the top and sidewall of the dummy gate structure 160, and the first interlayer dielectric layer 500 also covers the gate side wall. It is beneficial to protect the dummy gate structure 160 and the gate side wall during the removal of the sacrificial side wall 330, and to protect the sidewall and top of the dummy gate structure 160 during the subsequent formation of the first source-drain interconnection layer, and to lay a foundation for the subsequent formation of the second gate structure.

[0170] Referring to Figure 14 , Figure 14 (a) is based on Figure 13 (a) is based on Figure 14 (b) is based on Figure 13 (b) is based on Figure 14 The first source-drain interconnection layer 420 also extends to the top of the corresponding first pre-embedded power supply layer 140 in the longitudinal direction (as indicated by the Z direction in the figure) and is electrically connected with the first pre-embedded power supply layer 140.

[0171] The first source-drain interconnection layer 420 is used to electrically connect the first pre-embedded power supply layer 140 and the first source-drain doped layer 410, and to apply a voltage to the first source-drain doped layer 410.

[0172] In this embodiment, according to the design of the circuit layout, the first source-drain interconnection layer 420 extends to the top of the corresponding first pre-embedded power supply layer 140 and is electrically connected with the first pre-embedded power supply layer 140. In other embodiments, according to the process requirements, the first source-drain interconnection layer can also extend to the top of the second pre-embedded power supply layer and be electrically connected with the second pre-embedded power supply layer.

[0173] In this embodiment, the step of forming the first source-drain interconnection layer 420 includes: forming a first interconnection through hole (not shown in the figure) in the substrate 100 at the side of the first source-drain doped layer 410, the top of the first interconnection through hole is in communication with the bottom of the first opening 510, and the first interconnection through hole exposes the top of the first pre-embedded power supply layer 140; forming the first source-drain interconnection layer 420 covering the first source-drain doped layer 410 in the partial depth region of the first opening 510, and the first source-drain interconnection layer 420 also fills in the first interconnection through hole.

[0174] The first pre-embedded power supply layer 140 is located in the substrate 100, and the first interconnection through hole is located on the first pre-embedded power supply layer 140. By forming the first interconnection through hole extending in the longitudinal direction to expose the first pre-embedded power supply layer 140 and then filling the first interconnection through hole, the first source-drain interconnection layer 420 is in contact with the first pre-embedded power supply layer 140, and the first source-drain interconnection layer 420 is electrically connected with the first pre-embedded power supply layer 140.

[0175] Therefore, in this embodiment, the first interconnection through hole penetrates the isolation layer 130 at the top of the first pre-embedded power supply layer 140 in the longitudinal direction and exposes the top of the first pre-embedded power supply layer 140, and correspondingly, the first source-drain interconnection layer 420 penetrates the isolation layer 130 at the top of the first pre-embedded power supply layer 140 in the longitudinal direction.

[0176] In this embodiment, the material of the first source-drain interconnection layer 420 includes W or Co.

[0177] W or Co is a metal material and has good electrical conductivity, which is conducive to better electrical connection between the first source-drain doped layer 410 and the first pre-embedded power supply layer 140.

[0178] Reference Figure 15 , Figure 15 (a) is a sectional view based on Figure 14 (a), Figure 15 (b) is a sectional view based on Figure 14 (b), and the isolation layer 170 covering the top of the first source-drain interconnection layer 420 is formed, and the isolation layer 170 exposes the end of the second channel layer 220.

[0179] The end of the second channel layer 220 refers to the end of the second channel layer 220 in the first direction.

[0180] The isolation layer 170 is used to isolate the first source-drain interconnection layer 420 and the second source-drain doped layer formed subsequently on the isolation layer 170, and also to isolate the first source-drain interconnection layer 420 and the second source-drain interconnection layer formed subsequently on the isolation layer 170.

[0181] The isolation layer 170 is also used as an etching stop position for subsequent formation of the second opening.

[0182] The isolation layer 170 exposes the end of the second channel layer 220, which is conducive to the subsequent formation of the second source-drain doped layer in contact with the end of the second channel layer 220.

[0183] In the embodiment, the first source-drain interconnection layer 420 is formed in the first opening 510, and accordingly, the isolation layer 170 is formed on the top of the first source-drain interconnection layer 420 exposed by the first opening 510.

[0184] In the embodiment, the material of the isolation layer 170 includes SiN, SiON, SiOCN, SiOC or SiOCH. SiN, SiON, SiOCN, SiOC or SiOCH has good insulating properties and can achieve good isolation effect.

[0185] Specifically, the step of forming the isolation layer 170 on the top of the first source-drain interconnection layer 420 exposed by the first opening 510 includes: forming an isolation material layer (not shown) covering the bottom and sidewall of the first opening 510 and the top of the first interlayer dielectric layer 500; removing the isolation material layer located on the sidewall of the first opening 510 and the top of the first interlayer dielectric layer 500, and retaining the isolation material layer located on the top of the first source-drain interconnection layer 420 exposed by the first opening 510 as the isolation layer 170.

[0186] Reference Figure 16 , Figure 16 (a) is a sectional view based on Figure 15 (a), Figure 16 (b) is a sectional view based on Figure 15 (b), after the formation of the isolation layer 170 and before the subsequent formation of the second source-drain doped layer, further comprising: forming a second interlayer dielectric layer 520 in the remaining space of the first opening 510.

[0187] The second interlayer dielectric layer 520 is used to isolate adjacent devices, and the second interlayer dielectric layer 520 is also used to provide a process basis for subsequent formation of the second gate structure and the second source-drain interconnection layer.

[0188] The material of the second interlayer dielectric layer 520 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0189] Reference Figure 17 ,Figure 17 (a) is based on Figure 16 (a) is a cross-sectional view, Figure 17 (b) is based on Figure 16 (b) is a cross-sectional view, on both sides of the dummy gate structure 160, the adjacent part of the first interlayer dielectric layer 500 and the second interlayer dielectric layer 520 are removed to form the second opening 530 which exposes the end of the second channel layer 220 and the protection wall 310.

[0190] The end of the second channel layer 220 exposed by the second opening 530 is prepared for the subsequent formation of the second source / drain doped layer, and the second opening 530 also provides a spatial position for the subsequent formation of the second source / drain interconnection layer and makes the subsequently formed second source / drain interconnection layer contact the second source / drain doped layer.

[0191] In this embodiment, the second opening 530 extends along the second direction and extends above the top of the second pre-embedded power supply layer 150, so that the subsequently formed second source / drain interconnection layer can extend longitudinally to the top of the second pre-embedded power supply layer 150.

[0192] In this embodiment, the first opening 510 extends along the second direction and extends above the top of the first pre-embedded power supply layer 140, and the second opening 530 extends along the second direction and extends above the top of the second pre-embedded power supply layer 150. In this embodiment, after forming the second interlayer dielectric layer 520 in the remaining space of the first opening 510, the second opening 530 is formed. The same mask used to form the first opening 510 can be used to form the second opening 530, saving process cost.

[0193] Reference Figure 18 , Figure 18 (a) is based on Figure 17 (a) is a cross-sectional view, Figure 18 (b) is based on Figure 17 (b) is a cross-sectional view, the second source / drain doped layer 610 is formed on the isolation layer 170 on both sides of the dummy gate structure 160, and the second source / drain doped layer 610 contacts the end of the second channel layer 220 located below the dummy gate structure 160.

[0194] The second source / drain doped layer 610 is used as a source region or a drain region of the second transistor.

[0195] In the second opening 530, the second source / drain doped layer 610 is epitaxially grown based on the second channel layer 220, so in this embodiment, in the step of forming the second source / drain doped layer 610, the second source / drain doped layer 610 contacts the end of the second channel layer 220.

[0196] The doping type of the second source / drain doped layer 610 is the same as the channel conductivity type of the corresponding transistor. Specifically, the second transistor is a PMOS transistor, and the doping ions in the second source / drain doped layer 610 are P-type ions, including B ions, Ga ions, or In ions.

[0197] In this embodiment, a second source / drain doped layer 610 is formed in the second opening 530, protruding from the isolation layer 170.

[0198] refer to Figure 19 , Figure 19 (a) is based on Figure 18 (a) is a sectional view. Figure 19 (b) is based on Figure 18 (b) is a cross-sectional view showing a second source-drain interconnect layer 620 that covers the second source-drain doped layer 610 and the protective wall 310 located on the sidewall of the second source-drain doped layer 610. The second source-drain interconnect layer 620 also extends longitudinally to the top of the corresponding second embedded power layer 150 and is electrically connected to the second embedded power layer 150.

[0199] The second source-drain interconnect layer 620 is used to electrically connect the second buried power layer 150 and the second source-drain doped layer 610, thereby applying voltage to the second source-drain doped layer 610 through the second buried power layer 150.

[0200] In this embodiment, according to the designed circuit layout, the second source-drain interconnect layer 620 extends to the top of the corresponding second embedded power layer 150 and is electrically connected to the second embedded power layer 150. In other embodiments, according to process requirements, the second source-drain interconnect layer may also extend to the top of the first embedded power layer and be electrically connected to the first embedded power layer. Correspondingly, the protective wall is located on the sidewall of the second source-drain doped layer closest to the first embedded power layer and extends downward to cover the sidewall of the first source-drain doped layer.

[0201] In this embodiment, the protective wall 310 covers the sidewall of the second source / drain doped layer 610 that is closest to the second embedded power layer 150. Therefore, the second source / drain interconnect layer 620 covers a portion of the sidewall of the protective wall 310 accordingly.

[0202] In the embodiment, the step of forming the second source-drain interconnection layer 620 covering the second source-drain doped layer 610 includes: forming a second interconnection through hole (not shown in the figure) penetrating the first interlayer dielectric layer 500 and the substrate 100 on the side of the protection wall 310 facing away from the second source-drain doped layer 610, the top of the second interconnection through hole is in communication with the bottom of the second opening 530, and the second interconnection through hole exposes the top of the first pre-embedded power supply layer 150; forming the second source-drain interconnection layer 620 covering the second source-drain doped layer 610 and the protection wall 310 in the remaining space of the second opening 530, and the second source-drain interconnection layer 620 also fills in the second interconnection through hole.

[0203] The second pre-embedded power supply layer 150 is located in the substrate 100, so that the second pre-embedded power supply layer 150 is exposed by forming the second interconnection through hole extending longitudinally, and the second source-drain interconnection layer 620 is filled in the second interconnection through hole so as to be in contact with the second pre-embedded power supply layer 150, and the second source-drain interconnection layer 620 is electrically connected with the second pre-embedded power supply layer 150.

[0204] Therefore, in the embodiment, the second source-drain interconnection layer 620 longitudinally penetrates the isolation layer 130 and the first interlayer dielectric layer 500 on the top of the second pre-embedded power supply layer 150.

[0205] In the embodiment, when the second interconnection through hole is formed, the protection wall 310 preferably protects the first source-drain doped layer 410 and the first source-drain interconnection layer 420 on the side of the second interconnection through hole, so as to reduce the probability of exposing the first source-drain doped layer 410 or the first source-drain interconnection layer 420 due to being too close to the first source-drain doped layer 410 or the first source-drain interconnection layer 420 when the second interconnection through hole is formed, thereby reducing the probability of short circuiting with the first source-drain doped layer 410 or the first source-drain interconnection layer 420 when the second source-drain interconnection layer 620 is formed, and further ensuring the working performance of the semiconductor structure.

[0206] Reference Figure 20 , Figure 20 (a) is a sectional view based on Figure 19 (a), Figure 20 (b) is a sectional view based on Figure 19 (b), and after the second source-drain interconnection layer 620 is formed, the forming method further includes: removing the dummy gate structure 160 to form a gate opening (not shown in the figure) exposing the sacrificial layer 230.

[0207] The gate opening provides a spatial position for subsequent formation of the second gate structure, and also prepares for removal of the sacrificial layer 230.

[0208] In the embodiment, the sacrificial layer 230 is removed through the gate opening to form a through slot (not shown in the figure) surrounded by the first channel layer 210 and the second channel layer 220.

[0209] The through slot provides a spatial position for forming the first gate structure.

[0210] In this embodiment, the first gate structure 710 spanning the first channel layer 210 is formed through the gate opening and the through slot, the first gate structure 710 covering the top and sidewall of the first channel layer 210; the second gate structure 720 spanning the second channel layer 220 is formed on the first gate structure 710 through the gate opening, the second gate structure 720 covering the top and sidewall of the second channel layer 220.

[0211] Specifically, a first gate structure material layer spanning the first channel layer 210 is filled in the gate opening and the through slot; a partial thickness of the first gate structure material layer is etched to expose the second channel layer 220, the remaining first gate structure material layer is reserved as the first gate structure 710, the top surface of the first gate structure 710 being lower than the bottom surface of the second channel layer 220; the second gate structure 720 spanning the second channel layer 220 is formed on the first gate structure 710.

[0212] The first gate structure 710 is used to control the opening and closing of the channel of the first transistor, and the second gate structure 720 is used to control the opening and closing of the channel of the second transistor.

[0213] The first gate structure 710 and the second gate structure 720 each include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0214] The gate dielectric layer is used to isolate the gate electrode layer from the first channel layer 210 and the substrate 100, and is also used to isolate the gate electrode layer from the second channel layer 220 and the first gate structure 710. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0215] It should be noted that the gate dielectric layer can also include a gate oxide layer, the gate oxide layer being located between the high-k gate dielectric layer and the first channel layer 210, and also being located between the high-k gate dielectric layer and the second channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0216] In this embodiment, the first gate structure 710 and the second gate structure 720 are metal gate structures, and thus the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0217] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0218] In other embodiments, the gate electrode layer can also only include the work function layer.

[0219] In other embodiments, the first gate structure can also be a polysilicon gate structure according to the process requirement.

[0220] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and thus the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a device unit region for forming a first transistor and a second transistor stacked in sequence from bottom to top; a pre-embedded power supply layer in the substrate on both sides of the device unit region in a second direction, comprising a first pre-embedded power supply layer on one side of the device unit region and a second pre-embedded power supply layer on the other side of the device unit region; a first transistor on the substrate in the device unit region, the first transistor comprising a first channel layer extending along a first direction, a first gate structure crossing the first channel layer and covering the top and sidewall of the first channel layer, and a first source-drain doped layer on the substrate on both sides of the first gate structure, the first source-drain doped layer being in contact with the end of the first channel layer under the first gate structure, the second direction being perpendicular to the first direction; a first source-drain interconnection layer covering the first source-drain doped layer, the first source-drain interconnection layer further extending from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and being electrically connected with the first pre-embedded power supply layer; an insulating layer on the top of the first source-drain interconnection layer; a second transistor stacked above the first transistor, the second transistor comprising a second channel layer extending along the first direction, a second gate structure crossing the second channel layer and covering the second channel layer, and a second source-drain doped layer on the insulating layer on both sides of the second gate structure, the second source-drain doped layer being in contact with the end of the second channel layer under the second gate structure; a protection wall on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer and extending downward to cover the sidewall of the first source-drain doped layer; a second source-drain interconnection layer covering the second source-drain doped layer and part of the sidewall of the protection wall, the second source-drain interconnection layer further extending from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and being electrically connected with the second pre-embedded power supply layer.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first interlayer dielectric layer on the substrate and covering the sidewall of the first source-drain interconnection layer, the sidewall of the first gate structure, the sidewall of the second gate structure, and part of the sidewall of the protection wall; the first source-drain interconnection layer comprises: a first lateral portion extending along the second direction in the first interlayer dielectric layer, the first lateral portion covering the first source-drain doped layer; a first longitudinal portion extending longitudinally in the substrate on the side of the first source-drain doped layer, the top of the first longitudinal portion being connected with the bottom of the first lateral portion, and the bottom of the first longitudinal portion being connected with the top of the first pre-embedded power supply layer; the insulating layer is in the first interlayer dielectric layer and covers the top of the first source-drain interconnection layer; The second source-drain interconnection layer comprises a second lateral portion extending along the second direction, located in the first interlayer dielectric layer, covering the second source-drain doped layer and the protection wall located on the sidewall of the second source-drain doped layer; a second longitudinal portion extending longitudinally, located in the first interlayer dielectric layer and the substrate at the bottom of the second lateral portion, and connected to the top of the second pre-embedded power supply layer.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises a second interlayer dielectric layer located between the second lateral portion and the first interlayer dielectric layer, and located on the top of the isolation layer.

4. The semiconductor structure of claim 2, wherein, The second longitudinal portion is spaced apart from the protection wall.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a gate sidewall located on the sidewall of the gate structure. The protection wall and the gate sidewall are in an integrated structure.

6. The semiconductor structure of claim 1, wherein, The substrate comprises a substrate, a bottom fin portion of the substrate protruding in the device unit area, and an isolation layer located on the substrate and surrounding the bottom fin portion; The pre-embedded power supply layer is located in the substrate and covered by the isolation layer; The first channel layer is located on the bottom fin portion; The first source-drain interconnection layer longitudinally penetrates the isolation layer on the top of the first pre-embedded power supply layer; The second source-drain interconnection layer longitudinally penetrates the isolation layer on the top of the second pre-embedded power supply layer.

7. The semiconductor structure of claim 1, wherein, The material of the isolation layer comprises SiN, SiON, SiOCN, SiOC or SiOCH.

8. The semiconductor structure of claim 1, wherein, The material of the protection wall is SiN.

9. The semiconductor structure of claim 1, wherein, The width of the protection wall along the second direction is 2nm to 10nm.

10. The semiconductor structure of claim 1, wherein, The material of the first source-drain interconnection layer comprises W or Co; and the material of the second source-drain interconnection layer comprises W or Co.

11. The semiconductor structure of claim 1, wherein, The material of the first channel layer comprises silicon, germanium, silicon germanium or group III-V semiconductor material; and the material of the second channel layer comprises silicon, germanium, silicon germanium or group III-V semiconductor material.

12. The semiconductor structure of claim 1, wherein, The first gate structure and the second gate structure each comprise a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; and the material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

13. A method of forming a semiconductor structure, comprising: Comprise: A substrate is provided, comprising a device unit area for forming a first transistor and a second transistor stacked from bottom to top, a stack structure extending in a first direction is formed on the substrate of the device unit area, the stack structure comprises a first channel layer, a sacrificial layer located on the first channel layer, and a second channel layer located on the sacrificial layer, in a second direction, a first pre-embedded power supply layer and a second pre-embedded power supply layer are respectively formed in the substrate on both sides of the device unit area, the second direction is perpendicular to the first direction, a pseudo gate structure is also formed on the substrate, which spans the stack structure, and the pseudo gate structure covers part of the sidewall and part of the top of the stack structure; A protection wall is formed on the sidewall of the stack structure closest to the second pre-embedded power supply layer; After the protective wall is formed, the stack structure on both sides of the dummy gate structure is removed to form source-drain recesses; A first source-drain doped layer is formed in the source-drain recesses, and the first source-drain doped layer is in contact with the end of the first channel layer under the dummy gate structure; A first source-drain interconnection layer covering the first source-drain doped layer is formed, and the first source-drain interconnection layer also extends to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and is electrically connected with the first pre-embedded power supply layer; An isolation layer covering the top of the first source-drain interconnection layer is formed, and the isolation layer exposes the end of the second channel layer; A second source-drain doped layer is formed on the isolation layer on both sides of the dummy gate structure, and the second source-drain doped layer is in contact with the end of the second channel layer under the dummy gate structure; A second source-drain interconnection layer covering the second source-drain doped layer and the protective wall on the sidewall of the second source-drain doped layer is formed, and the second source-drain interconnection layer also extends to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and is electrically connected with the second pre-embedded power supply layer.

14. The method of forming a semiconductor structure of claim 13, wherein, The forming method further comprises: forming a gate sidewall on the sidewall of the dummy gate structure, and in the step of forming the gate sidewall, a protective wall is formed on the sidewall of the stack structure closest to the second pre-embedded power supply layer, and a sacrificial sidewall is formed on the remaining sidewalls of the stack structure; In the step of removing the stack structure on both sides of the dummy gate structure, the stack structure exposed by the protective wall and the sacrificial sidewall is removed, and the source-drain recesses are surrounded by the oppositely arranged protective wall and sacrificial sidewall; After the first source-drain doped layer is formed, before the first source-drain interconnection layer covering the first source-drain doped layer is formed, the method further comprises: removing the sacrificial sidewall.

15. The method of forming a semiconductor structure of claim 14, wherein, The steps of forming the gate sidewall, the protective wall and the sacrificial sidewall comprise: forming a sidewall material layer covering the stack structure and the dummy gate structure; The sidewall material layer on the top of the stack structure and the top of the dummy gate structure is removed, the sidewall material layer covering the sidewall of the stack structure closest to the second pre-embedded power supply layer is retained as the protective wall, and the sidewall material layer covering the sidewall of the dummy gate structure is retained as the gate sidewall.

16. The method of forming a semiconductor structure of claim 14, wherein, After the first source-drain doped layer is formed, before the sacrificial sidewall is removed, the method further comprises: forming a first interlayer dielectric layer covering the protective wall, the sacrificial sidewall and the first source-drain doped layer, and the first interlayer dielectric layer also covers the sidewall of the gate sidewall; On both sides of the dummy gate structure, part of the first interlayer dielectric layer is removed to form a first opening exposing the first source-drain doped layer and the sacrificial sidewall; The sacrificial sidewall exposed by the first opening is removed.

17. The method of forming a semiconductor structure of claim 16, wherein, In the step of forming the first opening, the first opening extends in the second direction and extends above the top of the first pre-embedded power supply layer; The step of forming the first source-drain interconnection layer includes: forming a first interconnection via in the base on the side of the first source-drain doped layer, the top of the first interconnection via is communicated with the bottom of the first opening, and the first interconnection via exposes the top of the first pre-embedded power supply layer; forming a first source-drain interconnection layer covering the first source-drain doped layer in the partial depth region of the first opening, and the first source-drain interconnection layer also fills in the first interconnection via; The isolation layer is formed on the top of the first source-drain interconnection layer exposed by the first opening.

18. The method of forming a semiconductor structure of claim 16, wherein, On both sides of the dummy gate structure, the first interlayer dielectric layer at the position of the protection wall is removed to form a second opening exposing the end of the second channel layer and the protection wall; In the second opening, a second source-drain doped layer standing on the isolation layer is formed; The step of forming the second source-drain interconnection layer includes: forming a second interconnection via penetrating the first interlayer dielectric layer and the base on the side of the protection wall away from the second source-drain doped layer and exposing the top of the first pre-embedded power supply layer, the top of the second interconnection via is communicated with the bottom of the second opening; forming a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall in the remaining space of the second opening, and the second source-drain interconnection layer also fills in the second interconnection via.

19. The method of forming a semiconductor structure of claim 18, wherein, After the isolation layer is formed and before the second source-drain doped layer is formed, a second interlayer dielectric layer is formed in the remaining space of the first opening; The step of forming the second opening exposing the end of the second channel layer and the protection wall includes: removing the adjacent part of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides of the dummy gate structure and at the position of the protection wall.

20. The method of forming a semiconductor structure according to any one of claims 13 to 16, wherein In the step of providing the base, the base includes a substrate, a bottom fin of the substrate standing in the device unit area, and an isolation layer located on the substrate and surrounding the bottom fin, the first pre-embedded power supply layer and the second pre-embedded power supply layer are formed in the substrate and covered by the isolation layer; The stack structure is formed on the bottom fin; In the step of forming the first source-drain interconnection layer, the first source-drain interconnection layer penetrates the isolation layer on the top of the first pre-embedded power supply layer; In the step of forming the second source-drain interconnection layer, the second source-drain interconnection layer penetrates the isolation layer on the top of the second pre-embedded power supply layer.

21. The method of forming a semiconductor structure of claim 14, wherein, The isotropic etching process is used to remove the sacrificial side wall.

Images