A tappered gate MOSFET device structure and method of fabrication thereof

Abstract

This invention discloses a tapered gate MOSFET device structure and its fabrication method. The device structure includes a device structure layer disposed on a substrate, and a source, drain, and gate that cooperate with the device structure layer. A groove cooperating with the gate is also formed on the device structure layer. The groove includes a first portion and a second portion, which are sequentially arranged along a direction away from the surface of the device structure layer. The sidewall of the first portion is perpendicular to the surface of the device structure layer, and the sidewall of the second portion forms an angle greater than 30° and less than 60° with the surface of the device structure layer. The bottom surface of the second portion is the bottom wall of the groove, and the bottom wall of the groove is parallel to the surface of the device structure layer. The tapered gate MOSFET device structure of this invention exhibits high reverse breakdown voltage and good forward conduction performance.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a tapered gate MOSFET device structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is one of the third-generation wide bandgap semiconductors. It has many outstanding and unique electrical, mechanical and chemical properties, such as a large bandgap, high electron and hole mobility, extremely high hardness, high wear resistance, high quality factor Q, high thermal conductivity and high chemical corrosion resistance, which makes it have broad application prospects in high-power, high-temperature and high-frequency power electronics.

[0003] The SiC UMOSFET (U Metal-Oxide-Semiconductor Field-Effect Transistor) device structure is characterized by a U-shaped trench gate with the channel perpendicular to the device surface, effectively eliminating the internal JFET (Junction Field-Effect Transistor) resistance. Under the same conditions, the on-resistance of the UMOSFET structure is significantly reduced. Furthermore, both the channel and source regions of the UMOSFET structure can be formed through epitaxial growth, avoiding the adverse effects of ion implantation, thus giving the SiC UMOSFET structure a greater advantage and enabling the achievement of lower on-resistance.

[0004] However, the SiC UMOSFET structure also has a significant inherent problem: in the blocking state, the electric field strength of the gate dielectric layer at the bottom of the UMOSFET trench is extremely high, approximately 2.5 times the peak electric field strength of its PN junction. At the corner of the trench bottom, due to the two-dimensional effect, the electric field is even more concentrated, resulting in an even higher electric field strength. This makes the gate dielectric layer at the trench corner of the SiC UMOSFET device more prone to breakdown first, leading to a decrease in device reliability. Most solutions involve placing an electric field shielding structure at the bottom of the trench, ensuring it is tightly attached to the trench bottom. However, when the device is in forward conduction, the depletion regions of the two PN junctions formed between the base region and drift region, and between the electric field shielding structure and the drift region, expand, forming a JFET region. The presence of the JFET narrows the current conduction path, thereby reducing the current carrying capacity.

[0005] Therefore, how to provide a solution that can prevent the gate dielectric layer at the bottom of the groove from breaking down without introducing a new JFET region or expanding the JFET region is an urgent problem to be solved. Summary of the Invention

[0006] The main objective of this invention is to provide a tapered gate MOSFET device structure and its fabrication method to overcome the shortcomings of the prior art.

[0007] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0008] This invention provides a tapered gate MOSFET device structure, comprising:

[0009] Device structure layer disposed on substrate, and

[0010] The device structure layer includes a source, a drain, and a gate that cooperate with the device structure layer, and a groove that cooperates with the gate is also formed on the device structure layer.

[0011] The groove includes a first part and a second part, which are arranged sequentially along a direction away from the surface of the device structure layer. The sidewall of the first part is perpendicular to the surface of the device structure layer. The sidewall of the second part forms an angle greater than 30° and less than 60° with the surface of the device structure layer. The bottom surface of the second part is the bottom wall of the groove, which is parallel to the surface of the device structure layer.

[0012] This invention also provides a method for fabricating the above-described tapered gate MOSFET device structure, comprising:

[0013] A device structure layer is formed on the first surface of the substrate;

[0014] A groove is formed in the device structure layer, and the sidewall of the first part of the groove is perpendicular to the surface of the device structure layer, the sidewall of the second part forms an angle greater than 30 and less than 60° with the surface of the device structure layer, and the bottom wall of the second part is parallel to the surface of the device structure layer.

[0015] Fabrication of the gate, source, and drain; and

[0016] A shielding layer is formed in the drift region of the device structure layer, and the shielding layer is distributed on both sides of the groove.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] (1) A tapered gate MOSFET device structure and its fabrication method are provided. The trench is designed into two parts, with the sidewall of the first part perpendicular to the device surface, the sidewall of the second part at a certain angle to the device surface, and the bottom surface of the second part parallel to the device surface. At the same time, an electric field shielding structure is set on both sides of the sidewall of the second part of the trench. While significantly increasing the forward conduction current density of the device, it also achieves a reverse breakdown voltage of 1345V. Furthermore, under a reverse blocking voltage of 1200V, the gate dielectric electric field strength is 3.05MV / cm, and the device has high reliability.

[0019] (2) A tapered gate MOSFET device structure and its fabrication method are provided. Due to its high current density, the same current output capability can be obtained using fewer cells in actual device fabrication. The reduction in cell density also results in a relatively smaller gate area, reducing the gate-drain capacitance C. D This reduces drive losses and increases switching speed.

[0020] (3) A tapered gate MOSFET device structure and its fabrication method are provided, wherein a current spreading layer is provided between the drift region and the base region of the device, so that electrons can spread laterally when leaving the channel, thereby avoiding the PN junction formed by direct contact between the base region and the drift region from affecting the current channel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a tapered gate MOSFET device structure in a typical embodiment of the present invention;

[0023] Figures 2a to 2k This is a schematic diagram illustrating the fabrication process of a tapered gate MOSFET device structure in a typical embodiment of the present invention. Detailed Implementation

[0024] In view of the deficiencies of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. Addressing the issue that existing trench gate MOSFET devices reduce the forward conduction capability by introducing a new JFET region while lowering the electric field strength of the gate dielectric layer at the bottom of the trench, this invention provides a tapered gate MOSFET device structure. The trench gate is a tapered structure composed of two parts. The sidewall of the first part is perpendicular to the device surface, and the sidewall of the second part forms a certain angle with the device surface. The channel region of the device is formed on the vertical plane of the trench gate. Simultaneously, electric field shielding structures are provided on both sides of the bottom of the trench to reduce the electric field strength of the gate dielectric within the trench, achieving a compromise between the reverse blocking capability and the forward conduction capability of the device. This maximizes the reverse breakdown voltage of the device while increasing the width of the JFET region, thereby reducing the forward conduction resistance and increasing the output current of the device.

[0025] The technical solutions of this invention will be described in a clearer and more detailed manner below.

[0026] One aspect of this invention provides a tapered gate MOSFET device structure, comprising:

[0027] Device structure layer disposed on substrate, and

[0028] The device structure layer includes a source, a drain, and a gate that cooperate with the device structure layer, and a groove that cooperates with the gate is also formed on the device structure layer.

[0029] The groove includes a first part and a second part, which are arranged sequentially along a direction away from the surface of the device structure layer. The sidewall of the first part is perpendicular to the surface of the device structure layer. The sidewall of the second part forms an angle greater than 30° and less than 60° with the surface of the device structure layer. The bottom surface of the second part is the bottom wall of the groove, which is parallel to the surface of the device structure layer.

[0030] Since the first part of the groove is a vertical structure and the second part is an inclined structure, and the conductive channel of the device is formed on the side wall of the first part, when the MOSFET device is forward-biased, when the current flows downward out of the vertical channel, it can flow quickly downward along the inclined surface into the drift region, and will not accumulate at the corner of the bottom of the groove.

[0031] Furthermore, the device structure layer includes a drift region and a base region sequentially disposed on the first surface of the substrate, and a first ohmic contact region and a second ohmic contact region are disposed on the base region; wherein the substrate, the drift region, and the first ohmic contact region are all of a first conductivity type, and the base region and the second ohmic contact region are both of a second conductivity type.

[0032] Furthermore, if either the first conductivity type or the second conductivity type is P-type and the other is N-type, the corresponding MOSFET device is a P-channel MOSFET device or an N-channel MOSFET device.

[0033] Furthermore, the device structure layer also includes a current spreading layer of a first conductivity type, which is disposed between the drift region and the base region.

[0034] Furthermore, the second portion of the groove is disposed within the drift region.

[0035] Furthermore, a shielding layer is also provided in the drift region, and the shielding layer is disposed between the groove and the substrate.

[0036] Furthermore, the shielding layer is located on both sides of the groove and close to the sidewall of the second part of the groove. When the MOSFET device is forward-biased, a strong electric field is formed between the shielding layer and the inclined sidewall of the groove, where electrons can obtain a higher drift velocity.

[0037] Furthermore, the base region, the first ohmic contact region, the second ohmic contact region, the current spreading layer, and the shielding layer are all formed by transforming local areas of the drift region.

[0038] Furthermore, the sides of the first ohmic contact area and the second ohmic contact area are in contact, and the source electrode is disposed on the surface of the first ohmic contact area and the second ohmic contact area.

[0039] Furthermore, the groove is filled with polysilicon, the gate is disposed on the polysilicon, and a gate dielectric layer is disposed between the polysilicon and the groove.

[0040] Furthermore, the drain is disposed on the second surface of the substrate.

[0041] Furthermore, the substrate includes a silicon carbide substrate.

[0042] This invention also provides a method for fabricating the aforementioned tapered gate MOSFET device structure, comprising:

[0043] A device structure layer is formed on the first surface of the substrate;

[0044] A groove is formed in the device structure layer, wherein the sidewall of the first portion of the groove is perpendicular to the surface of the device structure layer, the sidewall of the second portion forms an angle greater than 30° and less than 60° with the surface of the device structure layer, and the bottom wall of the second portion is parallel to the surface of the device structure layer; and

[0045] Fabricate the gate, source, and drain.

[0046] Furthermore, the manufacturing method further includes: forming a shielding layer in the drift region of the device structure layer, and distributing the shielding layer on both sides of the groove.

[0047] Furthermore, the manufacturing method specifically includes:

[0048] A first drift region is formed on the first surface of the substrate by epitaxy;

[0049] A shielding layer is formed on both sides of the first drift region by ion implantation;

[0050] The second drift region is epitaxially grown on the first drift region;

[0051] In the second drift region, a current spreading layer, a base region, and a first ohmic contact region are formed sequentially from bottom to top by ion implantation, and a second ohmic contact region is formed in the first ohmic contact region. The upper surfaces of the first ohmic contact region and the second ohmic contact region are flush with the upper surface of the second drift region.

[0052] A mask is applied to the upper surface of the second drift region, and the first etching is performed to form the second part of the groove. The mask is then removed.

[0053] A mask is then applied again to the upper surface of the second drift region, and a second etching is performed to cause the second part of the groove to move downward synchronously, thus forming the first part of the groove.

[0054] A gate dielectric layer is formed on the inner wall of the groove by high-temperature dry oxygen oxidation and then annealed at high temperature. Polycrystalline silicon is then deposited in the groove and activated at high temperature to make the polycrystalline silicon conductive.

[0055] The gate, source, and drain are formed by magnetron sputtering.

[0056] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the materials and processing technology of the MOSFET devices involved in the embodiments of the present invention are known to those skilled in the art.

[0057] Please see Figure 1A tapered gate MOSFET device structure includes a silicon carbide N+ substrate 11 and a device structure layer sequentially formed on the silicon carbide N+ substrate 11. The device structure layer includes an N-type drift region 10, an N+ type current spreading layer 6, and a P+ type base region 5 sequentially stacked on a first surface of the silicon carbide N+ substrate 11. An N+ type ohmic contact region 4 and P+ type ohmic contact regions 3 distributed on both sides of the N+ type ohmic contact region 4 are formed on the P+ type base region 5, and the sides of the N+ type ohmic contact region 4 and the P+ type ohmic contact region 3 are in contact. A groove 13 is also formed in the device structure layer. The groove 13 includes a first part 131 and a second part 132. The sidewall of the first part 131 is perpendicular to the surface of the device structure layer, the sidewall of the second part 132 has a 45-degree angle with the device surface, and the bottom surface of the second part 132 is the bottom wall of the groove and is parallel to the device surface.

[0058] Specifically, the first part 131 of the groove 13 passes through the N+ type ohmic contact region 4 and the P+ type base region 5 in sequence along the thickness direction of the device structure layer and extends partially into the N- type drift region 10, while the first part 132 of the groove 13 is completely disposed in the N- type drift region 10.

[0059] Specifically, a P+ shielding layer 9 is also formed in the N-type drift region 10, wherein the P+ shielding layer 9 is distributed on both sides of the sidewall of the second part 132 of the groove 13.

[0060] Specifically, in this embodiment, the channel region of the MOSFET device structure is formed in the P+ type base region 5 and near the sidewall of the first portion 131 of the groove 13. This channel is a vertical channel. When the device is forward-biased, as the current flows downward out of the vertical channel, it can quickly flow down the slope of the second portion 132 of the groove 13 into the drift region 10, avoiding the phenomenon of electrons accumulating at the bottom of the flat-bottomed trench as seen in conventional device structures. Furthermore, when the device is forward-biased, a strong electric field is formed between the P+ shielding layer 9 and the sloped gate bottom, allowing electrons to achieve a higher drift velocity. Moreover, when the device is reverse-biased, the P+ shielding layer 9 can shield the electric field, providing excellent protection for the gate dielectric.

[0061] Specifically, an N+ type current extension layer 6 is distributed between the P+ type base region 5 and the N- type drift region 10, which allows electrons to expand laterally when exiting the channel, thus preventing the PN junction formed by the direct contact between the P+ type base region 5 and the N- type drift region 10 from affecting the current channel.

[0062] Specifically, the interior of the groove 11 is filled with polysilicon 7, and a gate dielectric layer 8 is formed between the polysilicon 7 and the entire inner wall of the groove 11, and a gate 1 is formed on the polysilicon 7.

[0063] Specifically, an active electrode 2 is formed on the surface of the P+ type ohmic contact region 3 and the N+ type ohmic contact region 4 and on both sides of the gate 1, and a drain electrode 12 is formed on the second surface of the silicon carbide N+ type substrate 11.

[0064] In this embodiment of the MOSFET device, only one PN junction, consisting of the P+ type shielding layer 9 and the N-type drift region 10, is formed between the sidewalls of the second portion 132 of the groove 13, without forming a JFET region. The JFET is formed only between the two P+ shielding layers 9, and this JFET is relatively wide, having little impact on the on-resistance. Furthermore, a high electric field is formed between the P+ type shielding layer 9 and the sidewalls of the second portion 132 of the groove 13, which increases the electron drift velocity during forward conduction, improving the device's forward conduction performance. Compared to conventional silicon carbide UMOSFETs, the device in this embodiment has a wider current path. Simulation results show that the on-resistance of the device can be reduced by 12.1% compared to a conventional P+ type UMOSFET (from 1.82 mΩ·cm). 2 Reduced to 1.60 mΩ·cm 2 The forward conduction current density can be increased by 46.6% (from 3.20e-4A / μm). 2 Increased to 4.69e-4A / μm 2 ).

[0065] Specifically, the fabrication method of this tapered gate MOSFET device structure includes:

[0066] 1) A first portion of an N-type drift region 10 is formed epitaxially on the first surface of a silicon carbide N+ substrate 11. The N- doping concentration is 8 × 10⁻⁶. 15 cm -3 ,like Figure 2a As shown;

[0067] 2) A patterned silicon dioxide mask 14 is deposited on the upper surface of the first N-type drift region 10, and a P+ type shielding layer 9 is formed by implanting aluminum ions 15. The silicon dioxide mask 14 is then removed. The aluminum ion doping concentration is 1 × 10⁻⁶. 19 cm -3 ,like Figure 2b As shown;

[0068] 3) On the first N-type drift region 10, a second N-type drift region 10 with the same doping concentration as the first N-type drift region 10 is formed epitaxially, such as... Figure 2c As shown;

[0069] 4) An N+ type current extension layer 6 is formed in the second N-type drift region 10 by implanting nitrogen ions 16. The nitrogen ion doping concentration is 1 × 10⁻⁶. 17cm -3 ,like Figure 2d As shown;

[0070] 5) A P+ type base region 5 is formed in the second N-type drift region 10 above the P+ type current extension layer 6 by implanting aluminum ions 15. The aluminum ion doping concentration is 2 × 10⁻⁶. 17 cm -3 ,like Figure 2e As shown;

[0071] 6) An N+ type ohmic contact region 4 is formed in the second N- type drift region 10 above the P+ type base region 5 by implanting nitrogen ions 16, so that the upper surface of the N+ type ohmic contact region 4 is flush with the upper surface of the second N- type drift region 10. The nitrogen ion doping concentration is 1 × 10⁻⁶. 19 cm -3 ,like Figure 2f As shown;

[0072] 7) A patterned silicon dioxide mask 17 is deposited on the upper surface of the second N-type drift region 10, and P+-type ohmic contact regions 3 are formed on both sides of the N+-type ohmic contact region 4 by implanting aluminum ions 15. Then the silicon dioxide mask 142 is removed, wherein the aluminum ion doping concentration is 1×10⁻⁶. 19 cm -3 ,like Figure 2g As shown;

[0073] 8) A patterned mask is set on the upper surface of the second part N-type drift region 10. Figure 2g (Not shown in the image), exposing the corresponding area of ​​the groove 13 opening, and performing a first etching to form the second part 132 of the groove 13. The etching depth is 1 μm, and the sidewalls of the second part 132 are made at a 45-degree angle to the plane where the device is located. The mask is then removed. The mask can be photoresist or other masks with a low etch selectivity to silicon carbide, which helps to form the inclined sidewalls of the second part 132, such as... Figure 2h As shown.

[0074] 9) A patterned mask is then set again on the upper surface of the second part, the N-type drift region 10. Figure 2h (Not shown in the image), exposing the corresponding area of ​​the groove 13 opening, and performing a second etching to a depth of 1.7 μm. During this etching process, the sidewalls of the second portion 132 formed above will move downwards synchronously, ultimately forming the first portion 131 of the groove 13. The mask can be a silicon dioxide mask, or other masks with a high etching selectivity to silicon carbide, which helps to form the vertical sidewalls of the first portion 131, such as... Figure 2i As shown.

[0075] 10) A gate dielectric layer 8 is formed on the inner wall of the formed groove 13 by high-temperature dry oxygen oxidation. The thickness of the gate dielectric layer 8 on the vertical surface is 50 nm, and the material of the gate dielectric layer 8 can be silicon dioxide. Then, high-temperature nitrous oxide annealing is used to reduce the interface state density at the silicon carbide-silicon dioxide interface. Figure 2j As shown.

[0076] 11) Polycrystalline silicon 7 is deposited in the groove 13 and etched to obtain the desired polycrystalline silicon structure. The deposited polycrystalline silicon 7 is then heavily p-doped and subjected to high-temperature activation annealing to make the polycrystalline silicon 7 conductive, such as... Figure 2k As shown.

[0077] 12) Gate 1, source 2, and drain 12 are formed by magnetron sputtering, followed by high-temperature annealing to form an ohmic alloy, thus completing the device fabrication. The ohmic contact metals of source 2 and drain 12 are Ni / Al alloys, with the Al metal thickened. The ohmic contact metal of gate 1 is Al. Figure 1 As shown.

[0078] In addition, the inventors of this case also conducted experiments with other raw materials, process operations, and process conditions described in this specification, referring to the aforementioned embodiments, and obtained relatively ideal results in all cases.

[0079] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.

Claims

1. A tapered gate MOSFET device structure, comprising: The device structure layer includes a drift region (10) and a base region (5) sequentially disposed on the first surface of a substrate (11). A first ohmic contact region (4) and a second ohmic contact region (3) are disposed on the base region (5). The substrate (11), the drift region (10), and the first ohmic contact region (4) are all of the first conductivity type. The base region (5) and the second ohmic contact region (3) are all of the second conductivity type. The substrate (11) is a silicon carbide substrate. The device structure layer includes a source (2), a drain (12), and a gate (1), and a groove (13) is formed on the device structure layer to cooperate with the gate (1). Polysilicon (7) is filled in the groove (13), and the gate (1) is disposed on the polysilicon (7); A gate dielectric layer (8) is disposed between the polysilicon (7) and the groove (13); The groove (13) is characterized in that: the groove (13) includes a first part and a second part, the first part and the second part are arranged sequentially along the direction away from the surface of the device structure layer, the second part is arranged in the drift region (10), the sidewall of the first part is arranged perpendicular to the surface of the device structure layer, the sidewall of the second part forms an angle greater than 30 and less than 60° with the surface of the device structure layer, the bottom surface of the second part is the bottom wall of the groove, and the bottom wall of the groove is arranged parallel to the surface of the device structure layer; The gate dielectric layer (8) has a first region, a second region and a third region, wherein the first region is disposed on the sidewall of the first part of the groove (13), the second region is disposed on the sidewall of the second part of the groove (13), and the third region is disposed on the bottom surface of the second part of the groove (13), and the thickness of the first region is less than the thickness of the second region and the thickness of the third region. A current spreading layer (6) of the first conductivity type is provided between the drift region (10) and the base region (5). A shielding layer (9) is also provided in the drift region (10). The shielding layer (9) is provided between the groove (13) and the substrate (11) and is located on both sides of the groove (13).

2. The tapered gate MOSFET device structure according to claim 1, characterized in that: Either the first conductivity type or the second conductivity type is P-type, and the other is N-type.

3. The tapered gate MOSFET device structure according to any one of claims 1-2, characterized in that: The base region (5), the first ohmic contact region (4), the second ohmic contact region (3), the current extension layer (6), and the shielding layer (9) are all formed by transforming a local area of ​​the drift region (10).

4. The tapered gate MOSFET device structure according to claim 1, characterized in that: The first ohmic contact area (4) and the second ohmic contact area (3) are in contact with each other on their sides, and the source electrode is disposed on the surface of the first ohmic contact area (4) and the second ohmic contact area (3).

5. The tapered gate MOSFET device structure according to claim 1, characterized in that: The drain (12) is disposed on the second surface of the substrate (11).

6. A method for fabricating a tapered gate MOSFET device structure as described in any one of claims 1-5, characterized in that, include: A first portion of the drift region (10) is formed epitaxially on the first surface of the substrate (11); A shielding layer (9) is formed on both sides of the first drift region (10) by ion implantation. The second part of the drift region (10) is epitaxially grown on the first drift region (10); In the second drift region (10), a current spreading layer (6), a base region (5) and a first ohmic contact region (4) are formed sequentially from bottom to top by ion implantation, and a second ohmic contact region (3) is formed in the first ohmic contact region (4). The upper surfaces of the first ohmic contact region (4) and the second ohmic contact region (3) are flush with the upper surface of the second drift region (10), thereby forming a device structure layer. A mask is applied to the upper surface of the second drift region (10), and a first etching is performed to form the second part of the groove (13), after which the mask is removed; A mask is applied again to the upper surface of the second drift area (10), and a second etching is performed to make the second part of the groove (13) move down synchronously to form the first part of the groove (13); A gate dielectric layer (8) is formed on the inner wall of the groove (13) by high-temperature dry oxygen oxidation, and the interface state density of silicon carbide and silicon dioxide is reduced by high-temperature nitric oxide annealing. Then, polysilicon (7) is deposited in the groove (13) and high-temperature activation annealing is performed to make the polysilicon (7) conductive. The gate (1), source (2) and drain (12) are formed by magnetron sputtering of metal.

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