Enhanced semiconductor structure and method of making the same

Abstract

The application provides an enhanced semiconductor structure and a manufacturing method thereof. The enhanced semiconductor structure comprises a semiconductor substrate and a heterojunction structure arranged from bottom to top. The heterojunction structure comprises a channel layer close to the semiconductor substrate and a first barrier layer away from the semiconductor substrate. The heterojunction structure comprises a gate region and source and drain regions on both sides of the gate region. The channel layer and the first barrier layer of the gate region are sandwiched by an intermediate layer, and the intermediate layer is adapted to make the contacted first barrier layer non-polarized. According to an embodiment of the application, when no opening voltage is applied on the gate, the intermediate layer causes the first barrier layer thereon to be unable to produce a polarization effect, and the gate region is unable to produce a two-dimensional electron gas, so that the device can be realized as always off. When the opening voltage is applied on the gate, the first barrier layer of the gate region can produce a polarization effect, and thus the gate region can produce a two-dimensional electron gas, so that the device can be realized as on. In addition, the control ability of the gate to the channel is strong.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an enhanced semiconductor structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) is a representative of third-generation wide-bandgap semiconductors and is attracting widespread attention. Its superior performance is mainly reflected in its high electron mobility and high two-dimensional electron gas (2DEG) concentration. In addition, gallium nitride (GaN) materials are chemically stable, heat-resistant, and corrosion-resistant, giving them inherent advantages in high-frequency, high-power, and radiation-resistant applications.

[0003] High electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions have been widely used in the semiconductor field. These devices have characteristics such as high reverse blocking voltage, low forward on-resistance, and high operating frequency, thus meeting the system requirements for higher power, higher frequency, and smaller size operation of semiconductor devices.

[0004] HEMT devices typically employ a p-type semiconductor layer to deplete the two-dimensional electron gas beneath the gate, achieving normal-off operation. However, traditional p-type ions, such as Mg doping, only achieve an activation efficiency of around 2% after activation, thus requiring high-concentration Mg doping (>1e19cm). -3 This is achieved by using Mg doping to create a P-type semiconductor layer. Furthermore, Mg doping exhibits a self-compensating effect; if the Mg doping concentration continues to increase, the hole concentration in the P-type semiconductor layer will actually decrease.

[0005] To solve the above problems, the thickness of the P-type semiconductor layer must be increased to provide a higher hole concentration to deplete the two-dimensional electron gas beneath the gate, thus enabling the device to be normally off. However, excessive thickness of the P-type semiconductor layer reduces the gate's control over the channel, degrading device performance. Summary of the Invention

[0006] The purpose of this invention is to provide an enhanced semiconductor structure and its fabrication method, which enables the device to be normally off while maintaining strong gate control over the channel.

[0007] To achieve the above objectives, a first aspect of the present invention provides an enhanced semiconductor structure, comprising:

[0008] A semiconductor substrate and a heterojunction structure distributed from bottom to top, the heterojunction structure including a channel layer close to the semiconductor substrate and a first barrier layer away from the semiconductor substrate; the heterojunction structure including a gate region and source and drain regions located on both sides of the gate region, an intermediate layer sandwiched between the channel layer and the first barrier layer of the gate region, the intermediate layer being adapted to depolarize the first barrier layer it contacts.

[0009] Optionally, the intermediate layer is an amorphous layer, and the material of the amorphous layer is at least one of silicon nitride, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride.

[0010] Optionally, the intermediate layer is a polycrystalline layer, and the material of the polycrystalline layer is at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride.

[0011] Optionally, the channel layer is made of gallium nitride-based material, and the first barrier layer is made of aluminum-containing gallium nitride-based material, aluminum nitride, or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer.

[0012] Optionally, the thickness of the intermediate layer is greater than 0.2 nm.

[0013] Optionally, the thickness ratio of the first barrier layer to the intermediate layer is less than 50:1.

[0014] Optionally, the heterojunction structure further includes: a second barrier layer sandwiched between the channel layer and the first barrier layer, wherein the channel layer is made of gallium nitride-based material, the second barrier layer is made of aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, the thickness of the second barrier layer is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer is less than 10%; and the intermediate layer is sandwiched between the first barrier layer and the second barrier layer in the gate region.

[0015] Optionally, the heterojunction structure further includes: a second barrier layer sandwiched between the channel layer and the first barrier layer, wherein the channel layer is made of gallium nitride-based material, the second barrier layer is made of aluminum nitride, and the thickness of the second barrier layer is less than 10 nm; and the intermediate layer is sandwiched between the first barrier layer and the second barrier layer in the gate region.

[0016] Optionally, the enhanced semiconductor structure further includes: a gate structure located on the gate region, and source and drain located on both sides of the gate structure.

[0017] Optionally, the enhanced semiconductor structure further includes a passivation layer disposed between the gate structure and the source and between the gate structure and the drain.

[0018] Optionally, the gate structure is a stacked structure of a gate insulating layer and a gate, or includes only a gate. Optionally, the source and the drain are in contact with the channel layer or the first barrier layer.

[0019] A second aspect of the present invention provides a method for fabricating an enhanced semiconductor structure, comprising:

[0020] A semiconductor substrate is provided, on which a channel layer is formed;

[0021] An intermediate layer is formed in a portion of the channel layer; a first barrier layer is formed on the intermediate layer and the channel layer exposed by the intermediate layer; the channel layer, the intermediate layer, and the first barrier layer form a heterojunction structure, the heterojunction structure including a gate region and source and drain regions located on both sides of the gate region, the intermediate layer being sandwiched between the channel layer and the first barrier layer in the gate region, and the intermediate layer being adapted to depolarize the first barrier layer it contacts.

[0022] Optionally, the intermediate layer is an amorphous layer, and the material of the amorphous layer is at least one of silicon nitride, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride, and is formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0023] Optionally, the intermediate layer is a polycrystalline layer, and the material of the polycrystalline layer is at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride.

[0024] Optionally, the thickness of the intermediate layer is greater than 0.2 nm.

[0025] Optionally, the thickness ratio of the first barrier layer to the intermediate layer is less than 50:1.

[0026] Optionally, before the step of forming the intermediate layer, the method for fabricating the enhanced semiconductor structure further includes: forming a second barrier layer on the channel layer, wherein the material of the channel layer is a gallium nitride-based material, the material of the second barrier layer is an aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, the thickness of the second barrier layer is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer is less than 10%;

[0027] The intermediate layer is formed on a portion of the second barrier layer, and the first barrier layer is formed on the intermediate layer and the second barrier layer exposed by the intermediate layer; the channel layer, the second barrier layer, the intermediate layer and the first barrier layer form the heterojunction structure, and the intermediate layer is sandwiched between the first barrier layer and the second barrier layer in the gate region.

[0028] Optionally, before the step of forming the intermediate layer, the method for fabricating the enhanced semiconductor structure further includes: forming a second barrier layer on the channel layer, wherein the channel layer is made of gallium nitride-based material, the second barrier layer is made of aluminum nitride, and the thickness of the second barrier layer is less than 10 nm.

[0029] The intermediate layer is formed on a portion of the second barrier layer, and the first barrier layer is formed on the intermediate layer and the second barrier layer exposed by the intermediate layer; the channel layer, the second barrier layer, the intermediate layer and the first barrier layer form the heterojunction structure, and the intermediate layer is sandwiched between the first barrier layer and the second barrier layer in the gate region.

[0030] Optionally, a gate structure is formed on the gate region; and a source and a drain are formed on both sides of the gate structure.

[0031] Optionally, the gate structure is a stacked structure of a gate insulating layer and a gate, or it may only include a gate.

[0032] Optionally, the source and the drain are in contact with the channel layer or the first barrier layer.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] In a heterojunction structure, an intermediate layer is sandwiched between the channel layer and the first barrier layer in the gate region. When no turn-on voltage is applied to the gate, the intermediate layer prevents the first barrier layer above it from generating a polarization effect, and the gate region cannot generate a two-dimensional electron gas, thus enabling the device to be normally off. When a turn-on voltage is applied to the gate, the first barrier layer in the gate region can generate a polarization effect, thus enabling the generation of a two-dimensional electron gas in the gate region, thereby enabling the device to be turned on. Furthermore, the first barrier layer needs to be relatively thin to cause it to become non-polarized, thus giving the gate strong control over the channel. Attached Figure Description

[0035] Figure 1 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the first embodiment of the present invention;

[0036] Figure 2 yes Figure 1 A flowchart of the fabrication method for the enhanced semiconductor structure;

[0037] Figure 3 and Figure 4 yes Figure 2 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0038] Figure 5 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the second embodiment of the present invention;

[0039] Figure 6 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the third embodiment of the present invention;

[0040] Figure 7This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the fourth embodiment of the present invention;

[0041] Figure 8 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the fifth embodiment of the present invention;

[0042] Figure 9 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the sixth embodiment of the present invention.

[0043] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0044] Semiconductor substrate 10 Heterojunction structure 11

[0045] Channel layer 111 First barrier layer 112

[0046] Gate region 11a Source region 11b

[0047] Leakage area 11c, intermediate layer 12

[0048] Passivation layer 13 Second barrier layer 113

[0049] Gate structure 14a Source 14b

[0050] Drain 14c, Gate insulating layer 14d

[0051] Gate 14e enhancement-mode semiconductor structures 1, 2, 3, 4, 5, 6 Detailed Implementation

[0052] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a cross-sectional schematic diagram of the enhanced semiconductor structure according to the first embodiment of the present invention.

[0054] Reference Figure 1 As shown, the enhanced semiconductor structure 1 includes:

[0055] The semiconductor substrate 10 and the heterojunction structure 11 are distributed from bottom to top. The heterojunction structure 11 includes a channel layer 111 close to the semiconductor substrate 10 and a first barrier layer 112 away from the semiconductor substrate 10. The heterojunction structure 11 includes a gate region 11a and a source region 11b and a drain region 11c located on both sides of the gate region 11a. An intermediate layer 12 is sandwiched between the channel layer 111 and the first barrier layer 112 of the gate region 11a. The intermediate layer 12 is adapted to depolarize the first barrier layer 112 it contacts.

[0056] The gate structure 14a is located on the gate region 11a, and the source 14b and drain 14c are located on both sides of the gate structure 14a.

[0057] The semiconductor substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, or diamond.

[0058] Reference Figure 1 As shown, the heterojunction structure 11 includes a channel layer 111 close to the semiconductor substrate 10 and a first barrier layer 112 away from the semiconductor substrate 10. A two-dimensional electron gas can be formed at the interface between the channel layer 111 and the first barrier layer 112.

[0059] Both the channel layer 111 and the first barrier layer 112 can be made of III-V group compound materials, with the bandgap of the first barrier layer 112 being larger than that of the channel layer 111. The first barrier layer 112 can be made of an aluminum-based gallium nitride material, aluminum nitride, or a multilayer structure formed by an aluminum-based gallium nitride material layer and an aluminum nitride layer. The channel layer 111 can be made of a gallium nitride-based material, such as GaN. The aluminum-based gallium nitride material can be, for example, AlGaN or AlInGaN.

[0060] In a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, for example, but not limited to, the thickness of the AlGaN layer is 0.8 nm and the thickness of the aluminum nitride layer is 0.2 nm.

[0061] In one alternative, the intermediate layer 12 can be an amorphous layer, and the material of the amorphous layer can be at least one of silicon nitride, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride.

[0062] In another alternative, the intermediate layer 12 can be a polycrystalline layer, and the material of the polycrystalline layer can be at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride.

[0063] The thickness of the intermediate layer 12 can be greater than 0.2 nm. When the thickness of the intermediate layer 12 is less than 0.2 nm, i.e. too thin, it is insufficient to make the first barrier layer 112 amorphous or polycrystalline. Preferably, the thickness of the intermediate layer 12 can be greater than 1 nm. More preferably, the thickness of the intermediate layer 12 can be greater than 5 nm.

[0064] In this embodiment, the gate structure 14a includes only the gate 14e. The materials of the gate 14e, source 14b, and drain 14c can be metals, such as Ti / Al / Ni / Au, Ni / Au, etc. A Schottky contact can be formed between the gate 14e and the heterojunction structure 11, and ohmic contacts can be formed between the source 14b and the source region 11b, and between the drain 14c and the drain region 11c.

[0065] In this embodiment, when no turn-on voltage is applied to the gate 14e, the intermediate layer 12, whether it is amorphous or polycrystalline, can cause the first barrier layer 112 on it to become non-polarized, that is, it cannot generate a polarization effect. The gate region 11a cannot generate a two-dimensional electron gas, thereby enabling the enhancement semiconductor structure 1 to be normally off.

[0066] When a turn-on voltage is applied to the gate 14e, the first barrier layer 112 of the gate region 11a can generate a polarization effect, thereby generating a two-dimensional electron gas in the gate region 11a, which enables the conduction of the enhancement semiconductor structure 1.

[0067] The thickness ratio of the first barrier layer 112 to the intermediate layer 12 can be less than 50:1 to ensure that when no turn-on voltage is applied to the gate 14e, the intermediate layer 12 will cause the first barrier layer 112 thereon to become non-polarized, preventing the first barrier layer 112 from generating a polarization effect when it is too thick.

[0068] In the enhanced semiconductor structure 1, when the intermediate layer 12 causes the first barrier layer 112 on it to become non-polar, the thickness of the first barrier layer 112 needs to be thinner, so the gate 14e has a strong control over the channel.

[0069] The first embodiment of the present invention also provides Figure 1 A method for fabricating enhanced semiconductor structures. Figure 2 It is a flowchart of the production method; Figure 3 and Figure 4 yes Figure 2 The diagram shows the intermediate structure corresponding to the process flow.

[0070] First, refer to Figure 2 Step S1 and Figure 3 As shown, a semiconductor substrate 10 is provided, on which a channel layer 111 is formed.

[0071] The semiconductor substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, or diamond.

[0072] The material of the channel layer 111 can be a gallium nitride-based material, such as GaN.

[0073] The channel layer 111 can be epitaxially grown on the semiconductor substrate 10 using MOCVD (Metal-organic Chemical Vapor Deposition) technology. Before epitaxially growing the channel layer 111, a nucleation layer and a buffer layer can be epitaxially grown sequentially on the semiconductor substrate 10. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 111, and the semiconductor substrate 10, while the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0074] Next, refer to Figure 2 Step S2 and Figure 3 As shown, an intermediate layer 12 is formed in a portion of the channel layer 111; refer to Figure 4 As shown, a first barrier layer 112 is formed on the intermediate layer 12 and the channel layer 111 exposed by the intermediate layer 12; the channel layer 111, the intermediate layer 12 and the first barrier layer 112 form a heterojunction structure 11, the heterojunction structure 11 includes a gate region 11a and a source region 11b and a drain region 11c located on both sides of the gate region 11a, the intermediate layer 12 is sandwiched between the channel layer 111 and the first barrier layer 112 of the gate region 11a, and the intermediate layer 12 is adapted to depolarize the first barrier layer 112 it contacts.

[0075] The intermediate layer 12 can be an amorphous layer, and the material of the amorphous layer can be at least one of silicon nitride, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride, and it can be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The intermediate layer 12 can also be a polycrystalline layer, and the material of the polycrystalline layer can be at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride, and it can be formed by epitaxial growth. The intermediate layer 12 can be formed on the entire surface of the channel layer 111 first, and then patterned by dry etching or wet etching, retaining only a portion of the gate region 11a.

[0076] The thickness of the intermediate layer 12 can be greater than 0.2 nm. Preferably, the thickness of the intermediate layer 12 can be greater than 1 nm. More preferably, the thickness of the intermediate layer 12 can be greater than 5 nm.

[0077] The material of the first barrier layer 112 can be a III-V group compound material, and the band gap of the first barrier layer 112 is larger than the band gap of the channel layer 111. When the material of the channel layer 111 is a gallium nitride-based material, such as GaN, the material of the first barrier layer 112 can be an aluminum-containing gallium nitride-based material, aluminum nitride, or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer. The aluminum-containing gallium nitride-based material is, for example, AlGaN or AlInGaN.

[0078] The formation process of the first barrier layer 112 can refer to the formation process of the channel layer 111.

[0079] The thickness ratio of the first barrier layer 112 to the intermediate layer 12 can be less than 50:1.

[0080] Then, refer to Figure 2 Step S3 and Figure 1 As shown, a gate structure 14a is formed on the gate region 11a, and a source 14b and a drain 14c are formed on both sides of the gate structure 14a.

[0081] In this embodiment, the gate structure 14a includes only the gate 14e, while the source 14b and drain 14c are both in contact with the first barrier layer 112. The materials of the gate 14e, source 14b, and drain 14c can be metals, such as Ti / Al / Ni / Au, Ni / Au, etc., which can be formed by sputtering first and then patterned by etching.

[0082] A Schottky contact can be formed between the gate 14e and the heterojunction structure 11, and an Ohmic contact can be formed between the source 14b and the source region 11b, and between the drain 14c and the drain region 11c.

[0083] In this embodiment, when no turn-on voltage is applied to the gate 14e, the intermediate layer 12, whether it is amorphous or polycrystalline, can cause the first barrier layer 112 on it to become non-polarized, that is, it cannot generate a polarization effect. The gate region 11a cannot generate a two-dimensional electron gas, thereby enabling the enhancement semiconductor structure 1 to be normally off.

[0084] When a turn-on voltage is applied to the gate 14e, the first barrier layer 112 of the gate region 11a can generate a polarization effect, thereby generating a two-dimensional electron gas in the gate region 11a, which enables the conduction of the enhancement semiconductor structure 1.

[0085] In this embodiment, the sidewall of the gate 14e can be aligned with the sidewall of the intermediate layer 12, or it can be slightly wider than the sidewall of the intermediate layer 12.

[0086] Figure 5 This is a schematic cross-sectional view of the enhanced semiconductor structure according to the second embodiment of the present invention. (Refer to...) Figure 5As shown, the only difference between the enhanced semiconductor structure 2 in this embodiment and the enhanced semiconductor structure 1 in this embodiment is that the gate structure 14a is a stacked structure of the gate insulating layer 14d and the gate 14e. In other words, the enhanced semiconductor structure 2 is a MIS HEMT transistor.

[0087] In this embodiment, the two sides of the gate insulating layer 14d are aligned with the two sides of the gate 14e. In other embodiments, the gate insulating layer 14d may also extend between the source 14b and the drain 14c.

[0088] Apart from the differences mentioned above, the other structures of the enhanced semiconductor structure 2 in this embodiment 2 can refer to the corresponding structures of the enhanced semiconductor structure 1 in embodiment 1.

[0089] Accordingly, the difference between the fabrication method of the enhanced semiconductor structure 2 in this embodiment and the fabrication method of the enhanced semiconductor structure 1 in embodiment 1 is only that: in step S3, the gate structure 14a formed on the gate region 11a is a stacked structure of the gate insulating layer 14d and the gate 14e.

[0090] Specifically, step S3 may include: first forming a gate insulating material on the entire surface of the first barrier layer 112, then patterning it to retain only the gate insulating material in the gate region 11a to form a gate insulating layer 14d; then forming a metal layer on the entire surface using a sputtering method, and then patterning it using an etching method to form a gate 14e, a source 14b and a drain 14c.

[0091] Apart from the differences mentioned above, the other steps of the fabrication method of the enhanced semiconductor structure 2 in this embodiment can refer to the corresponding steps of the fabrication method of the enhanced semiconductor structure 1 in embodiment 1.

[0092] Figure 6 This is a schematic cross-sectional view of the enhanced semiconductor structure according to the third embodiment of the present invention. (Refer to...) Figure 6 As shown, the difference between the enhanced semiconductor structure 3 and its fabrication method in this embodiment 3 and the enhanced semiconductor structures 1 and 2 and their fabrication methods in embodiments 1 and 2 is only that the source 14b and the drain 14c are both in contact with the channel layer 111.

[0093] Figure 7 This is a schematic cross-sectional view of the enhanced semiconductor structure according to the fourth embodiment of the present invention. (Refer to...) Figure 7 As shown, the difference between the enhanced semiconductor structure 4 in this embodiment 4 and the enhanced semiconductor structures 1, 2, and 3 in embodiments 1 to 3 is only that the enhanced semiconductor structure 4 further includes a passivation layer 13, which is disposed between the gate structure 14a and the source 14b and between the gate structure 14a and the drain 14c.

[0094] In other words, the gate structure 14a is located within the passivation layer 13 on the gate region 11a, and the source 14b and drain 14c are located within the passivation layers 13 on both sides of the gate structure 14a.

[0095] The material of the passivation layer 13 can be silicon nitride or silicon dioxide.

[0096] Apart from the differences mentioned above, the other structures of the enhanced semiconductor structure 4 in this embodiment four can refer to the corresponding structures of the enhanced semiconductor structures 1, 2, and 3 in embodiments one to three.

[0097] Accordingly, the fabrication method of the enhanced semiconductor structure 4 in this embodiment 4 differs from the fabrication methods of the enhanced semiconductor structures 1, 2, and 3 in embodiments 1 to 3 only in that: in step S3, a) a passivation layer 13 is formed on the gate structure 14a, source 14b, drain 14c and the heterojunction structure 11 exposed by the gate structure 14a, source 14b, and drain 14c; the passivation layer 13 is planarized or a window is formed in the passivation layer 13 to expose the gate structure 14a, source 14b and drain 14c.

[0098] In other words, the upper surfaces of the gate structure 14a, source 14b, and drain 14c can be flush with the upper surface of the passivation layer 13; in other embodiments, the upper surfaces of the gate structure 14a, source 14b, and drain 14c can also be recessed into the upper surface of the passivation layer 13.

[0099] In other embodiments, b) a passivation layer 13 may be formed on the heterojunction structure 11 first, and then a gate structure 14a may be formed in the passivation layer 13 on the gate region 11a; and a source 14b and a drain 14c may be formed in the passivation layers 13 on both sides of the gate structure 14a.

[0100] In other words, the upper surfaces of the gate structure 14a, source 14b, and drain 14c can be flush with the upper surface of the passivation layer 13; in other embodiments, the upper surfaces of the gate structure 14a, source 14b, and drain 14c can also protrude from the upper surface of the passivation layer 13.

[0101] The passivation layer 13 can be made of silicon nitride or silicon dioxide, and can be formed by physical vapor deposition or chemical vapor deposition, respectively.

[0102] Apart from the differences mentioned above, the other steps of the fabrication method of the enhanced semiconductor structure 4 in this embodiment four can refer to the corresponding steps of the fabrication methods of the enhanced semiconductor structures 1, 2, and 3 in embodiments one to three.

[0103] Figure 8 This is a schematic cross-sectional view of the enhanced semiconductor structure according to the fifth embodiment of the present invention. (Refer to...) Figure 8As shown, the difference between the enhanced semiconductor structure 5 and its fabrication method in this embodiment 5 and the enhanced semiconductor structures 1, 2, and 3 and their fabrication methods in embodiments 1 to 3 is only that the gate structure 14a, source 14b, and drain 14c and their fabrication steps are omitted.

[0104] Enhanced semiconductor structure 5 can be produced and sold as a semi-finished product.

[0105] Figure 9 This is a schematic cross-sectional view of the enhanced semiconductor structure according to the sixth embodiment of the present invention. (Refer to...) Figure 9 As shown, the difference between the enhanced semiconductor structure 6 of this embodiment and the enhanced semiconductor structures 1, 2, 3, 4, and 5 of embodiments 1 to 5 is only that: the heterojunction structure 11 further includes: a second barrier layer 113 sandwiched between the channel layer 111 and the first barrier layer 112, the material of the channel layer 111 is gallium nitride-based material, the material of the second barrier layer 113 is aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, the thickness of the second barrier layer 113 is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer 113 is less than 10%.

[0106] In this embodiment, the intermediate layer 12 is sandwiched between the first barrier layer 112 and the second barrier layer 113 of the gate region 11a.

[0107] When the enhanced semiconductor structure 6 is turned on, the second barrier layer 113 can improve the interface properties between the first barrier layer 112 and the channel layer 111, thereby increasing the mobility of the two-dimensional electron gas during conduction.

[0108] When the channel layer 111 is made of gallium nitride-based material, the second barrier layer 113 is made of aluminum-containing gallium nitride-based material, such as AlGaN. The advantage of having a thickness of less than 10 nm and / or an Al content of less than 10% in the second barrier layer 113 is that when the enhancement-mode semiconductor structure 6 is turned off, there is no two-dimensional electron gas or the concentration of two-dimensional electron gas between the first barrier layer 112 and the channel layer 111 in the gate region 11a, thus not affecting the normal-off state of the enhancement-mode semiconductor structure 6.

[0109] Preferably, the thickness of the second barrier layer 113 in the multilayer structure formed by the aluminum-containing gallium nitride-based material or the aluminum-containing gallium nitride-based material layer and the aluminum nitride layer can be less than 5 nm. More preferably, the thickness of the second barrier layer 113 in the multilayer structure formed by the aluminum-containing gallium nitride-based material or the aluminum-containing gallium nitride-based material layer and the aluminum nitride layer can be less than 2 nm.

[0110] To achieve the same normally relevant benefits without compromising the enhancement-mode semiconductor structure 6, in other embodiments, when the channel layer 111 is made of gallium nitride, the second barrier layer 113 can be made of aluminum nitride. The thickness of the aluminum nitride second barrier layer 113 can be less than 10 nm. Preferably, the thickness of the aluminum nitride second barrier layer 113 can be less than 5 nm. More preferably, the thickness of the aluminum nitride second barrier layer 113 can be less than 2 nm.

[0111] Apart from the differences mentioned above, the other structures of the enhanced semiconductor structure 6 in this embodiment six can refer to the corresponding structures of the enhanced semiconductor structures 1, 2, 3, 4, and 5 in embodiments one to five.

[0112] Accordingly, the fabrication method of the enhanced semiconductor structure 6 in this embodiment six differs from the fabrication methods of the enhanced semiconductor structures 1, 2, 3, 4, and 5 in embodiments one to five only in that: in step S2, before forming the intermediate layer 12, the fabrication method of the enhanced semiconductor structure 6 further includes: forming a second barrier layer 113 on the channel layer 111, wherein the material of the channel layer 111 is a gallium nitride-based material, and the material of the second barrier layer 113 is an aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, wherein the thickness of the second barrier layer 113 is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer 113 is less than 10%.

[0113] The formation process of the second barrier layer 113 can refer to the formation process of the channel layer 111.

[0114] Preferably, the thickness of the second barrier layer 113 in the multilayer structure formed by the aluminum-containing gallium nitride-based material or the aluminum-containing gallium nitride-based material layer and the aluminum nitride layer can be less than 5 nm. More preferably, the thickness of the second barrier layer 113 in the multilayer structure formed by the aluminum-containing gallium nitride-based material or the aluminum-containing gallium nitride-based material layer and the aluminum nitride layer can be less than 2 nm.

[0115] In other embodiments, when the channel layer 111 is made of gallium nitride-based material, the second barrier layer 113 can be made of aluminum nitride. The thickness of the aluminum nitride second barrier layer 113 can be less than 10 nm. Preferably, the thickness of the aluminum nitride second barrier layer 113 can be less than 5 nm. More preferably, the thickness of the aluminum nitride second barrier layer 113 can be less than 2 nm.

[0116] In this embodiment, the intermediate layer 12 is formed in a portion of the second barrier layer 113, and the first barrier layer 112 is formed on the intermediate layer 12 and the second barrier layer 113 exposed by the intermediate layer 12; the channel layer 111, the second barrier layer 113, the intermediate layer 12 and the first barrier layer 112 form a heterojunction structure 11, and the intermediate layer 12 is sandwiched between the first barrier layer 112 and the second barrier layer 113 in the gate region 11a.

[0117] Apart from the differences mentioned above, the other steps of the fabrication method of the enhanced semiconductor structure 6 in this embodiment six can refer to the corresponding steps of the fabrication methods of the enhanced semiconductor structures 1, 2, 3, 4, and 5 in embodiments one to five.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An enhanced semiconductor structure, characterized in that, include: A semiconductor substrate (10) and a heterojunction structure (11) distributed from bottom to top, the heterojunction structure (11) including a channel layer (111) close to the semiconductor substrate (10) and a first barrier layer (112) away from the semiconductor substrate (10); the heterojunction structure (11) includes a gate region (11a) and a source region (11b) and a drain region (11c) located on both sides of the gate region (11a), an intermediate layer (12) is sandwiched between the channel layer (111) of the gate region (11a) and the first barrier layer (112), the intermediate layer (12) being adapted to depolarize the first barrier layer (112) it contacts; The intermediate layer (12) is a polycrystalline layer, and the material of the polycrystalline layer is at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride; or The intermediate layer (12) is an amorphous layer, and the material of the amorphous layer is at least one of silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride.

2. The enhanced semiconductor structure according to claim 1, characterized in that, The channel layer (111) is made of gallium nitride-based material, and the first barrier layer (112) is made of aluminum-containing gallium nitride-based material, aluminum nitride, or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer.

3. The enhanced semiconductor structure according to claim 1, characterized in that, The thickness of the intermediate layer (12) is greater than 0.2 nm.

4. The enhanced semiconductor structure according to claim 1 or 3, characterized in that, The thickness ratio of the first barrier layer (112) to the intermediate layer (12) is less than 50:

1.

5. The enhanced semiconductor structure according to claim 1, characterized in that, The heterojunction structure (11) further includes: a second barrier layer (113) sandwiched between the channel layer (111) and the first barrier layer (112), wherein the channel layer (111) is made of gallium nitride-based material, the second barrier layer (113) is made of aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, the thickness of the second barrier layer (113) is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer (113) is less than 10%; the intermediate layer (12) is sandwiched between the first barrier layer (112) and the second barrier layer (113) in the gate region (11a).

6. The enhanced semiconductor structure according to claim 1, characterized in that, The heterojunction structure (11) further includes: a second barrier layer (113) sandwiched between the channel layer (111) and the first barrier layer (112), wherein the channel layer (111) is made of gallium nitride-based material, the second barrier layer (113) is made of aluminum nitride, and the thickness of the second barrier layer (113) is less than 10 nm; the intermediate layer (12) is sandwiched between the first barrier layer (112) and the second barrier layer (113) in the gate region (11a).

7. The enhanced semiconductor structure according to claim 1, characterized in that, The enhanced semiconductor structure further includes a gate structure (14a) located on the gate region (11a), and a source (14b) and a drain (14c) located on both sides of the gate structure (14a).

8. The enhanced semiconductor structure according to claim 7, characterized in that, The enhanced semiconductor structure further includes a passivation layer (13) disposed between the gate structure (14a) and the source (14b) and between the gate structure (14a) and the drain (14c).

9. The enhanced semiconductor structure according to claim 7, characterized in that, The gate structure (14a) is a stacked structure of gate insulating layer (14d) and gate (14e), or only includes gate (14e).

10. A method for fabricating an enhanced semiconductor structure, characterized in that, include: A semiconductor substrate (10) is provided, on which a channel layer (111) is formed. An intermediate layer (12) is formed in a portion of the channel layer (111); a first barrier layer (112) is formed on the intermediate layer (12) and the channel layer (111) exposed by the intermediate layer (12); the channel layer (111), the intermediate layer (12) and the first barrier layer (112) form a heterojunction structure (11), the heterojunction structure (11) includes a gate region (11a) and a source region (11b) and a drain region (11c) located on both sides of the gate region (11a), the intermediate layer (12) is sandwiched between the channel layer (111) and the first barrier layer (112) in the gate region (11a), and the intermediate layer (12) is adapted to depolarize the first barrier layer (112) it contacts; The intermediate layer (12) is a polycrystalline layer, and the material of the polycrystalline layer is at least one of polycrystalline diamond, polycrystalline nickel oxide, and polycrystalline gallium nitride; or The intermediate layer (12) is an amorphous layer, and the material of the amorphous layer is at least one of silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and aluminum oxynitride.

11. The method for fabricating an enhanced semiconductor structure according to claim 10, characterized in that, The intermediate layer (12) is formed using physical vapor deposition, chemical vapor deposition or atomic layer deposition.

12. The method for fabricating an enhanced semiconductor structure according to claim 10, characterized in that, The thickness of the intermediate layer (12) is greater than 0.2 nm.

13. The method for fabricating an enhanced semiconductor structure according to claim 10 or 12, characterized in that, The thickness ratio of the first barrier layer (112) to the intermediate layer (12) is less than 50:

1.

14. The method for fabricating an enhanced semiconductor structure according to claim 10, characterized in that, Before the step of forming the intermediate layer (12), the method for fabricating the enhanced semiconductor structure further includes: forming a second barrier layer (113) on the channel layer (111), wherein the material of the channel layer (111) is a gallium nitride-based material, the material of the second barrier layer (113) is an aluminum-containing gallium nitride-based material or a multilayer structure formed by an aluminum-containing gallium nitride-based material layer and an aluminum nitride layer, the thickness of the second barrier layer (113) is less than 10 nm and / or the Al content of the aluminum-containing gallium nitride-based material in the second barrier layer (113) is less than 10%; The intermediate layer (12) is formed on a portion of the second barrier layer (113), and the first barrier layer (112) is formed on the intermediate layer (12) and the second barrier layer (113) exposed by the intermediate layer (12); the channel layer (111), the second barrier layer (113), the intermediate layer (12) and the first barrier layer (112) form the heterojunction structure (11), and the intermediate layer (12) is sandwiched between the first barrier layer (112) and the second barrier layer (113) in the gate region (11a).

15. The method for fabricating an enhanced semiconductor structure according to claim 10, characterized in that, Before the step of forming the intermediate layer (12), the method for fabricating the enhanced semiconductor structure further includes: forming a second barrier layer (113) on the channel layer (111), wherein the material of the channel layer (111) is gallium nitride-based material, the material of the second barrier layer (113) is aluminum nitride, and the thickness of the second barrier layer (113) is less than 10 nm. The intermediate layer (12) is formed on a portion of the second barrier layer (113), and the first barrier layer (112) is formed on the intermediate layer (12) and the second barrier layer (113) exposed by the intermediate layer (12); the channel layer (111), the second barrier layer (113), the intermediate layer (12) and the first barrier layer (112) form the heterojunction structure (11), and the intermediate layer (12) is sandwiched between the first barrier layer (112) and the second barrier layer (113) in the gate region (11a).

16. The method for fabricating an enhanced semiconductor structure according to claim 10, characterized in that, Also includes: A gate structure (14a) is formed on the gate region (11a), and a source (14b) and a drain (14c) are formed on both sides of the gate structure (14a).

17. The method for fabricating an enhanced semiconductor structure according to claim 16, characterized in that, The gate structure (14a) is a stacked structure of gate insulating layer (14d) and gate (14e), or only includes gate (14e).

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