Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method of forming the same, wherein the method includes: an interlayer dielectric layer on the surface of the first isolation structure and a first opening in the interlayer dielectric layer, the interlayer dielectric layer is located on the sidewalls of the gate, and the first opening exposes the top surface of the first isolation structure on the first region and the sidewalls of the gate on the first region; a second opening in the first isolation structure on the first region, the second opening extending along the second direction; a third opening between the second opening and the gate, the third opening communicating with the second opening and the first opening; a second isolation structure in the first opening, the second isolation structure closing the second opening to form a first void. On the one hand, the deformation of the fin on the second region is reduced. On the other hand, the first void has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In the existing semiconductor field, the fin field-effect transistor (FinFET) is a new type of multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the fin field-effect transistor has stronger short-channel suppression ability and stronger working current, and has now been widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, integrated circuits continue to be "scaled down". When the size of semiconductor devices is reduced to the nanometer level, especially for fin field-effect transistors, its gate control ability has a very close relationship with its physical size. The small geometric size and three-dimensional structure of fin field-effect transistors make the device impact caused by process variations more and more serious, and new methods are urgently needed to optimize. The method for forming the fin field-effect transistor structure in the prior art needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a base, the base includes a first region and a second region arranged along a first direction, and the first region is adjacent to the second region, the substrate further includes a plurality of fin portions located on the second region, the fin portions are parallel to a second direction and arranged along the first direction, and the second direction is perpendicular to the first direction; a first isolation structure located on the base, the first isolation structure is located on the sidewalls of the fin portions, and the top surface of the fin portions is higher than the top surface of the first isolation structure; a plurality of gates located on the first region and the second region and spanning the plurality of fin portions, the plurality of gates are located on the top and sidewall surfaces of some of the fin portions and on the surface of some of the first isolation structures; an interlayer dielectric layer located on the surface of the first isolation structure and a first opening in the interlayer dielectric layer, the interlayer dielectric layer is located on the sidewalls of the gates, and the first opening exposes the top surface of the first isolation structure on the first region and the sidewall of the gate on the first region; a second opening in the first isolation structure on the first region, the second opening extends along the second direction, and the plurality of gates are located above some of the second openings; a third opening located on some of the second openings, the third opening extends along the second direction through the plurality of gates and communicates with the first opening; a second isolation structure located in the first opening, the second isolation structure closes the second opening and the third opening to form a void.

[0006] Optionally, the second isolation structure is further located in the third opening.

[0007] Optionally, the material of the second isolation structure is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0008] Optionally, there are a plurality of the voids, and the plurality of voids extend along the second direction and are arranged along the first direction.

[0009] Optionally, the aspect ratio range of the second opening is greater than 8:1.

[0010] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a base, the base includes a first region and a second region arranged along a first direction, and the first region is adjacent to the second region, the substrate further includes a plurality of fin portions located on the first region and the second region, the fin portions are parallel to a second direction and arranged along the first direction, and the second direction is perpendicular to the first direction; forming a first isolation structure on the base, the first isolation structure is located on the sidewalls of the fin portions, and the top surface of the fin portions is higher than the top surface of the first isolation structure; forming a plurality of dummy gates across the fin portions, the dummy gates are located on the top and sidewall surfaces of some of the fin portions and on some surfaces of the first isolation structure; forming an interlayer dielectric layer on the surface of the substrate, and the interlayer dielectric layer is also located on the sidewalls of the dummy gates; after forming the interlayer dielectric layer, removing the fin portions on the first region, forming a first opening in the interlayer dielectric layer, forming a second opening in the first isolation structure, and forming a third opening between the dummy gate and the second opening, the first opening exposes the top surface of the first isolation structure on the first region and the sidewall of the dummy gate on the first region, and the second opening extends along the second direction; forming a second isolation structure in the first opening, and the second isolation structure closes the second opening to form a first gap.

[0011] Optionally, the method for removing the fin portions on the first region includes: removing the interlayer dielectric layer on the first region by a first etching process to form a first opening in the interlayer dielectric layer, and the first opening exposes some of the fin portions on the first region; after forming the first opening, etching the fin portions on the first region by a second etching process to form the second opening and the third opening.

[0012] Optionally, after the second etching process, the surface of the dummy gate exposed by the third opening has some fin portion residues.

[0013] Optionally, the second isolation structure is also located on the surface of the dummy gate in the third opening.

[0014] Optionally, the first etching process includes an anisotropic dry etching process; the second etching process includes an isotropic dry etching process or a combination of one or both of a wet etching process.

[0015] Optionally, the process parameters of the first etching process include: the gases used include CF4, HBr, O2, and Cl2, wherein the flow rate of CF4 is 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is 50 standard milliliters per minute to 3000 standard milliliters per minute.

[0016] Optionally, the selectivity range of the second etching process for the fin and the first isolation structure is greater than 5:1; the selectivity range of the second etching process for the fin and the dummy gate is greater than 10:1.

[0017] Optionally, the second isolation structure also seals the third opening to form a second gap between the dummy gate and the first region, and the first gap and the second gap form a gap.

[0018] Optionally, the formation process of the second isolation structure includes a plasma enhanced chemical vapor deposition process.

[0019] Optionally, the method for removing the fins on the first region includes: forming a patterned layer on the interlayer dielectric layer and the surface of the dummy gate, and the patterned layer exposes the interlayer dielectric layer and the surface of the dummy gate on the first region; using the patterned layer as a mask to etch the interlayer dielectric layer and the fins on the first region.

[0020] Optionally, after forming the second isolation structure, it further includes: removing the dummy gate, forming a gate groove in the interlayer dielectric layer; and forming a gate in the gate groove.

[0021] Optionally, after forming the first isolation structure and before forming the interlayer dielectric layer, source-drain layers are further formed in the fins on both sides of the dummy gate.

[0022] Optionally, the method for forming the first opening, the second opening, and the third opening further includes: removing the source-drain layer on the first region.

[0023] Optionally, there are a plurality of fins on the first region. After removing the plurality of fins on the first region, a plurality of the second openings are formed in the first isolation structure. The plurality of second openings extend along the second direction and are arranged along the first direction; the second isolation structure seals the plurality of second openings to form a plurality of the first gaps.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, on the one hand, after forming the first isolation structure, the fins on the first region are removed. Since the first isolation structure is formed before removing the fins on the first region, the fins on the second region are not affected by the heat treatment process of the first isolation structure, reducing the deformation of the fins on the second region and being beneficial to improving the performance of the subsequent formed devices. On the other hand, a second isolation structure is formed in the first opening, and the second isolation structure closes the second opening to form a first gap. The first gap has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0026] Furthermore, the second isolation structure also closes the third opening to form a second gap between the pseudo gate and the first region. The second gap has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0027] In the semiconductor structure provided by the technical solution of the present invention, the first gap has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0028] Furthermore, the second gap has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices. Description of the Drawings

[0029] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure formation process;

[0030] Figures 5 to 24 is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0031] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0032] As described in the background art, the performance of the semiconductor structure formed by the existing FinFET technology needs to be improved urgently. A semiconductor structure is now combined for explanation and analysis.

[0033] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure formation process.

[0034] Please refer to Figure 1 and Figure 2 , Figure 1 is Figure 2 a top view structural diagram of Figure 2 is Figure 1Schematic cross-sectional structure diagram along the DD1 direction. A substrate is provided, which includes a base 100 and a plurality of fin portions 101 located on a part of the base 100. The fin portions 101 are parallel to the first direction X and arranged along the second direction Y. The fin portions 101 include a first region I and a second region II arranged along the second direction Y.

[0035] Please refer to Figure 3 and Figure 4 , Figure 3 is Figure 4 the top-view structure diagram of Figure 4 is Figure 3 the schematic cross-sectional structure diagram along the DD1 direction in . Remove the first region I; after removing the first region I, a dielectric material layer (not marked in the figure) is formed on the surface of the substrate; the dielectric material layer is etched back until the top and part of the sidewalls of the fin portions 101 are exposed, forming an isolation structure 102.

[0036] In the above method, after removing the first region I, the isolation structure 102 is formed. The formation process of the isolation structure 102 requires a high-temperature heat treatment process. Since along the second direction Y, the coverage areas of the isolation structures 102 on both sides of the fin portions 101 at the periphery (the fin portions 101 adjacent to the first region I) on the base 100 are different, it will cause the stress magnitudes from the isolation structure 102 received on both sides of the fin portions 101 at the periphery to be different. Therefore, under the high-temperature heat treatment process, it is very easy to cause the fin portions 101 at the periphery to generate bending deformation, that is, there appears an abnormal fin A as shown in Figure 4 , which leads to unstable performance of the subsequent formed devices and reduces the production yield.

[0037] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, on the one hand, after forming the first isolation structure, the fin portions on the first region are removed. Since the first isolation structure is formed before removing the fin portions on the first region, the fin portions on the second region are not affected by the heat treatment process of the first isolation structure, reducing the deformation of the fin portions on the second region, which is beneficial to improving the performance of the subsequent formed devices; on the other hand, a second isolation structure is formed in the first opening, and the second isolation structure closes the second opening to form a first void, and the first void has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0039] Figures 5 to 24 is the structure schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0040] Please refer to Figures 5 to 7 , Figure 5 which is Figure 6 a Figure 7 top-down structural schematic diagram of Figure 6 and Figure 5 a cross-sectional structural schematic diagram along the EE1 direction in Figure 7 which is Figure 5 a cross-sectional structural schematic diagram along the DD1 direction in. A substrate is provided, and the substrate includes a base 200. The base 200 includes a first region A and a second region B arranged along a first direction X, and the first region A is adjacent to the second region B. The substrate further includes a plurality of fin portions 201 located on the first region A and the second region B. The fin portions 201 are parallel to a second direction Y and arranged along the first direction X, and the second direction Y is perpendicular to the first direction X. A first isolation structure 202 is formed on the base 200. The first isolation structure 202 is located on the sidewalls of the fin portions 201, and the top surface of the fin portions 201 is higher than the top surface of the first isolation structure 202. A plurality of dummy gates 203 spanning the fin portions 201 are formed. The dummy gates 203 are located on the top and sidewall surfaces of some of the fin portions 201 and on a part of the surface of the first isolation structure 202.

[0041] Specifically, the number of the fin portions on the first region A is plural. In this embodiment, there are two fin portions on the first region A. In other embodiments, the number of the fin portions on the first region is not limited to this.

[0042] In this embodiment, the material of the base 200 includes silicon. In other embodiments, the material of the base includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0043] In this embodiment, the material of the fin portions 201 includes silicon. In other embodiments, the material of the fin portions 201 can be silicon germanium.

[0044] In this embodiment, the dummy gate 203 includes a dummy gate layer (not marked in the figure) and a protective sidewall (not marked in the figure) located on the sidewall of the dummy gate layer.

[0045] In this embodiment, the method for forming the plurality of dummy gate layers includes: forming a dummy gate material layer (not marked in the figure) on the substrate; forming a hard mask layer 204 on the surface of the dummy gate material layer, and the hard mask layer 204 exposes a part of the dummy gate material layer; using the hard mask layer 204 as a mask to etch the dummy gate material layer to form the dummy gate 203.

[0046] In this embodiment, the material of the dummy gate layer is silicon. In other embodiments, the material of the dummy gate layer may be amorphous silicon, amorphous carbon, etc. The dummy gate 203 is used to occupy space for subsequent formation of the gate.

[0047] Subsequently, an interlayer dielectric layer is formed on the surface of the substrate 200, and the interlayer dielectric layer also lies on the sidewalls of the dummy gate 203.

[0048] The first isolation structure 202 is used for electrical insulation between devices. Subsequently, the fins 201 on the first region A are removed. Since the first isolation structure 202 is formed before removing the fins 201 on the first region A, the fins 201 on the second region B are not affected by the heat treatment process of the first isolation structure 202, reducing the deformation of the fins 201 on the second region B, which is beneficial to improving the performance of the subsequent formed devices.

[0049] In this embodiment, after forming the first isolation structure 202 and before forming the interlayer dielectric layer, please refer to Figures 8 to 10 .

[0050] Please refer to Figures 8 to 10 , Figure 8 is Figure 9 and Figure 10 a top view structural schematic diagram of the interlayer dielectric layer is omitted, Figure 9 is Figure 8 a cross-sectional structural schematic diagram along the EE1 direction, Figure 10 is Figure 8 a cross-sectional structural schematic diagram along the DD1 direction. Source / drain layers 205 are formed in the fins 201 on both sides of the dummy gate 203.

[0051] The method for forming the source / drain layers 205 includes: forming grooves (not marked in the figure) in the fins 201 on both sides of the dummy gate 203; forming an epitaxial layer (not marked in the figure) in the grooves, and implanting doping ions into the epitaxial layer, and the doping ions are N-type or P-type ions.

[0052] Please continue to refer to Figure 9 and Figure 10 , an interlayer dielectric layer 206 is formed on the surface of the substrate 200, and the interlayer dielectric layer 206 also lies on the sidewalls of the dummy gate 203.

[0053] In this embodiment, the method for forming the interlayer dielectric layer 206 includes: forming a first dielectric material layer (not marked in the figure) on the substrate, and the first dielectric material layer also lies on the sidewalls of the dummy gate 203; planarizing the first dielectric material layer until the top surface of the dummy gate 203 is exposed.

[0054] In this embodiment, a hard mask layer 204 is further provided on the top surface of the dummy gate 203, and the interlayer dielectric layer is also located on the sidewalls of the hard mask layer 204. Specifically, during the formation of the interlayer dielectric layer 206, the first dielectric material layer is planarized until the top surface of the hard mask layer 204 is exposed.

[0055] Subsequently, after the interlayer dielectric layer 206 is formed, the fins 201 on the first region A are removed, a first opening is formed in the interlayer dielectric layer 206, a second opening is formed in the first isolation structure 202, and a third opening is formed between the dummy gate 203 and the second opening. The first opening exposes the top surface of the first isolation structure 202 on the first region A and the sidewalls of the dummy gate 203 on the first region. The second opening extends along the second direction Y. For the method of removing the fins 201 on the first region A, please refer to Figures 11 to 20 .

[0056] Please refer to Figures 11 to 12 . Figure 11 is Figure 12 a top view structural schematic diagram of Figure 12 is Figure 11 a cross-sectional structural schematic diagram along the EE1 direction in . A patterned layer 207 is formed on the surfaces of the interlayer dielectric layer 206 and the dummy gate 203, and the patterned layer 207 exposes the surfaces of the interlayer dielectric layer 206 and the dummy gate 203 on the first region A.

[0057] In this embodiment, specifically, a patterned layer is formed on the surfaces of the interlayer dielectric layer 206 and the hard mask layer 204, and the patterned layer 207 exposes the surfaces of the interlayer dielectric layer 206 and the hard mask layer 204 on the first region A.

[0058] In this embodiment, the material of the patterned layer 207 is a bottom anti-reflection material.

[0059] In this embodiment, the method for forming the patterned layer 207 includes: forming a bottom anti-reflection layer (not shown in the figure) on the substrate surface; forming a photoresist layer (not shown in the figure) on the surface of a part of the bottom anti-reflection layer, and the photoresist layer exposes a part of the bottom anti-reflection layer surface; using the photoresist layer as a mask to etch the bottom anti-reflection layer, and using the bottom anti-reflection layer to form the patterned layer 207; after the patterned layer 207 is formed, removing the bottom anti-reflection layer.

[0060] Subsequently, using the mask layer 207 as a mask, the interlayer dielectric layer 206 and the fins 201 on the first region A are etched. Specifically, for the method of removing the fins 201 on the first region A, please continue to refer to Figures 13 to 18 .

[0061] Please refer to Figures 13 to 14 , Figure 13 which Figure 14 is a top view structural schematic diagram of Figure 14 and Figure 13 is a cross-sectional structural schematic diagram along the EE1 direction in . Using a first etching process to remove the interlayer dielectric layer 206 on the first region A, a first opening 208 is formed in the interlayer dielectric layer 206, and the first opening 208 exposes a part of the fin 201 on the first region A.

[0062] The formation method of the first opening 208, the second opening, and the third opening further includes: removing the source / drain layer 205 on the first region A.

[0063] In this embodiment, during the first etching process, the source / drain layer 205 on the first region A and the fin 201 in the interlayer dielectric layer 206 on the first region A are also etched and removed. In other embodiments, the source / drain layer 205 on the first region A and the fin 201 in the interlayer dielectric layer 206 on the first region A may not be removed during the first etching process.

[0064] The first etching process includes an anisotropic dry etching process. The anisotropic dry etching process is beneficial to improving the opening morphology of the formed first opening 208.

[0065] The process parameters of the first etching process include: the gases used include CF4, HBr, O2, and Cl2, where the flow rate of CF4 is 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is 50 standard milliliters per minute to 3000 standard milliliters per minute.

[0066] Please refer to Figures 15 to 18 , Figure 15 which Figures 16 to 18 is a top view structural schematic diagram of Figure 16 and Figure 15 is a cross-sectional structural schematic diagram along the EE1 direction in . Figure 17 is Figure 15 a cross-sectional structural schematic diagram along the DD1 direction in , Figure 18 and Figure 15 is a cross-sectional structural schematic diagram along the FF direction in . After forming the first opening 208, a second etching process is used to etch the fin 201 on the first region A to form the second opening 209 and the third opening 210.

[0067] The second opening 209 is located within the first isolation structure 202.

[0068] Specifically, after removing the plurality of fin portions 201 on the first region A, a plurality of the second openings 209 are formed in the first isolation structure 202. The plurality of the second openings 209 extend along the second direction Y and are arranged along the first direction X. In this embodiment, the number of the second openings 209 is two. In other embodiments, the number of the second openings is not limited thereto.

[0069] The aspect ratio range of the second opening 209 is greater than 8:1. Subsequently, a second isolation structure is formed in the first opening 208, and the second isolation structure closes the second opening 209 to form a first gap. Since the second opening 209 has a large aspect ratio, it is more conducive to the material of the second isolation structure 212 to close the second opening 209 to form the first gap.

[0070] The second etching process includes one or a combination of an isotropic dry etching process and a wet etching process.

[0071] The selectivity range of the second etching process for the fin portion 201 and the first isolation structure 202 is greater than 5:1. The reason for selecting this range ratio is to reduce the etching damage of the second etching process to the first isolation structure 202. In this embodiment, the selectivity range of the second etching process for the fin portion 201 and the first isolation structure 202 is 5:1 to 10:1.

[0072] The selectivity range of the second etching process for the fin portion 201 and the dummy gate 203 is greater than 10:1. Specifically, the selectivity range of the second etching process for the fin portion 201 and the protective sidewall of the dummy gate 203 is greater than 10:1. The reason for selecting this range ratio is to reduce the etching damage of the second etching process to the dummy gate 203. In this embodiment, the selectivity range of the second etching process for the fin portion 201 and the dummy gate 203 is 10:1 to 20:1.

[0073] In this embodiment, after the second etching process, the surface of the dummy gate 203 exposed by the third opening 210 has partial fin portion 201 residues, that is, a residue region 211 is formed. The residue region 211 can prevent the etching solution from flowing into the gap 210 when the dummy gate 203 is removed subsequently.

[0074] Please refer to Figures 19 to 21 , Figure 19 For Figure 20 and Figure 21 is a top view structural schematic diagram of Figure 20 For Figure 19 is a cross-sectional structural schematic diagram along the EE1 direction in Figure 21 For Figure 19Schematic cross-sectional structure diagram along the DD1 direction. A second isolation structure 212 is formed within the first opening 208, and the second isolation structure 212 closes the second opening 209 to form a first void 213.

[0075] In this embodiment, the method for forming the second isolation structure 212 includes: forming a second dielectric material layer within the first opening 208 and on the surface of the patterned layer 207; planarizing the second dielectric material layer until the surface of the interlayer dielectric layer 206 is exposed. The patterned layer 207 is removed during the planarization process.

[0076] The material of the second isolation structure 212 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second isolation structure 212 is silicon oxide.

[0077] The first void 213 has a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0078] In other embodiments, the second isolation structure 212 is also formed within the third opening 210.

[0079] The second isolation structure 212 also closes the third opening 210 to form a second void 214 between the pseudo-gate 203 and the first region A, and the first void 213 and the second void 214 form voids.

[0080] In this embodiment, there are a plurality of voids. The plurality of voids extend along the second direction Y and are arranged along the first direction X. In this embodiment, the number of voids is 2. In other embodiments, the number of voids is not limited to this.

[0081] The formation process of the second isolation structure 212 includes a plasma-enhanced chemical vapor deposition process.

[0082] The process parameters of the plasma-enhanced chemical vapor deposition process include: the reaction gases include SiH4, NH3, and N2, and the reaction temperature range is from 350 degrees Celsius to 450 degrees Celsius.

[0083] The plasma-enhanced chemical vapor deposition process has a fast film formation speed, which can reduce the filling of the material of the second isolation structure 212 within the second opening 209 and the third opening 210, and is beneficial to closing the second opening 209 and the third opening 210.

[0084] Please refer to Figures 22 to 24 , Figure 22 for Figure 23 and Figure 24Top view structural schematic diagram Figure 23 is Figure 22 Cross-sectional structural schematic diagram along the EE1 direction in Figure 24 is Figure 22 Cross-sectional structural schematic diagram along the DD1 direction in . After forming the second isolation structure 212, the dummy gate 203 is further removed, and a gate groove (not marked in the figure) is formed in the interlayer dielectric layer 206; a gate 215 is formed in the gate groove.

[0085] In this embodiment, before removing the dummy gate 203, it further includes: planarizing the hard mask layer 204 and the second isolation structure 212 until the surface of the dummy gate 203 is exposed.

[0086] The process of removing the dummy gate 203 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of removing the dummy gate 203 is a wet etching process.

[0087] The gate 215 includes a gate dielectric layer (not marked in the figure) on the surface of the gate groove and a gate layer (not marked in the figure) on the surface of the gate dielectric layer.

[0088] The material of the gate layer includes metal.

[0089] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figures 22 to 24 , including: a substrate, the substrate includes a base 200, the base 200 includes a first region A and a second region B arranged along a first direction X, and the first region A is adjacent to the second region B. The substrate further includes a plurality of fin portions 201 located on the second region B. The fin portions 201 are parallel to a second direction Y and arranged along the first direction X; a first isolation structure 202 located on the base 200, the first isolation structure 202 is located on the sidewalls of the fin portions 201, and the top surface of the fin portions 201 is higher than the top surface of the first isolation structure 202; a plurality of gates 215 located on the first region A and the second region B and spanning the plurality of fin portions 201. The plurality of gates 215 are located on the top and sidewall surfaces of some of the fin portions 201 and on the surface of some of the first isolation structures 202; an interlayer dielectric layer 206 located on the surface of the first isolation structure 202 and a first opening 208 in the interlayer dielectric layer 206 (as Figure 16 shown), the interlayer dielectric layer 206 is located on the sidewalls of the gates 215, and the first opening exposes the top surface of the first isolation structure 202 on the first region A and the sidewall of the gate 215 on the first region A; a second opening 209 in the first isolation structure 202 on the first region A (as Figure 16As shown, the second opening 209 extends along the second direction Y, and the plurality of gates 215 are located above a part of the second opening 209; a third opening 210 (as shown in Figure 17 As shown) that extends along the second direction Y through the plurality of gates 215 and communicates with the first opening 208; a second isolation structure 212 located within the first opening 208, the second isolation structure 212 closing the second opening 209 and the third opening 210 to form a gap.

[0090] In this embodiment, there are a plurality of such gaps, and the plurality of gaps extend along the second direction Y and are arranged along the first direction X.

[0091] The gaps have a low dielectric constant, which is beneficial to reducing the parasitic capacitance between different devices.

[0092] In this embodiment, the second isolation structure 212 closes the second opening 209 and the third opening 210 to form a gap, that is, it includes a first gap 213 closing the second opening 209 and a second gap 214 closing the third opening 210. In another embodiment, the second isolation structure is also located within the third opening, that is, it only closes the third opening to form a gap.

[0093] The material of the second isolation structure 212 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0094] The aspect ratio range of the second opening 209 is greater than 8:1.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a base, the base including a first region and a second region arranged in a first direction, and the first region being adjacent to the second region. The substrate further includes a plurality of fin portions located on the second region, the fin portions being parallel to a second direction and arranged in the first direction, the second direction being perpendicular to the first direction; A first isolation structure located on the base, the first isolation structure being located on the sidewalls of the fin portions, and the top surface of the fin portions being higher than the top surface of the first isolation structure; A plurality of gates located on the first region and the second region and spanning the plurality of fin portions, the plurality of gates being located on the top and sidewall surfaces of some of the fin portions and on the surface of some of the first isolation structure; An interlayer dielectric layer located on the surface of the first isolation structure and a first opening in the interlayer dielectric layer, the interlayer dielectric layer being located on the sidewalls of the gates, and the first opening exposing the top surface of the first isolation structure on the first region and the sidewalls of the gates on the first region; A second opening in the first isolation structure on the first region, the second opening extending in the second direction, and the plurality of gates being located above some of the second opening; A third opening located on some of the second opening, the third opening passing through the plurality of gates in the second direction and communicating with the first opening; A second isolation structure located in the first opening, the second isolation structure closing the second opening and the third opening to form a void.

2. The semiconductor structure according to claim 1, characterized in that, The second isolation structure is further located in the third opening.

3. The semiconductor structure according to claim 1, wherein The material of the second isolation structure is a dielectric material, the dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

4. The semiconductor structure according to claim 1, wherein The voids are plural, and the plural voids extend in the second direction and are arranged in the first direction.

5. The semiconductor structure according to claim 1, characterized in that, The aspect ratio range of the second opening is greater than 8:

1.

6. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a base, the base including a first region and a second region arranged in a first direction, and the first region being adjacent to the second region. The substrate further includes a plurality of fin portions located on the first region and the second region, the fin portions being parallel to a second direction and arranged in the first direction, the second direction being perpendicular to the first direction; Forming a first isolation structure on the base, the first isolation structure being located on the sidewalls of the fin portions, and the top surface of the fin portions being higher than the top surface of the first isolation structure; Forming a plurality of dummy gates spanning the fin portions, the dummy gates being located on the top and sidewall surfaces of some of the fin portions and on a part of the surface of the first isolation structure; A interlayer dielectric layer is formed on the surface of the substrate, and the interlayer dielectric layer also lies on the sidewalls of the dummy gate; after forming the interlayer dielectric layer, the fins on the first region are removed, a first opening is formed in the interlayer dielectric layer, a second opening is formed in the first isolation structure, and a third opening is formed between the dummy gate and the second opening. The first opening exposes the top surface of the first isolation structure on the first region and the sidewalls of the dummy gate on the first region. The second opening extends along the second direction; A second isolation structure is formed in the first opening, and the second isolation structure closes the second opening to form a first void.

7. The method for forming a semiconductor structure according to claim 6, wherein, The method for removing the fins on the first region includes: removing the interlayer dielectric layer on the first region by using a first etching process to form a first opening in the interlayer dielectric layer, and the first opening exposes a part of the fins on the first region; after forming the first opening, etching the fins on the first region by using a second etching process to form the second opening and the third opening.

8. The method for forming a semiconductor structure according to claim 7, wherein, After the second etching process, the surface of the dummy gate exposed by the third opening has partial fin residues.

9. The method for forming a semiconductor structure according to claim 7, wherein The second isolation structure also lies on the surface of the dummy gate in the third opening.

10. The method for forming a semiconductor structure according to claim 7, wherein, The first etching process includes an anisotropic dry etching process; the second etching process includes one or a combination of an isotropic dry etching process and a wet etching process.

11. The method for forming a semiconductor structure as described in claim 10, wherein, The process parameters of the first etching process include: the gases used include CF4, HBr, O2, Cl2, wherein the flow rate of CF4 is 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is 50 standard milliliters per minute to 3000 standard milliliters per minute.

12. The method for forming a semiconductor structure according to claim 10, wherein, The selectivity ratio of the second etching process for the fins and the first isolation structure ranges from greater than 5:1; the selectivity ratio of the second etching process for the fins and the dummy gate ranges from greater than 10:

1.

13. The method for forming a semiconductor structure according to claim 6, wherein, The second isolation structure also closes the third opening to form a second void between the dummy gate and the first region, and the first void and the second void form a void.

14. The method for forming a semiconductor structure according to claim 6, wherein, The formation process of the second isolation structure includes a plasma enhanced chemical vapor deposition process.

15. The method for forming a semiconductor structure according to claim 6, wherein The method for removing the fins on the first region includes: forming a patterned layer on the surface of the interlayer dielectric layer and the dummy gate, and the patterned layer exposes the surface of the interlayer dielectric layer and the dummy gate on the first region; using the patterned layer as a mask to etch the interlayer dielectric layer and the fins on the first region.

16. The method for forming a semiconductor structure according to claim 6, wherein, After forming the second isolation structure, it further includes: removing the dummy gate, forming a gate groove in the interlayer dielectric layer; forming a gate in the gate groove.

17. The method for forming a semiconductor structure according to claim 6, wherein, After forming the first isolation structure and before forming the interlayer dielectric layer, source-drain layers are also formed in the fins on both sides of the dummy gate.

18. The method for forming a semiconductor structure according to claim 17, wherein, The formation method of the first opening, the second opening, and the third opening further includes: removing the source-drain layer on the first region.

19. The method for forming a semiconductor structure as claimed in claim 6, wherein, The fin portions on the first region are multiple. After removing the multiple fin portions on the first region, multiple second openings are formed within the first isolation structure. The multiple second openings extend along the second direction and are arranged along the first direction; the second isolation structure closes the multiple second openings to form multiple first voids.

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