An Adaptive Turn-On Time Generation Circuit for DC-DC Converters

Abstract

The present invention claims protection for an adaptive on-time generation circuit for a DC-DC converter, which includes an adaptive on-time generation core circuit and an output shaping circuit. The present invention uses an NMOS transistor M1, resistors R1 to R2, an amplifier A1, and a controlled resistor R3 to generate a current I that is adaptive to the input voltage and output voltage of the DC-DC converter and does not change with the capacitor plate voltage. R3 , a source follower is formed by using a resistor R4 and a PMOS transistor M3 to make the current I R4 related to the current I R3 , a current comparator is formed by using resistors R4 to R5, a PMOS transistor M3, and an NMOS transistor M4 to compare the current I R4 with a reference current I R6 , reducing the system power consumption and increasing the comparison speed. An output shaping circuit is formed by using an inverter INV1, an inverter INV2, and NMOS transistors M5 to M6, improving the circuit shaping efficiency and flip speed, thereby realizing a high-performance adaptive on-time generation circuit.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to an adaptive on-time generation circuit for a DC-DC converter. Background Art

[0002] The buck DC-DC converter is one of the power management type chips with a very wide range of application scenarios at present. It can provide a large load current driving ability, is easy to use and has a high conversion efficiency. The constant on-time control mode, as a commonly used control mode at present, has been widely applied to DC-DC converter systems.

[0003] Figure 1 For a traditional adaptive on-time generation circuit, the amplifier A1 and the NMOS transistor M1 form a negative feedback to make the drain current I flowing through the PMOS transistor M2 2 related to the input voltage V in . The PMOS transistor M2 and the PMOS transistor M3 are exactly the same. Then, the drain current I of the PMOS transistor M3 3 has I 3 = I 2 . When the upper power transistor of the DC-DC converter is turned on, the switch S1 is closed and the switch S2 is opened. The drain current I of the PMOS transistor M3 3 charges the capacitor C1. At the same time, the voltage of the upper plate of the capacitor C1 and the voltage of the output terminal of the DC-DC converter obtained are compared by the comparator COMP. When the output of the comparator COMP is high level, the upper power transistor of the DC-DC converter is turned off. During the charging process of the capacitor C1, the voltage of the upper plate of the capacitor C1 continuously rises. Due to the channel modulation effect of the MOS transistor, the charging current I of the capacitor C1 3 is not equal to the drain current I of the PMOS transistor M2 2 , thereby affecting the on-time of the upper power transistor of the DC-DC converter and limiting the application of the adaptive on-time generation circuit in a high-precision DC-DC converter system. Summary of the Invention

[0004] The present invention aims to solve the above problems of the prior art. An adaptive on-time generation circuit for a DC-DC converter is proposed. The technical solution of the present invention is as follows:

[0005] An adaptive on-time generation circuit for a DC-DC converter, which includes an adaptive on-time generation core circuit (1) and an output shaping circuit (2). Among them, the signal output end of the adaptive on-time generation core circuit (1) is connected to the signal input end of the output shaping circuit (2); the adaptive on-time generation core circuit (1) generates a current that adapts to the input voltage and output voltage of the DC-DC converter. This current is compared with a reference current and provides an input signal for the output shaping circuit (2). The output shaping circuit (2) quickly shapes the output signal of the adaptive on-time generation core circuit (1) to obtain an adaptive on-time.

[0006] Further, the adaptive on-time generation core circuit (1) includes: resistor R1, resistor R2, resistor R4, resistor R5, resistor R6, operational amplifier A1, operational amplifier A2, NMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M7, capacitor C1, switch S1, and a controlled resistor R3. One end of resistor R1 is connected to the input terminal Vin of the DC-DC converter. The other end of resistor R1 is respectively connected to one end of resistor R2 and the non-inverting input terminal of operational amplifier A1. One end of switch S1 is respectively connected to one end of capacitor C1, one end of resistor R4, the drain of NMOS transistor M7, and the internal power supply VDD. The other end of switch S1 is respectively connected to the other end of capacitor C1 and the source of PMOS transistor M2. The drain of PMOS transistor M2 is respectively connected to the gate of PMOS transistor M2, the gate of PMOS transistor M3, and the drain of NMOS transistor M1. The output terminal of operational amplifier A1 is connected to the gate of NMOS transistor M1. The inverting input terminal of operational amplifier A1 is respectively connected to the source of NMOS transistor M1 and the other end of the controlled resistor R3. The other end of resistor R4 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is respectively connected to the input terminal of inverter INV1, the gate of NMOS transistor M5, and the drain of NMOS transistor M4. The gate of NMOS transistor M4 is respectively connected to the output terminal of operational amplifier A2 and the gate of NMOS transistor M7. The source of NMOS transistor M4 is connected to one end of resistor R5. The source of NMOS transistor M7 is respectively connected to the inverting input terminal of operational amplifier A2 and one end of resistor R6. The non-inverting input terminal of operational amplifier A2 is connected to the reference voltage input terminal Vref. The other end of resistor R6 is respectively connected to the other end of resistor R2, the other end of the controlled resistor R3, the other end of resistor R5, and the external ground wire GND.

[0007] Further, the output shaping circuit (2) includes: an inverter INV1, an inverter INV2, an NMOS transistor M5, and an NMOS transistor M6. The output terminal of the inverter INV1 is respectively connected to the drain of the NMOS transistor M5 and the input terminal of the inverter INV2. The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6. The gate of the NMOS transistor M6 is respectively connected to the output terminal of the inverter INV2 and the circuit output terminal Ton_rst. The source of the NMOS transistor M6 is connected to the external ground wire GND.

[0008] Further, in the adaptive conduction time generation core circuit (1), the DC gains of the operational amplifier A1 and the operational amplifier A2 are both much greater than 1. The resistance value of the resistor R1 is (k - 1) times that of the resistor R2. The controlled resistor R3 is controlled by the output voltage of the DC-DC converter, and the resistance value R 3 of the controlled resistor R3 is α times the output voltage V out of the DC-DC converter, where α < 1. The NMOS transistor M1, the resistor R1, the resistor R2, the operational amplifier A1, and the controlled resistor R3 form a discharge current generation circuit and generate a discharge current I in adaptive to the input voltage V out of the DC-DC converter and its output voltage V R3 and not changing with the plate voltage of the capacitor C1. The discharge current I R3 , that is, the current flowing through the controlled resistor R3, and I R3 = V in / (kαV out ). The PMOS transistors M2 and M3 have the same channel width-to-length ratio. When the upper power transistor of the DC-DC converter is turned off and the lower power transistor is turned on, the switch S1 is closed, and the lower plate voltage V A of the capacitor C1 is reset to a high level, that is, V A = V DD , where V DD is the internal power supply VDD voltage, thereby establishing an initial state. At this time, the initial current flowing through the resistor R4 , where R 4 is the resistance value of the resistor R4, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, and (W / L) 2 is the channel width-to-length ratio of the PMOS transistor M2.

[0009] Further, in the adaptive conduction time generation core circuit (1), when the upper power transistor of the DC-DC converter is turned on and the switch S1 is turned off, the current I R3 flowing through the controlled resistor R3 discharges the lower plate of the capacitor C1, and the discharge time length, that is, the conduction time of the upper power transistor of the DC-DC converter, is ton The resistor R4 and the PMOS transistor M3 form a source follower structure, so the voltage drop ΔV of the lower plate of the capacitor C1 A is equal to the change in the source voltage ΔV of the PMOS transistor M3 B with ΔV B = ΔV A = (V in t on ) / (kαV out C 1 ), where V in is the input voltage Vin at the input of the DC-DC converter, V out is the output voltage of the DC-DC converter, C 1 is the capacitance value of the capacitor C1, k is the resistance ratio coefficient of the resistor R1 and the resistor R2, and the resistance value of the resistor R1 is (k - 1) times that of the resistor R2. α is the coefficient of the controlled resistor R3's resistance value R 3 and V out , that is, R 3 = αV out ; The operational amplifier A2, the NOMS transistor M7, the NMOS transistor M4, the resistor R5 and the resistor R6 form a reference current generation circuit. The resistor R5 and the resistor R6 are exactly the same, the NMOS transistor M4 and the NMOS transistor M7 are exactly the same. The resistor R4, the PMOS transistor M3, the NMOS transistor M4 and the resistor R5 form a current comparator circuit. The discharge time length, that is, the conduction time t of the power transistor on the DC-DC converter on = (I 0 kαR 4 C 1 V out ) / V in , which is proportional to the output voltage V of the DC-DC converter out and inversely proportional to the input voltage V of the DC-DC converter in . Where, I 0 = (V ref / R 6 ) - I R4,0 , V ref is the voltage of the reference voltage input terminal Vref, R 6 is the resistance value of the resistor R6, I R4,0 is the initial current flowing through the resistor R4, and R 4 is the resistance value of the resistor R4.

[0010] Furthermore, when the DC-DC converter is in the continuous conduction mode, the conduction time t of the power transistor on it on has t on = dT = (V out / V in)T, where d is the duty cycle of the conduction time of the upper power transistor, T is the switching period of the DC-DC converter, V in is the input voltage Vin at the input end of the DC-DC converter, V out is the output voltage of the DC-DC converter. Then, the switching period T of the DC-DC converter is T = I 0 kαR 4 C 1 , where I 0 =(V ref / R 6 ) - I R4,0 , V ref is the voltage at the reference voltage input end Vref, R 6 is the resistance value of resistor R6, I R4,0 is the initial current flowing through resistor R4, k is the resistance value ratio coefficient of resistor R1 and resistor R2, and the resistance value of resistor R1 is (k - 1) times that of resistor R2. α is the coefficient of the resistance value R 3 of the controlled resistor R3 and V out , that is, R 3 =αV out , R 4 is the resistance value of resistor R4, C 1 is the capacitance value of capacitor C1.

[0011] Furthermore, in the output shaping circuit (2), when the voltage at the output end of the adaptive conduction time generation core circuit (1), that is, the drain voltage of PMOS transistor M3, turns high, the input voltage of inverter INV1 increases, the output voltage of inverter IV2 increases, NMOS transistors M5 and M6 conduct. At this time, the output voltage of inverter INV1 will be quickly pulled to a low potential, and then the output end of inverter INV2 will be quickly pulled to a high potential, thereby improving the shaping efficiency and flipping speed of the circuit.

[0012] The advantages and beneficial effects of the present invention are as follows:

[0013] By providing an adaptive conduction time generation circuit for a DC-DC converter, the present invention uses NMOS transistor M1, resistor R1, resistor R2, operational amplifier A1, and controlled resistor R3 (where the controlled resistor R3 is controlled by the output voltage V out of the DC-DC converter) to generate a discharge current I R3 that is adaptive to the input voltage and output voltage of the DC-DC converter and does not change with the plate voltage of capacitor C1. The source follower composed of resistor R4 and PMOS transistor M3 is used to make the current I R4 of resistor R4 and the discharge current I R3Related, a current comparator is formed by using resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5, and by comparing current I R4 with reference current I R6 to achieve the output flip of the current comparator, thereby effectively reducing the system power consumption and improving the comparison speed. An output shaping circuit is formed by using inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6 to improve the shaping efficiency and flip speed of the circuit, so as to realize a high-performance adaptive on-time generation circuit. Description of the Drawings

[0014] Figure 1 is the schematic diagram of a traditional adaptive on-time generation circuit;

[0015] Figure 2 is the schematic diagram of an adaptive on-time generation circuit for a DC-DC converter according to a preferred embodiment provided by the present invention;

[0016] Figure 3 is the characteristic simulation diagram of an adaptive on-time generation circuit for a DC-DC converter according to a preferred embodiment provided by the present invention. Detailed Embodiments

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and detailedly described with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention.

[0018] The technical solution of the present invention to solve the above technical problems is:

[0019] In the embodiment of the present application, NMOS transistor M1, resistor R1, resistor R2, operational amplifier A1, and controlled resistor R3 (wherein, the controlled resistor R3 is controlled by the output voltage V of the DC-DC converter) are used to generate a discharge current I that is adaptive to the input voltage and output voltage of the DC-DC converter and does not change with the plate voltage of capacitor C1. A source follower is formed by using resistor R4 and PMOS transistor M3 to make the current I of resistor R4 related to the discharge current I. A current comparator is formed by using resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5, and by comparing current I out with reference current I R3 to achieve the output flip of the current comparator, thereby effectively reducing the system power consumption and improving the comparison speed. An output shaping circuit is formed by using inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6 to improve the shaping efficiency and flip speed of the circuit, so as to realize a high-performance adaptive on-time generation circuit. R4 with the discharge current I R3 Related, a current comparator is formed by using resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5, and by comparing current I R4 with reference current I R6 to achieve the output flip of the current comparator, thereby effectively reducing the system power consumption and improving the comparison speed. An output shaping circuit is formed by using inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6 to improve the shaping efficiency and flip speed of the circuit, so as to realize a high-performance adaptive on-time generation circuit.

[0020] To better understand the above technical solution, the following will combine the accompanying drawings of the specification and specific implementation manners to elaborate on the above technical solution in detail.

[0021] Embodiment

[0022] An adaptive on-time generation circuit for a DC-DC converter, as Figure 2 shown, includes an adaptive on-time generation core circuit 1 and an output shaping circuit 2;

[0023] Wherein, the signal output end of the adaptive on-time generation core circuit 1 is connected to the signal input end of the output shaping circuit 2; the adaptive on-time generation core circuit 1 generates a current that is adaptive to the input voltage and output voltage of the DC-DC converter, this current is compared with a reference current and provides an input signal for the output shaping circuit 2, and the output shaping circuit 2 quickly shapes the output signal of the adaptive on-time generation core circuit 1 to obtain an adaptive on-time.

[0024] As a preferred technical solution, as Figure 2As shown, the adaptive conduction time generation core circuit 1 includes: resistor R1, resistor R2, resistor R4, resistor R5, resistor R6, operational amplifier A1, operational amplifier A2, NMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M7, capacitor C1, switch S1, and controlled resistor R3. One end of resistor R1 is connected to the input terminal Vin of the DC-DC converter, and the other end of resistor R1 is respectively connected to one end of resistor R2 and the non-inverting input terminal of operational amplifier A1. One end of switch S1 is respectively connected to one end of capacitor C1, one end of resistor R4, the drain of NMOS transistor M7, and the internal power supply VDD, and the other end of switch S1 is respectively connected to the other end of capacitor C1 and the source of PMOS transistor M2. The drain of PMOS transistor M2 is respectively connected to the gate of PMOS transistor M2, the gate of PMOS transistor M3, and the drain of NMOS transistor M1. The output terminal of operational amplifier A1 is connected to the gate of NMOS transistor M1, and the inverting input terminal of operational amplifier A1 is respectively connected to the source of NMOS transistor M1 and the other end of controlled resistor R3. The other end of resistor R4 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is respectively connected to the input terminal of inverter INV1, the gate of NMOS transistor M5, and the drain of NMOS transistor M4. The gate of NMOS transistor M4 is respectively connected to the output terminal of operational amplifier A2 and the gate of NMOS transistor M7. The source of NMOS transistor M4 is connected to one end of resistor R5. The source of NMOS transistor M7 is respectively connected to the inverting input terminal of operational amplifier A2 and one end of resistor R6. The non-inverting input terminal of operational amplifier A2 is connected to the reference voltage input terminal Vref. The other end of resistor R6 is respectively connected to the other end of resistor R2, the other end of controlled resistor R3, the other end of resistor R5, and the external ground wire GND.

[0025] The output shaping circuit 2 includes: inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6. The output terminal of inverter INV1 is respectively connected to the drain of NMOS transistor M5 and the input terminal of inverter INV2. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M6. The gate of NMOS transistor M6 is respectively connected to the output terminal of inverter INV2 and the circuit output terminal Ton_rst. The source of NMOS transistor M6 is connected to the external ground wire GND.

[0026] In the adaptive conduction time generation core circuit 1, the DC gains of both operational amplifier A1 and operational amplifier A2 are much greater than 1. The resistance value of resistor R1 is (k - 1) times that of resistor R2. The controlled resistor R3 is controlled by the output voltage of the DC-DC converter, and the resistance value R of the controlled resistor R3 3 is the output voltage V of the DC-DC converter outα times, where α < 1; NMOS transistor M1, resistor R1, resistor R2, operational amplifier A1, and controlled resistor R3 form a discharge current generation circuit for capacitor C1 and generate a discharge current I that is the input voltage of the adaptive DC-DC converter and its output voltage and does not change with the plate voltage of capacitor C1 R3 (i.e., the current flowing through the controlled resistor R3), then there is

[0027]

[0028] In the formula, V in is the input voltage Vin at the input terminal of the DC-DC converter. PMOS transistors M2 and M3 have the same channel width-to-length ratio. When the upper power transistor of the DC-DC converter is turned off and the lower power transistor is turned on, switch S1 is closed, and the lower plate voltage V A of capacitor C1 is reset to a high level (V A = V DD , where V DD is the internal power supply VDD voltage), thereby establishing an initial state. At this time, the initial current I R4,0 flowing through resistor R4 is

[0029]

[0030] In the formula, R 4 is the resistance value of resistor R4, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, (W / L) 2 is the channel width-to-length ratio of PMOS transistor M2.

[0031] When the upper power transistor of the DC-DC converter is turned on and switch S1 is disconnected, current I R3 discharges the lower plate of capacitor C1, and the discharge time length (i.e., the conduction time of the upper power transistor of the DC-DC converter) is t on , then the voltage drop ΔV A of the lower plate of capacitor C1 is

[0032]

[0033] In the formula, C 1 is the capacitance value of capacitor C1. Resistor R4 and PMOS transistor M3 form a source follower structure. Therefore, the change in the source voltage ΔV B of PMOS transistor M3 has ΔV B = ΔV A , and operational amplifier A2, NOMS transistor M7, NMOS transistor M4, resistor R5, and resistor R6 form a reference current generation circuit. The current I R6 flowing through resistor R6 is

[0034]

[0035] Wherein, V ref is the voltage of the reference voltage input terminal Vref, which is provided by an external bandgap reference circuit, and R 6 is the resistance value of resistor R6. Resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5 form a current comparator circuit, thereby effectively reducing the system power consumption and increasing the comparison speed. Among them, resistor R5 is exactly the same as resistor R6, and NMOS transistor M4 is exactly the same as NMOS transistor M7. Then the flip condition of the output terminal of the current comparator (i.e., the drain of PMOS transistor M3) is

[0036]

[0037] The discharge time length (i.e., the conduction time of the power transistor on the DC-DC converter) t on is

[0038]

[0039] Wherein, I 0 =(V ref / R 6 ) - I R4,0 . Equation (6) shows that the conduction time t on of the power transistor on the DC-DC converter is proportional to the output voltage V out of the DC-DC converter and inversely proportional to the input voltage V in of the DC-DC converter. When the DC-DC converter is in continuous conduction mode, for the conduction time t on of the power transistor on the DC-DC converter, there is t on = dT = (V out / V in )T, where d is the duty cycle of the conduction time of the power transistor, and T is the switching period of the DC-DC converter. Then the switching period T of the DC-DC converter is

[0040] T = I 0 kαR 4 C 1 (7)

[0041] It can be obtained from equation (7) that by reasonably selecting parameters such as the resistance value of resistor R4, the resistance value of resistor R6, the proportionality coefficient k, the voltage-controlled resistance coefficient α, and the capacitance value of capacitor C1, a high-performance constant-period adaptive conduction time can be obtained.

[0042] In the output shaping circuit 2, when the voltage at the output terminal of the adaptive on-time generation core circuit 1 (the drain voltage of PMOS transistor M3) rises, the input voltage of inverter INV1 increases, and the output voltage of inverter IV2 increases. When NMOS transistors M5 and M6 are turned on, the output voltage of inverter INV1 will be quickly pulled to a low potential at this time, and then the output terminal of inverter INV2 is quickly pulled to a high potential, thereby improving the shaping efficiency and flip speed of the circuit.

[0043] Figure 3 This is the on-time simulation curve generated by an adaptive on-time generation circuit for a DC-DC converter of the present invention when the input voltage of the DC-DC converter is 20V and the output voltage is 10V. The simulation results show that when the switching period of the DC-DC converter is 2 μs and the upper power transistor conducts at 2 μs, the output terminal of the adaptive on-time generation circuit of the present invention flips after 1.007 μs (note: the theoretical value of this circuit is 1 μs), and its absolute error is only 0.7%.

[0044] In the above embodiments of the present application, an adaptive on-time generation circuit for a DC-DC converter includes an adaptive on-time generation core circuit and an output shaping circuit. The embodiments of the present application use NMOS transistor M1, resistor R1, resistor R2, operational amplifier A1, and a controlled resistor R3 (wherein, the controlled resistor R3 is controlled by the output voltage V of the DC-DC converter) to generate a discharge current I that adapts to the input voltage and output voltage of the DC-DC converter and does not change with the plate voltage of capacitor C1. The source follower is formed by resistor R4 and PMOS transistor M3 to make the current I of resistor R4 related to the discharge current I. A current comparator is formed by resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5, and the output of the current comparator is flipped by comparing the current I with the reference current I, thereby effectively reducing the system power consumption and increasing the comparison speed. The output shaping circuit is formed by inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6 to improve the shaping efficiency and flip speed of the circuit, thereby realizing a high-performance adaptive on-time generation circuit. out control) to generate a discharge current I that adapts to the input voltage and output voltage of the DC-DC converter and does not change with the plate voltage of capacitor C1 R3 and uses resistor R4 and PMOS transistor M3 to form a source follower so that the current I of resistor R4 R4 is related to the discharge current I R3 and uses resistor R4, PMOS transistor M3, NMOS transistor M4, and resistor R5 to form a current comparator and realizes the output flip of the current comparator by comparing the current I R4 with the reference current I R6 to effectively reduce the system power consumption and increase the comparison speed, and uses inverter INV1, inverter INV2, NMOS transistor M5, and NMOS transistor M6 to form an output shaping circuit to improve the shaping efficiency and flip speed of the circuit, thereby realizing a high-performance adaptive on-time generation circuit.

[0045] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions.

[0046] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

[0047] The above embodiments should be understood as being only for illustrative purposes of the present invention and not for limiting the scope of protection of the present invention. After reading the content described in the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. An adaptive on-time generation circuit for a DC-DC converter, characterized in that, it includes an adaptive on-time generation core circuit (1) and an output shaping circuit (2). Among them, the signal output end of the adaptive on-time generation core circuit (1) is connected to the signal input end of the output shaping circuit (2); the adaptive on-time generation core circuit (1) generates a current that adapts to the input voltage and output voltage of the DC-DC converter. This current is compared with a reference current and provides an input signal for the output shaping circuit (2). The output shaping circuit (2) quickly shapes the output signal of the adaptive on-time generation core circuit (1) to obtain an adaptive on-time; The adaptive on-time generation core circuit (1) includes: resistor R1, resistor R2, resistor R4, resistor R5, resistor R6, operational amplifier A1, operational amplifier A2, NMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M7, capacitor C1, switch S1, and a controlled resistor R3. One end of resistor R1 is connected to the input terminal Vin of the DC-DC converter. The other end of resistor R1 is respectively connected to one end of resistor R2 and the non-inverting input terminal of operational amplifier A1. One end of switch S1 is respectively connected to one end of capacitor C1, one end of resistor R4, the drain of NMOS transistor M7, and the internal power supply VDD. The other end of switch S1 is respectively connected to the other end of capacitor C1 and the source of PMOS transistor M2. The drain of PMOS transistor M2 is respectively connected to the gate of PMOS transistor M2, the gate of PMOS transistor M3, and the drain of NMOS transistor M1. The output terminal of operational amplifier A1 is connected to the gate of NMOS transistor M1. The inverting input terminal of operational amplifier A1 is respectively connected to the source of NMOS transistor M1 and the other end of the controlled resistor R3. The other end of resistor R4 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is respectively connected to the input terminal of inverter INV1, the gate of NMOS transistor M5, and the drain of NMOS transistor M4. The gate of NMOS transistor M4 is respectively connected to the output terminal of operational amplifier A2 and the gate of NMOS transistor M7. The source of NMOS transistor M4 is connected to one end of resistor R5. The source of NMOS transistor M7 is respectively connected to the inverting input terminal of operational amplifier A2 and one end of resistor R6. The non-inverting input terminal of operational amplifier A2 is connected to the reference voltage input terminal Vref. The other end of resistor R6 is respectively connected to the other end of resistor R2, the other end of the controlled resistor R3, the other end of resistor R5, and the external ground wire GND.

2. The adaptive on-time generation circuit for a DC-DC converter according to claim 1, characterized in that, The output shaping circuit (2) includes: an inverter INV1, an inverter INV2, an NMOS transistor M5, and an NMOS transistor M6. The output terminal of the inverter INV1 is respectively connected to the drain of the NMOS transistor M5 and the input terminal of the inverter INV2. The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6. The gate of the NMOS transistor M6 is respectively connected to the output terminal of the inverter INV2 and the circuit output terminal Ton_rst. The source of the NMOS transistor M6 is connected to the external ground wire GND.

3. The adaptive on-time generation circuit for a DC-DC converter according to claim 1, characterized in that In the adaptive turn-on time generation core circuit (1), the DC gains of operational amplifiers A1 and A2 are both much greater than 1. The resistance value of resistor R1 is (k - 1) times that of resistor R2. The controlled resistor R3 is controlled by the output voltage of the DC-DC converter, and the resistance value R 3 of the controlled resistor R3 is α times the output voltage V out of the DC-DC converter, where α < 1. The NMOS transistor M1, resistor R1, resistor R2, operational amplifier A1, and controlled resistor R3 form a discharge current generation circuit and generate a discharge current I in that is adaptive to the input voltage V out of the DC-DC converter and its output voltage V R3 , and does not change with the plate voltage of capacitor C1. The discharge current I R3 is the current flowing through the controlled resistor R3, and I R3 = V in / (kαV out ). k is the resistance ratio coefficient of resistor R1 and resistor R2. The PMOS transistors M2 and M3 have the same channel width-to-length ratio. When the upper power transistor of the DC-DC converter is turned off and the lower power transistor is turned on, the switch S1 is closed, and the lower plate voltage V A of capacitor C1 is reset to the high level, that is, V A = V DD , where V DD is the internal power supply VDD voltage, thereby establishing an initial state. At this time, the initial current flowing through resistor R4 where, R 4 is the resistance value of resistor R4, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, and (W / L) 2 is the channel width-to-length ratio of PMOS transistor M2.

4. The adaptive on-time generation circuit for a DC-DC converter according to claim 3, characterized in that In the described adaptive turn-on time generation core circuit (1), when the upper power transistor of the DC-DC converter conducts and the switch S1 is turned off, the current I flowing through the controlled resistor R3 R3 discharges the lower plate of the capacitor C1, and the discharge time length, which is the turn-on time of the upper power transistor of the DC-DC converter, is t on . The resistor R4 and the PMOS transistor M3 form a source follower structure, so the voltage drop ΔV of the lower plate of the capacitor C1 A and the change amount ΔV of the source voltage of the PMOS transistor M3 B have ΔV B =ΔV A =(V in t on ) / (kαV out C 1 ), where V in is the input voltage Vin of the DC-DC converter, V out is the output voltage of the DC-DC converter, C 1 is the capacitance value of the capacitor C1, k is the resistance ratio coefficient of the resistor R1 and the resistor R2, and the resistance value of the resistor R1 is (k - 1) times that of the resistor R2, and α is the coefficient of the resistance value R 3 of the controlled resistor R3 and V out , that is, R 3 =αV out ; The operational amplifier A2, the NOMS transistor M7, the NMOS transistor M4, the resistor R5, and the resistor R6 form a reference current generation circuit. The resistor R5 and the resistor R6 are exactly the same, the NMOS transistor M4 and the NMOS transistor M7 are exactly the same. The resistor R4, the PMOS transistor M3, the NMOS transistor M4, and the resistor R5 form a current comparator circuit. The discharge time length, which is the turn-on time t on of the upper power transistor of the DC-DC converter =(I 0 kαR 4 C 1 V out ) / V in , which is proportional to the output voltage V out of the DC-DC converter and inversely proportional to the input voltage V in of the DC-DC converter. Among them, I 0 =(V ref / R 6 )-I R4,0 , V ref is the voltage of the reference voltage input terminal Vref, R 6 is the resistance value of the resistor R6, I R4,0 is the initial current flowing through the resistor R4, and R 4 is the resistance value of the resistor R4.

5. The adaptive on-time generation circuit for a DC-DC converter according to claim 4, characterized in that When the DC-DC converter is in continuous conduction mode, the conduction time t of its upper power transistor on has t on = dT = (V out / V in )T, where d is the duty cycle of the conduction time of the upper power transistor, T is the switching period of the DC-DC converter, V in is the input voltage Vin at the input end of the DC-DC converter, V out is the output voltage of the DC-DC converter. Then the switching period T of the DC-DC converter = I 0 kαR 4 C 1 , where I 0 = (V ref / R 6 ) - I R4,0 , V ref is the voltage at the reference voltage input end Vref, R 6 is the resistance value of resistor R6, I R4,0 is the initial current flowing through resistor R4, k is the resistance value ratio coefficient of resistor R1 and resistor R2, and the resistance value of resistor R1 is (k - 1) times that of resistor R2. α is the coefficient of the resistance value R 3 of the controlled resistor R3 and V out , that is, R 3 = αV out , R 4 is the resistance value of resistor R4, and C 1 is the capacitance value of capacitor C1.

6. The adaptive on-time generation circuit for a DC-DC converter according to claim 2, characterized in that In the output shaping circuit (2), when the voltage at the output terminal of the adaptive on-time generation core circuit (1), i.e., the drain voltage of the PMOS transistor M3, turns high, the voltage at the input terminal of the inverter INV1 increases, the voltage at the output terminal of the inverter IV2 increases, the NMOS transistors M5 and M6 conduct. At this time, the voltage at the output terminal of the inverter INV1 will be quickly pulled to a low potential, and further the output terminal of the inverter INV2 will be quickly pulled to a high potential, thereby improving the shaping efficiency and inversion speed of the circuit.

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