Surface acoustic wave (SAW) filter and method for manufacturing the same

Abstract

The present application provides a surface acoustic wave (SAW) filter, comprising: a bottom substrate; a piezoelectric layer disposed above the bottom substrate, wherein the piezoelectric layer has a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a lower cavity disposed below the piezoelectric layer; an interdigital transducer (IDT) disposed on the top surface of the piezoelectric layer; and a back electrode disposed on the bottom surface of the piezoelectric layer, wherein the back electrode is exposed in the lower cavity. The present application also provides a method for manufacturing a surface acoustic wave (SAW) filter.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a surface acoustic wave (SAW) filter and a manufacturing method thereof. Background Art

[0002] Surface acoustic wave (SAW) devices, such as SAW resonators and SAW filters, are used in many applications such as radio frequency (RF) filters. A typical SAW filter includes a plurality of interdigital transducers (IDTs) formed on a piezoelectric substrate. The plurality of IDTs are connected in series or in parallel.

[0003] As the use of SAW filters in modern RF communication systems increases, there is a growing need for SAW filters with improved quality factor (Q). Summary of the invention

[0004] According to one aspect of the present disclosure, a surface acoustic wave (SAW) filter is provided. The SAW filter includes: a bottom substrate; a piezoelectric layer disposed above the bottom substrate, and the piezoelectric layer has a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a lower cavity disposed below the piezoelectric layer; an interdigital transducer (IDT) disposed on the top surface of the piezoelectric layer; and a back electrode disposed on the bottom surface of the piezoelectric layer, and the back electrode is exposed in the lower cavity.

[0005] According to another aspect of the present disclosure, a SAW filter is provided. The SAW filter includes: a bottom substrate; a piezoelectric layer disposed above the bottom substrate, and the piezoelectric layer has a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a lower cavity disposed below the piezoelectric layer; a back electrode disposed on the top surface of the piezoelectric layer; and an interdigital transducer IDT disposed on the bottom surface of the piezoelectric layer, and the interdigital portion of the interdigital transducer is exposed in the lower cavity.

[0006] According to one aspect of the present disclosure, a method for manufacturing a surface acoustic wave (SAW) filter is provided. The method includes: obtaining a piezoelectric substrate; forming a back electrode on a first portion of the piezoelectric substrate; forming a sacrificial layer covering the back electrode on the first portion of the piezoelectric substrate; forming a first dielectric layer covering the sacrificial layer on the first portion of the piezoelectric substrate; bonding a bottom substrate to the first dielectric layer; removing a second portion of the piezoelectric substrate to expose a first portion of the piezoelectric substrate, the first portion of the piezoelectric substrate constituting a piezoelectric layer; forming an interdigital transducer (IDT) on the piezoelectric layer; forming one or more release holes passing through the piezoelectric layer; etching and releasing the sacrificial layer through the one or more release holes to form a lower cavity exposing the back electrode.

[0007] According to another aspect of the present disclosure, a method for manufacturing a surface acoustic wave (SAW) filter is provided. The method includes: obtaining a piezoelectric substrate; forming an interdigital transducer (IDT) on a first portion of the piezoelectric substrate; forming a sacrificial layer covering the interdigital portion of the IDT on the first portion of the piezoelectric substrate; forming a first dielectric layer covering the sacrificial layer and the IDT on the first portion of the piezoelectric substrate; bonding a bottom substrate to the first dielectric layer; removing a second portion of the piezoelectric substrate to expose a first portion of the piezoelectric substrate, the first portion of the piezoelectric substrate constituting a piezoelectric layer; forming a back electrode on the piezoelectric layer; forming one or more release holes passing through the piezoelectric layer; etching and releasing the sacrificial layer to form a lower cavity below the interdigital portion of the IDT. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate the disclosed embodiments and, together with the description, serve to explain the disclosed embodiments.

[0009] Figure 1A is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0010] Figure 1B According to one embodiment of the present disclosure, Figure 1A A top view of a selected portion of a SAW filter;

[0011] Figure 1C According to one embodiment of the present disclosure, Figure 1A A top view of other selected portions of the SAW filter;

[0012] Figure 1D is a top view of an interdigital transducer IDT according to an embodiment of the present disclosure;

[0013] Figure 1E is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0014] Figure 2 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 1A Flow chart of the SAW filter process;

[0015] Figures 3A-3T According to one embodiment of the present disclosure, Figure 2 A cross-sectional view of a structure formed in a process of

[0016] Figure 4 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 1E Flow chart of the SAW filter process;

[0017] Figure 5A is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0018] Figure 5B According to one embodiment of the present disclosure, Figure 5A A top view of a selected portion of a SAW filter;

[0019] Figure 5C According to one embodiment of the present disclosure, Figure 5A A top view of a selected portion of a SAW filter;

[0020] Figure 5D is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0021] Figure 6 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 5A Flow chart of the SAW filter process;

[0022] Figures 7A-7T According to one embodiment of the present disclosure, Figure 6 A cross-sectional view of a structure formed in a process of

[0023] Figure 8 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 5D Flowchart of the SAW filter process. DETAILED DESCRIPTION

[0024] The following text describes the present disclosure in detail in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present disclosure. The protection scope of the present invention includes changes made to the structure, method or function by ordinary technicians in this field based on these embodiments.

[0025] In order to facilitate the presentation of the drawings in the present disclosure, the size of some structures or parts may be enlarged relative to other structures or parts. Therefore, the drawings in the present disclosure are only used for the purpose of illustrating the basic structure of the subject matter of the present disclosure. Unless otherwise specified, the same numbers in different drawings represent the same or similar elements.

[0026] In addition, terms indicating relative spatial positions, such as "top", "bottom", "upper", "lower", "above", "below", etc., are used herein to describe the relationship between an element or feature depicted in a figure and another element or feature therein for purposes of explanation. Terms indicating relative spatial positions may refer to positions other than those depicted in the drawings when the device is in use or operation. For example, if the device shown in the figure is turned over, a unit described as being "below" or "below" another element or feature would be "above" the other element or feature. Thus, the illustrative term "below" may include both above and below positions. The device may be oriented in other ways (e.g., rotated 90 degrees or facing another direction), and descriptive terms appearing in the text and relating to space should be interpreted accordingly. When a component or layer is referred to as being "on" or "connected to" another component or layer, it can be directly on or directly connected to the other component or layer, or there may be intervening components or layers.

[0027] Figure 1A is a cross-sectional view of a SAW filter 1000 provided according to an embodiment of the present disclosure. Figure 1B is a top view of selected portions of a SAW filter 1000 provided according to one embodiment of the present disclosure. Figure 1B The cross section of the selected part along the line A-A' is as follows Figure 1A shown. Figure 1C is a top view of other selected portions of the SAW filter 1000 provided according to one embodiment of the present disclosure. Figure 1C The cross section of the selected part along the line BB' is as follows Figure 1A As shown. Figure 1A , Figure 1B as well as Figure 1C As shown, the SAW filter 1000 includes: a bottom substrate 210; a piezoelectric layer 140 arranged above the bottom substrate 210, the piezoelectric layer 140 having a bottom surface 140a facing the bottom substrate 210 and a top surface 140b opposite to the bottom surface 140a; a lower cavity 500a arranged below the piezoelectric layer 140; an interdigital transducer IDT130 arranged on the top surface 140b of the piezoelectric layer 140; and a back electrode 150 arranged on the bottom surface 140a of the piezoelectric layer 140 and exposed in the lower cavity 500a.

[0028] Figure 1D FIG. 1 is a top view of an interdigital transducer IDT according to an embodiment of the present disclosure. Figure 1DAs shown, the IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133. The interdigital portion 133 includes a first group of electrode fingers 1331 coupled to the first input and output terminal 131 and a second group of electrode fingers 1332 coupled to the second input and output terminal 132. The second group of electrode fingers 1332 are staggered and parallel to the first group of electrode fingers 1331.

[0029] Reference again Figure 1A , Figure 1B as well as Figure 1C , the first dielectric layer 180 is disposed between the piezoelectric layer 140 and the bottom substrate 210 and surrounds the lower cavity 500a. In other words, the first dielectric layer 180 and the piezoelectric layer 140 together surround the lower cavity 500a.

[0030] The base substrate 210 may be formed of Si, SiO 2 , polysilicon, silicon carbide, sapphire (Al 2 O 3 ), or a stacked combination of two or more of these materials. The base substrate 210 may be bonded to the first dielectric layer 180 .

[0031] The upper cavity 500b is disposed above the piezoelectric layer 140. The top substrate 250 is disposed above the upper cavity 500b and covers the upper cavity 500b. The second dielectric layer 240 is disposed between the piezoelectric layer 140 and the top substrate 250 and surrounds the upper cavity 500b. In other words, the top substrate 250, the second dielectric layer 240 and the piezoelectric layer 140 together surround the upper cavity 500b.

[0032] The top substrate 250 may be formed of Si, SiO 2 , polysilicon, silicon carbide, sapphire (Al 2 O 3 ), or a stacked combination of two or more of these materials. The top substrate 250 may be bonded to the second dielectric layer 240 .

[0033] One or more release holes 145 are formed in the piezoelectric layer 140. The one or more release holes 145 are used to form the lower cavity 500a in the etching and release process. Figure 1B As shown, a back electrode contact hole 148 is formed in the piezoelectric layer 140 , and the back electrode contact hole 148 exposes a portion of the top surface of the back electrode 150 .

[0034] The pad metal layer 310 is disposed above the IDT 130. The first portion 311 of the pad metal layer 310 is disposed above the first input and output terminal 131 of the IDT 130; the second portion 312 of the pad metal layer 310 is disposed above the input and output terminal 132 of the second IDT 130. The third portion 313 of the pad metal layer 310 (also referred to as "back electrode pad metal film 313") is formed above the back electrode contact hole 148 and is electrically connected to the exposed portion of the top surface of the back electrode 150 through the back electrode contact hole 148.

[0035] A first through silicon via (TSV) 441 and a second through silicon via TSV 442 are formed in the top substrate 250 and the second dielectric layer 240. The first TSV 441 exposes the first portion 311 of the pad metal layer 310, and the second TSV 442 exposes the second portion 312 of the pad metal layer 310.

[0036] The redistribution metal layer 260 is disposed on the top substrate 250 . The first portion 261 of the redistribution metal layer 260 is electrically connected to the first portion 311 of the pad metal layer 310 through the first TSV 441 , and the second portion 262 of the redistribution metal layer is electrically connected to the second portion 312 of the pad metal layer 310 through the second TSV 442 .

[0037] The passivation layer 290 is disposed on the top substrate 250 and fills in the first TSV 441 and the second TSV 442. The passivation layer 290 is formed with a first window 291 exposing the first portion 261 of the redistribution metal layer 260 and a second window 292 exposing the second portion 262 of the redistribution metal layer 260.

[0038] An under bump metallization (UBM) layer 300 is disposed on the passivation layer 290. A first portion 301 of the UBM layer 300 is disposed over the first portion 261 of the redistribution metal layer 260 and is electrically connected to the first portion 261 of the redistribution metal layer 260 through the first window 291; a second portion 302 of the UBM layer 300 is disposed over the second portion 262 of the redistribution metal layer 260 and is electrically connected to the second portion 262 of the redistribution metal layer 260 through the second window 292.

[0039] The first solder bump 281 and the second solder bump 282 are disposed over the top substrate 250. The first solder bump 281 is disposed over the first portion 301 of the UBM layer 300 and is electrically connected to the first portion 261 of the redistribution metal layer 260 through the first portion 301 of the UBM layer 300. The second solder bump 282 is disposed over the second portion 302 of the UBM layer 300 and is electrically connected to the second portion 262 of the redistribution metal layer 260 through the second portion 302 of the UBM layer 300.

[0040] Figure 1E1 is a cross-sectional view of a SAW filter 1001 provided according to an embodiment of the present disclosure. The difference between the SAW filter 1001 and the SAW filter 1000 is that the SAW filter 1001 includes a non-conductive layer 320 and a buffer layer 330 disposed between the first dielectric layer 180 and the bottom substrate 210. Specifically, the non-conductive layer 320 is disposed above the bottom substrate 210, and the buffer layer 330 is disposed above the non-conductive layer 320. The functions of the non-conductive layer 320 and the buffer layer 330 are to make the bonding of the bottom substrate 210 easier and to ensure the quality of the bonding, or to improve the performance of the SAW filter 1001 by improving the quality factor Q of the SAW resonator. The non-conductive layer 320 may be formed of polycrystalline silicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials. The non-conductive layer 320 is used to improve the quality factor Q of the SAW resonator. The buffer layer 330 may be formed of silicon nitride, silicon oxide, or a stacked combination of these materials. The buffer layer 330 serves to create a suitable bonding surface for the base substrate 210 or to balance the warpage of the base substrate 210 , thereby allowing the base substrate 210 to be bonded to the first dielectric layer 180 more smoothly.

[0041] In some optional embodiments, the SAW filter may include only one of the non-conductive layer 320 and the buffer layer 330. For example, the SAW filter may include the non-conductive layer 320 disposed between the first dielectric layer 180 and the bottom substrate 210. Alternatively, the SAW filter may include the buffer layer 330 disposed between the first dielectric layer 180 and the bottom substrate 210.

[0042] The structure and components of the SAW filter 1001 are the same as those of the SAW filter 1000 except for the non-conductive layer 320 and the buffer layer 330 , and thus a detailed description of the other components of the SAW filter 1001 will not be repeated.

[0043] Figure 2 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 1A Flow chart of the SAW filter process; Figures 3A-3T According to one embodiment of the present disclosure, Figure 2 A cross-sectional view of a structure formed in the process.

[0044] like Figure 3A As shown, in step S1, a piezoelectric substrate 100 is obtained. The piezoelectric substrate may be a lithium niobate or lithium tantalate single crystal substrate.

[0045] like Figure 3BAs shown, in step S2, ions are implanted into the piezoelectric substrate 100 at a predetermined implantation depth d, thereby forming an ion layer 101 at the depth d of the piezoelectric substrate 100. The ions may be helium ions or hydrogen ions. The implantation depth d may be determined based on the desired thickness of the piezoelectric layer 140. For example, the implantation depth d may be in a range from about 0.3 μm to about 10 μm. The first portion 100 a of the piezoelectric substrate 100 is disposed above the ion layer 101, and the second portion 100 b of the piezoelectric substrate 100 is disposed below the ion layer 101.

[0046] Reference Figure 3C In step S3, a back electrode 150 is formed on the first portion 100a of the piezoelectric substrate 100. The back electrode 150 may include any suitable conductive material, such as various metal materials or stacks of several conductive metal materials having conductive properties, such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), etc.

[0047] Reference Figure 3D In step S4, a sacrificial layer 170 is deposited on the first portion 100a of the piezoelectric substrate 100 and covers the back electrode 150. The sacrificial layer 170 may include Si, such as amorphous Si or polycrystalline Si.

[0048] Reference Figure 3E In step S5, the sacrificial layer 170 is patterned by etching. The patterned sacrificial layer 170 covers the back electrode 150. The sacrificial layer 170 will be removed during the subsequent etching and release process, thereby forming a lower cavity 500a.

[0049] like Figure 3F As shown, in step S6, a first dielectric layer 180 is deposited on the first portion 100a of the piezoelectric substrate 100 and covers the sacrificial layer 170. Then, the first dielectric layer 180 is surface planarized and polished by using a chemical mechanical polishing (CMP) process. The planarized first dielectric layer 180 still covers the sacrificial layer 170.

[0050] refer to Figure 3G In step S7, the base substrate 210 is bonded to the first dielectric layer 180. The base substrate 210 may include Si, SiO2, polysilicon, silicon carbide, sapphire (Al2O3), or a stacked combination of two or more of these materials.

[0051] Reference Figure 3H In step S8, Figure 3GThe structure shown is turned over and the structure is thermally annealed. The annealing temperature may range from about 400° C. to about 650° C. After the thermal annealing, the ion layer 101 in the piezoelectric substrate 100 is destroyed. The second portion 100 b of the piezoelectric substrate 100 below the ion layer 101 is removed, while the first portion 100 a of the piezoelectric substrate 100 above the ion layer 101 is retained. The first portion 100 a of the piezoelectric substrate 100 constitutes the piezoelectric layer 140 in the SAW filter 1000. The piezoelectric layer 140 has a bottom surface 140 a forming a back electrode 150, and the top surface 140 b is exposed. CMP polishing may be performed on the exposed top surface 140 b of the piezoelectric layer 140 to obtain a smooth surface and achieve the desired thickness of the piezoelectric layer 140 in the SAW filter 1000. In some embodiments, ion beam etching (IBE) or ion beam milling may be performed on the piezoelectric layer 140 to obtain a more uniform thickness.

[0052] like Fig. 3I As shown, in step S9, the piezoelectric layer 140 is etched to form one or more release holes 145 passing through the piezoelectric layer 140. Each release hole 145 exposes a portion of the sacrificial layer 170. In addition, although Fig. 3I Although not shown, in step S9, a back electrode contact hole 148 ( Figure 1B The back electrode contact hole 148 exposes a portion of the top surface of the back electrode 150 .

[0053] like Figure 3J As shown, in step S10, an IDT 130 is formed on the top surface 140b of the piezoelectric layer 140. The IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133 disposed between the first input and output terminal 131 and the second input and output terminal 132. The interdigital portion 133 is vertically aligned with the back electrode 150.

[0054] like Figure 3K As shown, in step S11, a pad metal layer 310 is formed on the IDT 130. Then, the pad metal layer 310 is patterned to form: a first portion 311 disposed above the first input and output terminal 131 of the IDT 130 and electrically connected to the IDT 130; a second portion 312 disposed above the second input and output terminal 132 of the IDT 130 and electrically connected to the IDT 130; and a third portion 313 disposed above the back electrode contact hole 148 and electrically connected to the back electrode 150 through the back electrode contact hole 148 ( Figure 3K Not shown, but Figure 1B ).

[0055] like Figure 3LAs shown, in step S12, a second dielectric layer 240 is deposited on the piezoelectric layer 140, covering the entire IDT 130, and filling one or more release holes 145. The second dielectric layer 240 can be formed of silicon oxide, silicon nitride, or a stacked combination of these materials. The second dielectric layer 240 is deposited by using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. A CMP planarization process is performed on the second dielectric layer 240 so that the top surface of the second dielectric layer 240 is parallel to the top surface 140b of the piezoelectric layer 140.

[0056] Reference Figure 3M , in step S13, the second dielectric layer 240 is patterned by etching. After the patterning process, a portion of the second dielectric layer 240 is removed to expose the interdigital portion 133 of the IDT 130 and a portion of the piezoelectric layer 140. The area of ​​the removed portion of the second dielectric layer 240 is larger than the area of ​​the interdigital portion 133 of the IDT 130. The second dielectric layer 240 covers the first input and output terminal 131 and the second input and output terminal 132 of the IDT 130, and the first portion 311 and the second portion 312 of the pad metal layer 310. In addition, in step S13, the portion of the second dielectric layer 240 filled in the one or more release holes 145 is removed to expose a portion of the sacrificial layer 170.

[0057] refer to Figure 3N In step S14, after the sacrificial layer 170 is etched and released, a lower cavity 500a is formed below the back electrode 150. The sacrificial layer 170 can be etched by a dry etching process using XeF2 plasma. The etchant and etching products of the etching process can be released through one or more release holes 145.

[0058] Reference Fig.3O In step S15, the top substrate 250 is bonded to the second dielectric layer 240. The top substrate 250, the second dielectric layer 240 and the piezoelectric layer 140 together surround the upper cavity 500b. The top substrate 250 may include Si, SiO2, polysilicon, silicon carbide, sapphire (Al2O3), or a stacked combination of two or more of these materials.

[0059] Reference Figure 3P In step S16, the top substrate 250 is thinned to a predetermined thickness.

[0060] Reference Figure 3QIn step S17, a first TSV 441 and a second TSV 442 are formed in the top substrate 250 and the second dielectric layer 240. The first TSV 441 exposes a first portion 311 of the pad metal layer 310 electrically connected to the first input and output terminal 131 of the IDT 130. The second TSV 442 exposes a second portion 312 of the pad metal layer 310 electrically connected to the second input and output terminal 132 of the IDT 130.

[0061] Reference Figure 3R In step S18, a redistribution metal layer 260 is formed on the top substrate 250 and in the first TSV 441 and the second TSV 442. The redistribution metal layer 260 is patterned to form a first portion 261 connected to the first portion 311 of the pad metal layer 310 through the first TSV 441, and a second portion 262 connected to the second portion 312 of the pad metal layer 310 through the second TSV 442. Therefore, the first portion 261 of the redistribution metal layer 260 is electrically connected to the first input and output terminals 131 of the IDT 130, and the second portion 262 of the redistribution metal layer 260 is electrically connected to the second input and output terminals 132 of the IDT 130.

[0062] Reference Figure 3S In step S19, a passivation layer 290 is formed on the top substrate 250 and covers the redistribution metal layer 260. Then, the passivation layer 290 is etched to form a first window 291 exposing a portion of the first portion 261 of the redistribution metal layer 260, and a second window 292 exposing a portion of the second portion 262 of the redistribution metal layer 260. The passivation layer 290 may include an organic material, such as polyimide. The first window 291 is not vertically aligned with the first TSV 441, and the second window 292 is not vertically aligned with the second TSV 442.

[0063] refer to Figure 3T In step S20, the UBM layer 300 is formed on the passivation layer 290. The UBM layer 300 is patterned to form a first portion 301 connected to an exposed portion of the first portion 261 of the redistribution metal layer 260 through a first window 291 of the passivation layer 290, and a second portion 302 connected to an exposed portion of the second portion 262 of the redistribution metal layer 260 through a second window 292 of the passivation layer 290. Thereafter, a first solder bump 281 is formed on the first portion 301 of the UBM layer 300 and connected to the first portion 301 of the UBM layer 300, and a second solder bump 282 is formed on the second portion 302 of the UBM layer 300 and connected to the second portion 302 of the UBM layer 302. Therefore, the first solder bump 281 is electrically connected to the first input and output terminal 131 of the IDT 130, and the second solder bump 282 is electrically connected to the second input and output terminal 132 of the IDT. Thus, as shown in FIG. Figure 1A The SAW filter 1000 shown is manufactured.

[0064] Figure 4 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 1E Flowchart of the process of the SAW filter 1001. The manufacturing process of the SAW filter 1001 is the same as the manufacturing process of the SAW filter 1000, except that, in step S7, a base substrate 210 is obtained, at least one of the non-conductive layer 320 or the buffer layer 330 is deposited on the base substrate 210, and then the base substrate 210 on which at least one of the non-conductive layer 320 or the buffer layer 330 is deposited is bonded to the first dielectric layer 180. When both the non-conductive layer 320 and the buffer layer 330 are deposited on the base substrate 210, the non-conductive layer 320 is first deposited on the base substrate 210, and then the buffer layer 330 is deposited on the non-conductive layer 320.

[0065] Except for step S7 , the manufacturing process of the SAW filter 1001 is the same as the manufacturing process of the SAW filter 1000 , and thus a detailed description of the other steps of manufacturing the SAW filter 1001 will not be repeated.

[0066] Figure 5A is a cross-sectional view of a SAW filter 2000 provided according to an embodiment of the present disclosure. Figure 5B is a top view of selected portions of a SAW filter 2000 provided according to one embodiment of the present disclosure. Figure 5B The cross section of the selected part along the line A-A' is as follows Figure 5A shown. Figure 5C is a top view of other selected portions of the SAW filter 2000 provided according to one embodiment of the present disclosure. Figure 5C The cross section of the selected part along the line BB' is as follows Figure 5C As shown. Figure 5A , Figure 5B as well as Figure 5C As shown, the SAW filter 2000 includes: a bottom substrate 210; a piezoelectric layer 140 disposed above the bottom substrate 210, the piezoelectric layer 140 having a bottom surface 140a facing the bottom substrate 210 and a top surface 140b opposite to the bottom surface 140a; a lower cavity 500a disposed below the piezoelectric layer 140; a back electrode 150 disposed on the top surface 140b of the piezoelectric layer 140; and an interdigital transducer (IDT) 130 disposed on the bottom surface 140a of the piezoelectric layer 140. The IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133. The interdigital portion 133 of the IDT 130 is exposed in the lower cavity 500a.

[0067] The first dielectric layer 180 is disposed between the piezoelectric layer 140 and the bottom substrate 210 and surrounds the lower cavity 500 a. In other words, the first dielectric layer 180 and the piezoelectric layer 140 together surround the lower cavity 500 a. The bottom substrate 210 may be bonded to the first dielectric layer 180 .

[0068] The upper cavity 500b is disposed above the piezoelectric layer 140. The top substrate 250 covers the upper cavity 500b. The second dielectric layer 240 is disposed between the piezoelectric layer 140 and the top substrate 250 and surrounds the upper cavity 500b. In other words, the top substrate 250, the second dielectric layer 240 and the piezoelectric layer 140 together surround the upper cavity 500b.

[0069] The pad metal layer 310 is disposed under the IDT 130 . A first portion 311 of the pad metal layer 310 is disposed under the first input and output terminal 131 of the IDT 130 ; and a second portion 312 of the pad metal layer 310 is disposed above the second input and output terminal 132 of the IDT 130 .

[0070] One or more release holes 145 are formed in the piezoelectric layer 140. The one or more release holes 145 are used to form the lower cavity 500a in the etching and releasing process.

[0071] The first TSV 441 and the second TSV 442 are formed in the top substrate 250 , the second dielectric layer 240 , and the piezoelectric layer 140 . The first TSV 441 exposes the first input and output terminals 131 of the IDT 130 , and the second TSV 442 exposes the output terminal 132 of the second input IDT 130 .

[0072] The redistribution metal layer 260 is disposed on the top substrate 250 . The first portion 261 of the redistribution metal layer 260 is electrically connected to the first input and output terminals 131 of the IDT 130 through the first TSV 441 , and the second portion 262 of the redistribution metal layer 260 is electrically connected to the second input and output terminals 132 of the IDT 130 through the second TSV 442 .

[0073] The passivation layer 290 is disposed on the top substrate 250 and fills the first and second TSVs 441 and 442. The passivation layer 290 is formed with a first window 291 exposing the first portion 261 of the redistribution metal layer 260 and a second window 292 exposing the second portion 262 of the redistribution metal layer 260.

[0074] An under bump metallization (UBM) layer 300 is disposed on the passivation layer 290. A first portion 301 of the UBM layer 300 is disposed over the first portion 261 of the redistribution metal layer 260 and is electrically connected to the first portion 261 of the redistribution metal layer 260 through the first window 291; a second portion 302 of the UBM layer 300 is disposed over the second portion 262 of the redistribution metal layer 260 and is electrically connected to the second portion 262 of the redistribution metal layer 260 through the second window 292.

[0075] The first solder bump 281 and the second solder bump 282 are disposed over the top substrate 250. The first solder bump 281 is disposed over the first portion 301 of the UBM layer 300 and is electrically connected to the first portion 261 of the redistribution metal layer 260 through the first portion 301 of the UBM layer 300. The second solder bump 282 is disposed over the second portion 302 of the UBM layer 300 and is electrically connected to the second portion 262 of the redistribution metal layer 260 through the second portion 302 of the UBM layer 300.

[0076] Figure 5D 2 is a cross-sectional view of a SAW filter 2001 provided according to an embodiment of the present disclosure. The difference between the SAW filter 2001 and the SAW filter 2000 is that the SAW filter 1001 includes a non-conductive layer 320 and a buffer layer 330 disposed between the first dielectric layer 180 and the bottom substrate 210. Specifically, the non-conductive layer 320 is disposed above the bottom substrate 210, and the buffer layer 330 is disposed on the non-conductive layer 320. The non-conductive layer 320 can be formed by polycrystalline silicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials. The buffer layer 330 can be formed by silicon nitride, silicon oxide, or a stacked combination of these materials.

[0077] In some optional embodiments, the SAW filter may include only one of the non-conductive layer 320 and the buffer layer 330. For example, the SAW filter may include the non-conductive layer 320 disposed between the first dielectric layer 180 and the bottom substrate 210. Alternatively, the SAW filter may include the buffer layer 330 disposed between the first dielectric layer 180 and the bottom substrate 210.

[0078] The structure and components of the SAW filter 2001 are the same as those of the SAW filter 2000 except for the non-conductive layer 320 and the buffer layer 330 , and thus a detailed description of the other components of the SAW filter 2001 will not be repeated.

[0079] Figure 6 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 5A Flow chart of the SAW filter process; Figures 7A-7T According to one embodiment of the present disclosure, Figure 6 A cross-sectional view of a structure formed in the process.

[0080] like Fig. 7A As shown, in step S1, a piezoelectric substrate 100 is obtained. The piezoelectric substrate may be a lithium niobate or lithium tantalate single crystal substrate.

[0081] like Figure 7B As shown, in step S2, ions are implanted into the piezoelectric substrate 100 at a predetermined implantation depth d, thereby forming an ion layer 101 at the depth d of the piezoelectric substrate 100. The ions may be helium ions or hydrogen ions. The implantation depth d may be determined based on the desired thickness of the piezoelectric layer 140. For example, the implantation depth d may be in a range from about 0.3 μm to about 10 μm. The first portion 100 a of the piezoelectric substrate 100 is disposed above the ion layer 101, and the second portion 100 b of the piezoelectric substrate 100 is disposed below the ion layer 101.

[0082] Reference Figure 7C In step S3, an IDT 130 is formed on the first portion 100a of the piezoelectric substrate 100. The IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133 disposed between the first input and output terminal 131 and the second input and output terminal 132.

[0083] Reference Fig.7D In step S4, a pad metal layer 310 is formed on the IDT 130. Then, the pad metal layer 310 is patterned to form a first portion 311 disposed over the first input and output terminal 131 of the IDT 130 and electrically connected to the IDT 130, and a second portion 312 disposed over the second input and output terminal 132 of the IDT 130 and electrically connected to the IDT 130.

[0084] refer to Fig. 7E In step S5, a sacrificial layer 170 is deposited on the first portion 100a of the piezoelectric substrate 100 and covers the IDT 130 and the pad metal layer 310. The sacrificial layer 170 may include Si, such as amorphous Si or polycrystalline silicon.

[0085] Reference Figure 7F In step S6, the sacrificial layer 170 is patterned by etching. The patterned sacrificial layer 170 covers the interdigital portion 133 of the IDT 130. The area of ​​the patterned sacrificial layer 170 is larger than the area of ​​the interdigital portion 133 of the IDT 130. The sacrificial layer 170 will be removed during the subsequent etching and release process, thereby forming the lower cavity 500a.

[0086] like Figure 7GAs shown, in step S7, the first dielectric layer 180 is deposited on the first portion 100a of the piezoelectric substrate 100 and covers the sacrificial layer 170, the IDT 130 and the pad metal layer 310. Then, the first dielectric layer 180 is surface planarized and polished by using a chemical mechanical polishing (CMP) process. The planarized first dielectric layer 180 still covers the sacrificial layer 170.

[0087] refer to Figure 7H In step S8, the base substrate 210 is bonded to the first dielectric layer 180. The base substrate 210 may include Si, SiO2, polysilicon, silicon carbide, sapphire (Al2O3), or a stacked combination of two or more of these materials.

[0088] Reference Fig.7I In step S9, Figure 7H The structure shown is turned over and the structure is thermally annealed. The annealing temperature may range from about 400° C. to about 650° C. After the thermal annealing, the ion layer 101 in the piezoelectric substrate 100 is destroyed. The second portion 100 b of the piezoelectric substrate 100 below the ion layer 101 is removed, while the first portion 100 a of the piezoelectric substrate 100 above the ion layer 101 is retained. The first portion 100 a of the piezoelectric substrate 100 constitutes the piezoelectric layer 140 in the SAW filter 1000. The piezoelectric layer 140 has a bottom surface 140 a forming the IDT 13, and the top surface 140 b is exposed. CMP polishing may be performed on the exposed top surface 140 b of the piezoelectric layer 140 to obtain a smooth surface and achieve the desired thickness of the piezoelectric layer 140 in the SAW filter 1000. In some embodiments, ion beam etching (IBE) or ion beam milling may be performed on the piezoelectric layer 140 to obtain a more uniform thickness.

[0089] Reference Figure 7J In step S10, a back electrode 150 is formed on the piezoelectric layer 140. The back electrode 150 may include any suitable conductive material, such as various metal materials or stacks of several conductive metal materials having conductive properties, such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), etc. The back electrode 150 is vertically aligned with the interdigital portion 133 of the IDT 130.

[0090] refer to Figure 7KIn step S11, a second dielectric layer 240 is deposited on the piezoelectric layer 140, covering the back electrode 150. The second dielectric layer 240 can be formed of silicon oxide, silicon nitride, or a stacked combination of these materials. The second dielectric layer 240 is deposited by using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. A CMP planarization process is performed on the second dielectric layer 240 so that the top surface of the second dielectric layer 240 is parallel to the top surface 140b of the piezoelectric layer 140.

[0091] Reference Figure 7L In step S12, the second dielectric layer 240 is patterned by etching. After the patterning process, a portion of the second dielectric layer 240 is removed to expose the entire or a portion of the back electrode 150 and a portion of the piezoelectric layer 140. The area of ​​the removed portion of the second dielectric layer 240 is larger than the area of ​​the interdigital portion 133 of the IDT 130.

[0092] like Figure 7M As shown, in step S13 , the portion of the piezoelectric layer 140 exposed by the second dielectric layer 240 is etched to form one or more release holes 145 passing through the piezoelectric layer 140 . Each release hole 145 exposes a portion of the sacrificial layer 170 .

[0093] refer to Figure 7N In step S14, after the sacrificial layer 170 is etched and released, a lower cavity 500a is formed below the interdigital portion 133 of the IDT 130. The sacrificial layer 170 can be etched by a dry etching process using XeF2 plasma. The etchant and etching products of the etching process can be released through one or more release holes 145.

[0094] Reference Fig.7O In step S15, the top substrate 250 is bonded to the second dielectric layer 240. The top substrate 250, the second dielectric layer 240 and the piezoelectric layer 140 together surround the upper cavity 500b. The top substrate 250 may include Si, SiO2, polysilicon, silicon carbide, sapphire (Al2O3), or a stacked combination of two or more of these materials.

[0095] Reference Figure 7P In step S16, the top substrate 250 is thinned to a predetermined thickness.

[0096] Reference Figure 7Q In step S17, a first TSV 441 and a second TSV 442 are formed in the top substrate 250, the second dielectric layer 240, and the piezoelectric layer 140. The first TSV 441 exposes the first input and output terminals 131 of the IDT 130, and the second TSV 442 exposes the second input and output terminals 132 of the IDT 130.

[0097] refer to Figure 7R In step S18, a redistribution metal layer 260 is formed on the top substrate 250 and within the first TSV 441 and the second TSV 442. The redistribution metal layer 260 is patterned to form a first portion 261 electrically connected to the first input and output terminal 131 of the IDT 130 through the first TSV 441, and a second portion 262 electrically connected to the second input and output terminal 132 of the IDT 130 through the second TSV 442.

[0098] Reference Figure 7S In step S19, a passivation layer 290 is formed on the top substrate 250 and covers the redistribution metal layer 260. Then, the passivation layer 290 is etched to form a first window 291 exposing a portion of the first portion 261 of the redistribution metal layer 260, and a second window 292 exposing a portion of the second portion 262 of the redistribution metal layer 260. The passivation layer 290 may include an organic material, such as polyimide. The first window 291 is not vertically aligned with the first TSV 441, and the second window 292 is not vertically aligned with the second TSV 442.

[0099] Reference Figure 7T In step S20, the UBM layer 300 is formed on the passivation layer 290. The UBM layer 300 is patterned to form a first portion 301 connected to an exposed portion of the first portion 261 of the redistribution metal layer 260 through a first window 291 of the passivation layer 290, and a second portion 302 connected to an exposed portion of the second portion 262 of the redistribution metal layer 260 through a second window 292 of the passivation layer 290. Thereafter, a first solder bump 281 is formed on the first portion 301 of the UBM layer 300 and connected to the first portion 301 of the UBM layer 300, and a second solder bump 282 is formed on the second portion 302 of the UBM layer 300 and connected to the second portion 302 of the UBM layer 300. Therefore, the first solder bump 281 is electrically connected to the first input and output terminals 131 of the IDT 130, and the second solder bump 282 is electrically connected to the second input and output terminals 132 of the IDT. Thus, as shown in FIG. Figure 5A The SAW filter 2000 shown is manufactured.

[0100] Figure 8 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 5DFlowchart of the process of the SAW filter 2001. The manufacturing process of the SAW filter 2001 is the same as the manufacturing process of the SAW filter 2000, except that, in step S8, a base substrate 210 is obtained, at least one of the non-conductive layer 320 or the buffer layer 330 is deposited on the base substrate 210, and then the base substrate 210 on which at least one of the non-conductive layer 320 or the buffer layer 330 is deposited is bonded to the first dielectric layer 180. When both the non-conductive layer 320 and the buffer layer 330 are deposited on the base substrate 210, the non-conductive layer 320 is first deposited on the base substrate 210, and then the buffer layer 330 is deposited on the non-conductive layer 320.

[0101] The manufacturing process of the SAW filter 2001 is the same as the manufacturing process of the SAW filter 2000 except step S8, and thus a detailed description of the other steps of manufacturing the SAW filter 2001 will not be repeated.

[0102] In the SAW filters 1000, 1001, 2000 and 2001 provided according to the embodiments of the present disclosure, the IDT 130 is disposed on one side of the piezoelectric layer 140, and the back electrode 150 is disposed on the opposite side of the piezoelectric layer 140. As a result, a higher effective electromechanical coupling coefficient of the resonant device, also referred to as Keff2, can be obtained.

[0103] In addition, the SAW filters 1000 , 1001 , 2000 , and 2001 provided according to the embodiments of the present disclosure are provided with a wafer level package (WLP) structure.

[0104] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A surface acoustic wave (SAW) filter, characterized in that: include: bottom substrate; a piezoelectric layer disposed above the bottom substrate and having a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; A lower cavity, disposed below the piezoelectric layer; An interdigital transducer IDT is arranged on the top surface of the piezoelectric layer; a back electrode disposed on the bottom surface of the piezoelectric layer and exposed in the lower cavity, wherein a portion of the top surface of the back electrode is exposed through a back electrode contact hole formed in the piezoelectric layer; a first dielectric layer disposed between the piezoelectric layer and the bottom substrate and surrounding the lower cavity; an upper cavity, located above the piezoelectric layer, exposing the interdigital portion of the IDT and a portion of the piezoelectric layer, wherein one or more release holes are formed in the piezoelectric layer, and the upper cavity and the lower cavity are connected through the release holes; a top substrate covering the upper cavity; a second dielectric layer disposed between the piezoelectric layer and the top substrate and surrounding the upper cavity; A pad metal layer is disposed above the IDT, wherein a first portion of the pad metal layer is disposed above a first input and output terminal of the IDT, and a second portion of the pad metal layer is disposed above a second input and output terminal of the IDT; A first through silicon via TSV and a second through silicon via TSV are formed in the top substrate and the second dielectric layer, the first TSV exposing a first portion of the pad metal layer, and the second TSV exposing a second portion of the pad metal layer; a redistribution metal layer, disposed on the top substrate, wherein a first portion of the redistribution metal layer is electrically connected to a first portion of the pad metal layer through the first TSV, and a second portion of the redistribution metal layer is electrically connected to a second portion of the pad metal layer through the second TSV; a non-conductive layer disposed between the first dielectric layer and the base substrate; and A buffer layer is disposed between the first dielectric layer and the non-conductive layer.

2. The SAW filter according to claim 1, characterized in that: Also includes: A first solder bump and a second solder bump are disposed above the top substrate, the first solder bump being electrically connected to a first portion of the redistribution metal layer, and the second solder bump being electrically connected to a second portion of the redistribution metal layer.

3. The SAW filter according to claim 1, characterized in that: The top substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials; and The top substrate is bonded to the second dielectric layer.

4. The SAW filter according to claim 1, characterized in that: The bottom substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials; and The base substrate is bonded to the first dielectric layer.

5. The SAW filter according to claim 4, characterized in that: Also includes: The non-conductive layer is formed of polysilicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials; and The buffer layer is formed of silicon nitride, silicon oxide, or a stacked combination of these materials.

6. A surface acoustic wave (SAW) filter, characterized in that: include: bottom substrate; a piezoelectric layer disposed above the bottom substrate and having a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; A lower cavity, disposed below the piezoelectric layer; A back electrode disposed on the top surface of the piezoelectric layer, a portion of the top surface of the back electrode being exposed through a back electrode contact hole formed in the piezoelectric layer; an interdigital transducer IDT, disposed on the bottom surface of the piezoelectric layer and having an interdigital portion exposed in the lower cavity; a first dielectric layer disposed between the piezoelectric layer and the bottom substrate and surrounding the lower cavity; an upper cavity, located above the piezoelectric layer, exposing a portion of the back electrode and the piezoelectric layer, wherein one or more release holes are formed in the piezoelectric layer, and the upper cavity and the lower cavity are connected through the release holes; a top substrate covering the upper cavity; a second dielectric layer disposed between the piezoelectric layer and the top substrate and surrounding the upper cavity; A first through silicon via TSV and a second through silicon via TSV are formed in the top substrate, the second dielectric layer and the piezoelectric layer, the first TSV exposing the first input and output terminals of the IDT, and the second TSV exposing the output terminal of the second input IDT; and A redistribution metal layer is disposed on the top substrate, a first portion of the redistribution metal layer is electrically connected to the first input and output terminals of the IDT through the first TSV, and a second portion of the redistribution metal layer is electrically connected to the second input and output terminals of the IDT through the second TSV; a non-conductive layer disposed between the first dielectric layer and the base substrate; and A buffer layer is disposed between the first dielectric layer and the non-conductive layer.

7. The SAW filter according to claim 6, characterized in that: Also includes: A first solder bump and a second solder bump are disposed above the top substrate, the first solder bump being electrically connected to a first portion of the redistribution metal layer, and the second solder bump being electrically connected to a second portion of the redistribution metal layer.

8. The SAW filter according to claim 6, characterized in that: The top substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials; and The top substrate is bonded to the second dielectric layer.

9. The SAW filter according to claim 6, characterized in that: The bottom substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials; and The base substrate is bonded to the first dielectric layer.

10. The SAW filter according to claim 7, characterized in that: Also includes: The non-conductive layer is formed of polysilicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials; and The buffer layer is formed of silicon nitride, silicon oxide, or a stacked combination of these materials.

11. A method for manufacturing a surface acoustic wave (SAW) filter according to any one of claims 1 to 5, characterized in that: include: obtaining a piezoelectric substrate; forming a back electrode on a first portion of the piezoelectric substrate; forming a sacrificial layer covering the back electrode on the first portion of the piezoelectric substrate; forming a first dielectric layer covering the sacrificial layer on a first portion of the piezoelectric substrate; bonding a base substrate to the first dielectric layer; removing a second portion of the piezoelectric substrate to expose a first portion of the piezoelectric substrate, the first portion of the piezoelectric substrate constituting a piezoelectric layer; forming one or more release holes through the piezoelectric layer; forming an interdigital transducer (IDT) on the piezoelectric layer; etching and releasing the sacrificial layer through one or more release holes to form a lower cavity exposing the back electrode; forming a first pad metal layer at a first input and output end of the IDT, and forming a second pad metal layer at a second input and output end of the IDT; forming a second dielectric layer on the piezoelectric layer; wherein the second dielectric layer covers the first input and output terminals, the second input and output terminals, the first pad metal layer and the second pad metal layer, and exposes the interdigital portion of the IDT; bonding a top substrate to the second dielectric layer; wherein the top substrate, the second dielectric layer and the piezoelectric layer together surround an upper cavity; thinning the top substrate to a predetermined thickness; Forming a first through silicon via TSV and a second TSV in the top substrate and the second dielectric layer; wherein the first TSV exposes the first pad metal layer, and the second TSV exposes the second pad metal layer; forming a redistribution metal layer on the top substrate; wherein a first portion of the redistribution metal layer is electrically connected to the first input and output terminals via a first TSV, and a second portion of the redistribution metal layer is electrically connected to the second input and output terminals via a second TSV; forming a passivation layer on the top substrate and the redistribution metal layer; wherein the passivation layer exposes a portion of the first portion of the redistribution metal layer and a portion of the second portion of the redistribution metal layer; Before bonding the base substrate to the first dielectric layer: forming a non-conductive layer on the base substrate; and forming a buffer layer on the non-conductive layer.

12. The method according to claim 11, characterized in that Also includes: Before forming the back electrode on the first portion of the piezoelectric substrate, ions are implanted into the piezoelectric substrate to form an ion layer at a predetermined depth of the piezoelectric substrate; wherein the first portion of the piezoelectric layer is disposed above the ion layer, and the second portion of the piezoelectric layer is disposed below the ion layer; and After bonding the base substrate to the first dielectric layer, thermal annealing is performed to destroy the ion layer in the piezoelectric substrate, thereby removing a second portion of the piezoelectric substrate.

13. The method according to claim 11, characterized in that Also includes: A first solder bump and a second solder bump are formed on the top substrate; wherein the first solder bump is electrically connected to the exposed portion of the first portion of the redistribution metal layer, and the second solder bump is electrically connected to the exposed portion of the second portion of the redistribution metal layer.

14. The method according to claim 11, characterized in that The piezoelectric substrate is a lithium niobate or lithium tantalate single crystal substrate.

15. The method according to claim 11, characterized in that The top substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials.

16. The method according to claim 11, characterized in that The base substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials.

17. A method for manufacturing a surface acoustic wave (SAW) filter according to any one of claims 6 to 10, characterized in that: include: obtaining a piezoelectric substrate; forming an interdigital transducer (IDT) on a first portion of the piezoelectric substrate; forming a sacrificial layer covering the interdigital portions of the IDT on the first portion of the piezoelectric substrate; forming a first dielectric layer covering the sacrificial layer and the IDT on a first portion of the piezoelectric substrate; bonding a base substrate to the first dielectric layer; removing a second portion of the piezoelectric substrate to expose a first portion of the piezoelectric substrate, the first portion of the piezoelectric substrate constituting a piezoelectric layer; forming a back electrode on the piezoelectric layer; forming a release hole through the piezoelectric layer; etching and releasing the sacrificial layer to form a lower cavity below the interdigital portion of the IDT; forming a first pad metal layer at a first input and output end of the IDT, and forming a second pad metal layer at a second input and output end of the IDT; forming a second dielectric layer on the piezoelectric layer to expose the back electrode; bonding a top substrate to the second dielectric layer; wherein the top substrate, the second dielectric layer and the piezoelectric layer together surround an upper cavity; thinning the top substrate to a predetermined thickness; forming a first through silicon via TSV and a second TSV in the top substrate, the second dielectric layer and the piezoelectric layer; wherein the first TSV exposes the first pad metal layer and the second TSV exposes the second pad metal layer; forming a redistribution metal layer on the top substrate; wherein a first portion of the redistribution metal is electrically connected to the first input and output terminals via the first TSV, and a second portion of the redistribution metal layer is electrically connected to the second input and output terminals via a second TSV; forming a passivation layer on the top substrate and the redistribution metal layer; wherein the passivation layer exposes a portion of the first portion of the redistribution metal layer and a portion of the second portion of the redistribution metal layer; Before bonding the base substrate to the first dielectric layer: forming a non-conductive layer on the base substrate; and forming a buffer layer on the non-conductive layer.

18. The method according to claim 17, characterized in that Also includes: Before forming the IDT on the first portion of the piezoelectric layer, ions are implanted into the piezoelectric substrate to form an ion layer at a predetermined depth of the piezoelectric substrate; wherein the first portion of the piezoelectric layer is disposed above the ion layer, and the second portion of the piezoelectric layer is disposed below the ion layer; and After bonding the base substrate to the first dielectric layer, thermal annealing is performed to destroy the ion layer in the piezoelectric substrate, thereby removing a second portion of the piezoelectric substrate.

19. The method according to claim 17, characterized in that Also includes: A first solder bump and a second solder bump are formed on the top substrate; wherein the first solder bump is electrically connected to the exposed portion of the first portion of the redistribution metal layer, and the second solder bump is electrically connected to the exposed portion of the second portion of the redistribution metal layer.

20. The method according to claim 17, characterized in that The piezoelectric substrate is a lithium niobate or lithium tantalate single crystal substrate.

21. The method according to claim 17, characterized in that The top substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials.

22. The method according to claim 17, characterized in that The base substrate is formed of Si, SiO2, polysilicon, silicon carbide, sapphire Al2O3, or a stacked combination of two or more of these materials.

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