Transmitter and signal transmission method thereof

Abstract

The transmitter includes a sequencer, a main driver, and an auxiliary driver. The sequencer sequentially outputs a first signal and a second signal as two consecutive data in a first output signal based on a clock signal, and detects whether the first and second signals are identical to generate a control signal. The main driver generates a second output signal based on the first output signal. The auxiliary driver selectively switches according to the control signal. The main driver and the auxiliary driver are powered by the same power supply voltage.

Description

Technical Field

[0001] This case relates to a transmitter, and more particularly to a transmitter with a stable voltage mechanism and a signal transmission method thereof. Background Art

[0002] A transmitter can be used to transmit data to another device. Depending on the data type being transmitted, the transmitter may consume different currents at different times. For example, if the data type being transmitted is a series of different data values, the internal circuitry in the transmitter will continuously switch, generating a large dynamic current. Alternatively, if the data type being transmitted is a series of identical data values, the internal circuitry in the transmitter will not switch, resulting in a more stable current. In these situations, the power supply for the transmitter must have good regulation capabilities and / or a large filter capacitor to meet the requirements of high-speed data transmission. However, as data rates increase, the bandwidth and regulation capabilities of the power supply are no longer sufficient to support current high-speed data rates (e.g., gigahertz). On the other hand, increasing the filter capacitor's capacitance would significantly increase the chip's overall area and cost, and would also reduce the power supply's bandwidth. Summary of the Invention

[0003] The embodiments of the present application provide a transmitter with a stable voltage mechanism and a signal transmission method thereof to improve the deficiencies of the prior art.

[0004] An embodiment of the present application provides a transmitter comprising a sequencer, a main driver, and an auxiliary driver. The sequencer sequentially outputs a first signal and a second signal as two consecutive data in a first output signal according to a clock signal, and detects whether the first signal and the second signal are identical to generate a control signal. The main driver generates a second output signal according to the first output signal. The auxiliary driver selectively switches according to the control signal, wherein the main driver and the auxiliary driver are powered by the same power supply voltage.

[0005] The present application also provides a signal transmission method comprising the following operations: sequentially outputting a first signal and a second signal as two consecutive data in a first output signal according to a frequency signal, and detecting whether the first signal and the second signal are identical to generate a control signal; generating a second output signal according to the first output signal by a main driver; and selectively switching an auxiliary driver according to the control signal, wherein the main driver and the auxiliary driver are powered by the same power supply voltage.

[0006] The features, implementation and effects of the present invention are described in detail below with reference to the drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] [Figure 1 ] is a schematic diagram of a transmitter according to some embodiments of the present invention;

[0008] [ Figure 2 ] is drawn according to some embodiments of the present invention Figure 1 Schematic diagram of the sequencer, main driver and auxiliary driver;

[0009] [ Figure 3 ] is drawn according to some embodiments of the present invention Figure 1 and / or Figure 2 A schematic diagram of the dynamic waveform of the current consumed by some signals and / or some circuits in the circuit; and

[0010] [ Figure 4 ] is a flowchart of a signal transmission method according to some embodiments of the present case. DETAILED DESCRIPTION

[0011] All terms used herein have their ordinary meanings. The definitions of the above terms in commonly used dictionaries, including any examples of their use in the context of this application, are intended to be illustrative only and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments described herein.

[0012] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action of two or more components. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active or passive component connected in a specific manner to process signals.

[0013] Figure 1 This figure is a schematic diagram of a transmitter 100 according to some embodiments of the present invention. In some embodiments, transmitter 100 may be a wired transmission transmitter. Transmitter 100 includes a sequencer 110, a main driver 120, an auxiliary driver 125, a post driver 130, a power supply 140, and a power supply 150. Power supply 140 operates as a core power supply, providing a power supply voltage VDD3 to sequencer 110 and a power supply voltage VDD1 to main driver 120 and auxiliary driver 125 to power these circuits. In some embodiments, power supply voltage VDD3 and power supply voltage VDD1 may be the same voltage, but the present invention is not limited thereto. Power supply 150 operates as a power supply for an input / output interface, providing a power supply voltage VDD2 to post driver 130 to power post driver 130.

[0014] Sequencer 110 can sequentially output signals S1 and S2 as two consecutive data points in output signal SO1 according to a clock signal CLK. In other words, sequencer 110 can convert two parallel signals (i.e., signals S1 and S2) into a single serial output (i.e., output signal SO1). Sequencer 110 can also detect whether signals S1 and S2 are identical to generate control signal SC.

[0015] In some embodiments, the main driver 120 and the auxiliary driver 125 may be pre-drivers having the same structure. In some embodiments, the main driver 120 operates as a main transmission path, which can be used to transmit the output signal SO1, and the auxiliary driver 125 operates as an auxiliary transmission path, which can be used to stabilize the power supply voltage VDD1. Specifically, the main driver 120 can be coupled to the sequencer 110 to receive the output signal SO1 and generate the output signal SO2 based on the output signal SO1. The auxiliary driver 125 can be coupled to the sequencer 110 to receive the control signal SC and selectively switch based on the control signal SC. For example, if the sequencer 110 determines that the signal S1 is the same as the signal S2, the auxiliary driver 125 switches based on the control signal SC. Alternatively, if the sequencer 110 determines that the signal S1 is different from the signal S2, the auxiliary driver 125 does not switch based on the control signal SC. By using the above configuration, it is ensured that both the main driver 120 and the auxiliary driver 125 draw similar currents from the power supply 140 during any period, so that the power supply voltage VDD1 can be more stable. Figure 2 and Figure 3 The post-driver 130 is coupled to the main driver 120 to receive the output signal SO2. The post-driver 130 can generate an output signal SO3 according to the output signal SO2 and transmit the output signal SO3 to another device (not shown) via the cable 105.

[0016] Figure 2 According to some embodiments of the present invention Figure 1 FIG2 is a circuit diagram of the sequencer 110, main driver 120, and auxiliary driver 125 in FIG2. Sequencer 110 includes a data capture circuit 211, a buffer circuit 212, a multiplexer 213, and a detection circuit 214. Data capture circuit 211 outputs signals S1 and S2 as data D1 and data D2, respectively, based on a clock signal CLK. In some embodiments, data capture circuit 211 may include a D-type flip-flop 211A and a D-type flip-flop 211B. D-type flip-flop 211A outputs signal S1 as data D1 based on a clock signal CLK. D-type flip-flop 211B outputs signal S2 as data D2 based on a clock signal CLK.

[0017] The temporary storage circuit 212 temporarily stores data D2 as data D3 according to the clock signal CLK. For example, the temporary storage circuit 212 may be, but is not limited to, a D-type latch, which can temporarily store data D2 as data D3 according to the clock signal CLK. The detection circuit 214 can compare data D1 and data D2 to determine whether signal S1 is the same as signal S2 to generate the control signal SC. As described above, signals S1 and S2 are output as two consecutive data in the output signal SO1. For example, signal S1 can be output as even-numbered data in the output signal SO1, and signal S2 can be output as odd-numbered data in the output signal SO1. To determine whether signals S1 and S2 are the same, the temporary storage circuit 212 can delay signal S2 to align it with signal S1 in time (i.e., data D1 can be aligned with data D3). In this way, the detection circuit 214 can compare the data D1 and the data D3 to confirm whether two consecutive data in the output signal SO1 are the same.

[0018] In some embodiments, the detection circuit 214 may include a comparator 214A and a control signal generator 214B. The comparator 214A may compare data D1 and data D3 to generate a signal S3. In some embodiments, the comparator 214A may be, but is not limited to, an XNOR gate, which may be used to perform the above operation to generate the signal S3. For example, if the data D1 is the same as the data D3, the comparator 214A may output a signal S3 having a first logic value (e.g., a logic value of 1). Alternatively, if the data D1 is different from the data D3, the comparator 214A may output a signal S3 having a second logic value (e.g., a logic value of 0). The control signal generator 214B may generate a control signal SC based on the signal S3 and the clock signal CLK. In some embodiments, the control signal generator 214B may be, but is not limited to, a NAND gate, which may perform the above operation to generate the control signal SC. For example, in response to a signal S3 having a first logic value, the control signal generator 214B may output the clock signal CLK as the control signal SC, causing the auxiliary driver 125 to switch in accordance with the clock signal CLK. Alternatively, in response to a signal S3 having a second logic value, the control signal generator 214B may output a control signal SC having a fixed logic value (e.g., logic value 1), causing the auxiliary driver 125 to not switch.

[0019] Multiplexer 213 can sequentially output data D1 and data D3 as two consecutive data in output signal SO1 based on clock signal CLK. For example, when clock signal CLK has a first level, multiplexer 213 outputs data D1 as even-numbered data in output signal SO1. Alternatively, when clock signal CLK has a second level different from the first level, multiplexer 213 outputs data D3 as odd-numbered data in output signal SO1. Equivalently, data capture circuit 211 and multiplexer 213 can convert multiple parallel signals S1 and S2 into consecutive data in output signal SO1 (i.e., serialize them).

[0020] In this example, each of the main driver 120 and the auxiliary driver 125 can be an inverter circuit, which can be powered by the power supply voltage VDD1. For example, each of the main driver 120 and the auxiliary driver 125 can be implemented by P-type transistors and N-type transistors with the same size setting. As described above, the main driver 120 can generate an output signal SO2 according to the output signal SO1 and transmit the output signal SO2 to Figure 1 The post-driver 130 in FIG. In some embodiments, the output of the auxiliary driver 125 is coupled to a capacitor C and does not transmit signals to other circuits. When data D1 differs from data D3 (i.e., the captured signal S1 differs from the captured signal S2), the auxiliary driver 125 may not switch in response to the control signal SC, while the main driver 120 will continuously output different data (because data D1 and data D3 are two consecutive data in the output signal SO1) and switch. In other words, under this condition, the main driver 120 will switch and consume dynamic current.

[0021] On the other hand, when data D1 is the same as data D3 (i.e., the captured signal S1 is the same as the captured signal S2), the auxiliary driver 125 can switch in response to the control signal SC, while the main driver 120 will continue to output the same data without switching. In other words, under this condition, the auxiliary driver 125 will switch and consume dynamic current. Accordingly, in any of the above situations, a corresponding one of the main driver 120 and the auxiliary driver 125 will switch, causing the main driver 120 and the auxiliary driver 125 to consume approximately the same amount of dynamic current as a whole. In this way, the Figure 1 In some embodiments, to ensure that the main driver 120 and the auxiliary driver 125 can generate substantially the same dynamic current, the capacitance of the capacitor C can be adjusted according to the current fluctuation of the power supply 140 providing the power supply voltage VDD1. Figure 1 The input capacitance of the post driver 130 (e.g. Figure 1For example, the capacitance of capacitor C can be set to be the same as the capacitance of input capacitor Cin of post-driver 130. In this way, the main driver 120 and auxiliary driver 125 can generate more similar dynamic currents during switching.

[0022] Figure 3 According to some embodiments of the present invention Figure 1 and / or Figure 2 Schematic diagram of the waveform of the dynamic current consumed by some signals and / or circuits in the circuit. Figure 3 As shown, the output signal SO1 includes a plurality of data, which may be logic value 0, logic value 1, logic value 0, logic value 1, logic value 0, and logic value 1 in period T1 and a plurality of logic values ​​1 in period T2. The plurality of data may be data values ​​of the signal S1 and the signal S2 at different times.

[0023] During the period T1, since the two consecutive data of the output signal SO1 are different from each other (i.e., a logic value 0 and a logic value 1), it means that the main driver 120 switches continuously and generates a plurality of different data. Thus, the main driver 120 consumes dynamic current (e.g., Figure 3 On the other hand, under this condition, the auxiliary driver 125 does not switch in response to the control signal SC and does not generate dynamic current consumption (such as Figure 3 Waveform 302 shown).

[0024] During the period T2, since the two consecutive data of the output signal SO1 are the same (i.e., both are logic 1), it means that the main driver 120 has not switched to output the same data. Therefore, the main driver 120 will not generate dynamic current during the period T2. On the other hand, under this condition, the auxiliary driver 125 switches in response to the control signal SC and generates dynamic current (such as Figure 3 As shown in the waveform 302). Figure 3 As shown, since there is a corresponding driver generating substantially equal dynamic currents during the period T1 and the period T2, the fluctuation of the power supply voltage VDD1 during the period T1 and the period T2 can be made more stable (e.g. Figure 3 Waveform 303 shown).

[0025] In contrast, if the auxiliary driver 125 is not provided to generate the same amount of dynamic current during the period T2, the power supply voltage VDD1 (eg Figure 3During period T1, the voltage level of the power supply voltage VDD1 (shown as a dotted line in the figure) gradually decreases due to dynamic current consumption. During period T2, since the main driver 120 is not switching, the power supply 140 adjusts the power supply voltage VDD1, gradually restoring the power supply voltage VDD1. Comparing waveforms 303 and 304, it can be seen that without the auxiliary driver 125, the power supply voltage VDD1 experiences significant fluctuations due to high-speed data transmission. In other words, the provision of the auxiliary driver 125 effectively increases the stability of the power supply voltage VDD1, making it suitable for high-speed data transmission.

[0026] Figure 4 A flow chart of a signal transmission method 400 according to some embodiments of the present invention is provided. In operation S410, a first signal and a second signal are sequentially output as two consecutive data in a first output signal according to a clock signal, and a detection is made to determine whether the first signal and the second signal are identical to generate a control signal. In operation S420, a main driver generates a second output signal according to the first output signal. In operation S430, an auxiliary driver is selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same power supply voltage.

[0027] The various operations of the signal transmission method 400 described above can be referred to in the description of the aforementioned embodiments, and thus will not be repeated here. The various operations of the signal transmission method 400 described above are merely examples and are not intended to limit their execution to the order shown in this example. The various operations of the signal transmission method 400 may be appropriately added, replaced, omitted, or executed in a different order (e.g., simultaneously or partially simultaneously) without departing from the operational manner and scope of the various embodiments of the present invention.

[0028] In summary, the transmitter and signal transmission method in some embodiments of the present invention utilize an auxiliary driver to improve power supply voltage stability. This eliminates the limitations of power supply regulation and eliminates the need for large filter capacitors, making them suitable for high-speed data transmission applications while reducing overall chip cost.

[0029] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application defined in this specification.

[0030]

Explanation of symbols

[0031] 0,1: logical value

[0032] 100: Transmitter

[0033] 105: Cable

[0034] 110: Serializer

[0035] 120: Main drive

[0036] 125: Auxiliary drive

[0037] 130: Rear drive

[0038] 140,150: Power supply

[0039] 211: Data acquisition circuit

[0040] 211A, 211B: D-type flip-flop

[0041] 212: Temporary storage circuit

[0042] 213: Multitasking

[0043] 214: Detection circuit

[0044] 214A: Comparator

[0045] 214B: Control signal generator

[0046] 301~304: Waveform

[0047] 400: Signal transmission method

[0048] C: Capacitor

[0049] CLK: clock signal

[0050] Cin: input capacitance

[0051] D1~D3: Data

[0052] S1~S3:Signal

[0053] S410, S420, S430: Operation

[0054] SC: Control signal

[0055] SO1, SO2, SO3: output signal

[0056] T1, T2: period

[0057] VDD1, VDD2, VDD3: power supply voltage

Claims

1. A transmitter, characterized in that: The transmitter comprises: a sequencer that sequentially outputs a first signal and a second signal as two consecutive data in a first output signal according to a clock signal, and detects whether the first signal and the second signal are identical to generate a control signal; a main driver, generating a second output signal according to the first output signal; and an auxiliary driver selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same power supply voltage; The sequencer comprises: a data acquisition circuit, outputting the first signal and the second signal as first data and second data respectively according to the clock signal; a temporary storage circuit temporarily storing the second data as third data according to the clock signal; a multiplexer that sequentially outputs the first data and the third data as the two consecutive data in the first output signal according to the clock signal; and A detection circuit compares the second data with the third data to generate the control signal.

2. The transmitter according to claim 1, wherein When the first signal is the same as the second signal, the auxiliary driver switches according to the control signal, and when the first signal is different from the second signal, the auxiliary driver does not switch according to the control signal.

3. The transmitter according to claim 1, wherein The transmitter further comprises: a post driver, generating a third output signal according to the second output signal, An output terminal of the auxiliary driver is coupled to a capacitor, and the capacitance of the capacitor is set according to the capacitance of an input capacitor of the post driver.

4. The transmitter according to claim 1, wherein The data acquisition circuit includes: a first D-type flip-flop, outputting the first signal as the first data according to the clock signal; and A second D-type flip-flop outputs the second signal as the second data according to the clock signal.

5. The transmitter according to claim 1, wherein The temporary storage circuit includes: A D-type latch outputs the second data as the third data according to the clock signal.

6. The transmitter according to claim 1, wherein The detection circuit includes: a comparator that compares the first data with the third data to generate a third signal; and A control signal generator generates the control signal according to the third signal and the clock signal.

7. The transmitter according to claim 6, characterized in that The comparator is an XNOR gate.

8. The transmitter according to claim 6, wherein The control signal generator is a NAND gate.

9. A signal transmission method, characterized in that: The method comprises: Outputting a first signal and a second signal in sequence as two consecutive data in a first output signal according to a clock signal, and detecting whether the first signal and the second signal are identical to generate a control signal; generating a second output signal according to the first output signal by a main driver; and selectively switching an auxiliary driver according to the control signal, wherein the main driver and the auxiliary driver are powered by the same power supply voltage; The method of outputting a first signal and a second signal in sequence as two consecutive data in a first output signal according to a clock signal, and detecting whether the first signal and the second signal are identical to generate a control signal, includes: outputting the first signal and the second signal as a first data and a second data respectively according to the clock signal; temporarily storing the second data as third data according to the frequency signal; outputting the first data and the third data in sequence as the two consecutive data in the first output signal according to the clock signal; and The second data and the third data are compared to generate the control signal.

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