Memory Subsystem Calibration Using Alternative Results

Abstract

The present invention discloses a memory subsystem and a method for performing calibration therein. The memory subsystem includes a memory controller coupled to a memory via a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine a corresponding eye diagram corresponding to a signal path in the plurality of signal paths. For a subsequent calibration, an updated eye diagram is determined for a subset of the plurality of signal paths. During the subsequent calibration, the remaining signal paths in the plurality of signal paths (not included in the subset) are inactive. Based on information obtained during the initial calibration and information from a signal path in a subset-designated agent for the remaining signal paths in the plurality of signal paths, an updated eye diagram for the remaining signal paths in the plurality of signal paths is determined.

Description

Background Art Technical Field

[0001] The present disclosure relates to memory subsystems, and more particularly, to performing calibration in a memory subsystem.

[0002] Related technical description

[0003] An eye pattern or eye diagram is a graphical representation of the time and amplitude at which a digital signal can be sampled at its correct value. In various types of systems including data transmission, it is desirable to sample a signal (e.g., a data signal synchronized by a clock signal) near the center of the eye in terms of both time and sampling voltage. In terms of timing, this can provide the signal with both a sufficient amount of setup and hold time while also making the signal less susceptible to noise. In terms of voltage, this can enable a more accurate determination of a logic value (e.g., a logic 1 or a logic 0) based on a threshold voltage used to distinguish one logic value from another.

[0004] In the memory subsystem, calibration may be performed to determine the points within the eye diagram at which the signal is sampled. Calibration is performed to determine an eye diagram that enables accurate sampling of the signal, and therefore includes calibration based on both timing (sometimes referred to as horizontal calibration) and sampling threshold voltage (sometimes referred to as vertical calibration). Performing these calibrations typically includes adjusting a number of different parameters that govern the transfer of data between the memory controller and the memory. Such calibrations may be performed during system startup, and may also be performed periodically thereafter. Summary of the invention

[0005] The present invention discloses a memory subsystem and a method for performing calibration therein. In one embodiment, a memory controller is coupled to a memory via a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine a corresponding eye diagram corresponding to each of the signal paths. For subsequent calibration, an updated eye diagram is determined for a subset of the plurality of signal paths. During the subsequent calibration, the remaining signal paths in the plurality of signal paths (not included in the subset) are inactive. An updated eye diagram for the remaining signal paths in the plurality of signal paths is determined based on information obtained during the initial calibration.

[0006] In one embodiment, a plurality of signal paths are divided into a first subgroup and a second subgroup. During the initial calibration, at least the signal paths in the first subgroup are calibrated in the first scan, and at least one signal path in the second subgroup is calibrated in the second scan. When the initial calibration is completed, the result obtained from the calibration of the first subgroup is compared with the result obtained for the second subgroup. For a given signal path in the second subgroup, the signal path in the first subgroup is selected as a proxy. Based on the fact that its calibration result is the closest match relative to other signal paths in the first subgroup, the signal path in the first subgroup is selected as a proxy for the corresponding signal path in the second subgroup. The difference (e.g., voltage offset and timing offset) between the given signal path in the second subgroup and its selected proxy is also determined. In the subsequent calibration, only the signal paths in the first subgroup are activated and calibrated directly (e.g., active during calibration), wherein the eye diagrams of these signal paths are updated accordingly. The updated eye diagram for a given signal path in the second subgroup is determined by combining the calibration result (from the subsequent calibration) for its corresponding proxy in the first subgroup with the difference determined during the initial calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0008] Figure 1 is a block diagram illustrating one embodiment of a memory subsystem having a memory controller and memory.

[0009] Figure 2 is a block diagram further illustrating one embodiment of a memory controller.

[0010] Figure 3 is a block diagram illustrating one embodiment of a system having an integrated circuit and a memory.

[0011] Figure 4 is a flow chart illustrating one embodiment of a method for calibrating a signal path coupled between a memory controller and a memory.

[0012] Figure 5 is a flow chart of another embodiment of a method for calibrating a signal path coupled between a memory controller and a memory.

[0013] Figure 6 is a block diagram of an exemplary system.

[0014] Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments of the invention are shown in the drawings by way of example and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the scope of the claims to the specific forms disclosed. On the contrary, the application is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the disclosure of the application as defined by the appended claims.

[0015] This disclosure includes references to "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," or "an embodiment." The appearance of the phrases "in one embodiment," "in a specific embodiment," "in some embodiments," "in various embodiments," or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0016] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. "An integral distribution circuit configured to distribute integrals to multiple processor cores" is intended to cover, for example, an integrated circuit having circuits that perform that function during operation, even if the integrated circuit in question is not currently being used (e.g., power is not connected to it). Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0017] The term “configured to” is not intended to mean “configurable to.” For example, an unprogrammed FPGA would not be considered “configured to” perform a particular function, although it might be “configurable to” perform that function after being programmed.

[0018] The statement in the appended claims that a structure is "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. Thus, no claim in the present application as filed is intended to be interpreted as having means-plus-function elements. If the applicant wishes to invoke section 112(f) during the prosecution of the application, it will use the "means for [performing the function]" statement to phrase the claim elements.

[0019] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0020] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that other factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

[0021] As used herein, the terms "first," "second," and the like act as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified. For example, in a register file having eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, rather than, for example, just logical registers 0 and 1.

[0022] The statement "the memory controller is coupled to the memory via a set of signal paths" and including "activating each signal path in the set of signal paths" in the initial calibration means that there are at least two signal paths coupled between the memory controller and the memory, and the at least two signal paths are activated during the initial calibration. In some embodiments, there may be other signal paths coupled between the memory controller and the memory, which do not have to be activated during the initial calibration. In other embodiments, all signal paths coupled between the memory controller and the memory may be activated during the initial calibration. Therefore, the statement "activating each signal path in the set of signal paths" should not be interpreted as in all cases, all signal paths coupled between the memory controller and the memory are activated during the initial calibration. Instead, the statement simply provides the possibility that this may be the case in some instances and may not be the case in other instances.

[0023] When used in the claims, the term "or" is used as an inclusive or rather than an exclusive or. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z and any combination thereof.

[0024] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will recognize that aspects of the disclosed embodiments may be practiced without these specific details. In some cases, well-known circuits, structures, signals, computer program instructions, and techniques are not shown in detail to avoid obscuring the disclosed embodiments. DETAILED DESCRIPTION

[0025] The present disclosure relates to calibration of a signal path coupled between a memory controller and a memory. During operation of a memory subsystem, calibration is performed at various times to ensure that the logic value of a signal transmitted between a memory controller and a memory is correctly interpreted when received. Correct interpretation of the logic value can be achieved by providing a sufficient amount of setup and hold time and determining a voltage that distinguishes logic 0 from logic 1. Calibration for ensuring sufficient setup and hold time for a signal involves adjusting the amount of delay provided to a data strobe signal (e.g., a clock signal for transmitting and receiving a synchronization signal) and determining its corresponding logic value. Similarly, calibration for determining a distinguishing voltage involves interpreting the logic value of a signal at various voltage levels. The former calibration may be referred to as horizontal calibration, while the latter may be referred to as vertical calibration. In summary, horizontal calibration and vertical calibration may be used to determine what is commonly referred to as an eye diagram, which represents the timing and voltage value range at which the logic value of a signal can be correctly interpreted.

[0026] In some memory subsystems, there may be a limit to the number of signal paths that can be calibrated at any given time. However, the total number of signal paths to be calibrated may exceed the number that can be calibrated in a given scan or instance. Therefore, in such embodiments, two scans may be required to calibrate all signal paths. If the duration of each calibration scan is substantially the same, the second scan effectively doubles the calibration time amount, and therefore doubles the amount of time that the memory system is unavailable. In addition, in some memory subsystems, a specific signal path may be inactive for a large amount of time, wherein the corresponding circuit is powered off. Therefore, calibration of these signal paths may require powering on the circuit, and therefore invalidating at least some power savings.

[0027] The method for performing calibration in a memory subsystem disclosed herein is a method in which only signal paths in a subgroup are calibrated for at least some instances of calibration. An initial calibration is performed in which all signal paths in a particular plurality of signal paths are calibrated. The plurality of signal paths may be divided into a first subgroup and a second subgroup. The results of the initial calibration for the signal paths in the first subgroup are compared with the calibration results for the signal paths in the second subgroup. For a given signal path in the second subgroup, a proxy signal path is selected from the signal paths in the first subgroup. The selection is based on the result of the comparison. More specifically, the proxy signal path of the first subgroup is selected based on: having a calibration result that most closely matches the calibration result of its corresponding signal path in the second subgroup. The difference or offset between the two signal paths is also calculated.

[0028] For calibration after the initial calibration, only the signal paths in the first subgroup are directly calibrated, while those in the second subgroup can remain inactive. As used herein, the term "direct calibration" with respect to a signal path means that the signal path is active during calibration and data is collected based on the signal transmitted on the signal path. For each signal path in the second subgroup, the calibration results of its agent from the first signal path are combined together with the calculated offset. This effectively produces a calibration for each of the signal paths in the second subgroup, and thus determines an eye diagram for each of the signal paths without having to perform a scan calibration twice or activate an otherwise inactive signal path. Therefore, the time that the memory subsystem is unavailable due to calibration can be reduced, while additional power savings can be achieved. Various embodiments of the memory subsystem are now discussed in further detail.

[0029] Figure 1 1 is a block diagram showing one embodiment of a memory subsystem having a memory controller and memory in the memory subsystem. In the illustrated embodiment, the memory subsystem 11 includes a memory controller 12 and a memory 158. A plurality of signal paths (particularly signal paths 0 to 9) are coupled between the memory controller 12 and the memory 158.

[0030] The illustrated signal paths may be divided into a first subset 18 and a second subset 19. In this particular embodiment, signal paths 0 through 7 of the first subset 18 are provided for communicating data (for reading and writing) between the memory controller 12 and the memory 158. Signal paths 8 and 9 of the second subset 19 may be provided for various other functions, such as providing one or more error correction code (ECC) bits, signals for performing data bus inversion (e.g., inverting data values ​​on signal paths 0 through 7), etc.

[0031] In various embodiments, the memory controller 12 performs calibration of the signal paths to determine the eye diagram for each signal path. The calibration may include data transfer between the memory controller 12 and the memory 158, including both reads and writes. Figure 1 Although not explicitly shown in the figure, a data strobe signal is transmitted between the memory controller 12 and the memory 158. The data strobe signal is used to synchronize the reading and writing of data transmitted on each of the signal paths. Calibration includes determining the time when the signal transmitted on the signal path in the plurality of signal paths is sampled relative to the data strobe signal. Therefore, calibration includes providing various delays to the data strobe signal, reading the data, and comparing with the expected data. In addition, the voltage level used to distinguish between logic 1 and logic 0 can also be changed during calibration. Therefore, calibration includes determining the voltage at which the signal transmitted on the signal path in the plurality of signal paths is used to distinguish between logic 1 and logic 0. Based on the comparison results, an eye diagram can be determined for each of the signal paths in the signal path.

[0032] In the illustrated embodiment, the memory controller 12 performs an initial calibration that includes activating each signal path in a group of signal paths to determine a corresponding eye diagram for the signal paths in the entire group. Since the memory controller 12 can be limited to calibrating less than the entire group of signal paths during a single calibration scan, the initial calibration can include at least two scans. A calibration scan can be defined as a calibration performed on a selected group of signal paths. Therefore, during the initial calibration, the memory controller 12 in the illustrated embodiment performs a first calibration scan to determine a corresponding eye diagram for a signal path in a subset (e.g., a first subset), and then performs a second calibration scan to determine a corresponding eye diagram for at least one of the remaining signal paths in the signal path (e.g., a second subset). The information obtained during the initial calibration includes: for the remaining signal paths in the group of signal paths, relative to the corresponding selected signal paths in the first subset of the group of signal paths and timing offsets.

[0033] A single calibration scan may include all signal paths in the first subset 18, and in some embodiments, include signal paths in the second subset 19. For example, consider a situation where only 9 of the 10 signal paths can be calibrated during a given scan. Thus, signal paths 0 to 8 can be calibrated during the first scan, while signal path 9 can be calibrated during the second scan. Thus, in the illustrated embodiment, at least two scans are required to ensure that all signal paths are calibrated.

[0034] Because operating conditions (e.g., temperature) may change over time, the memory controller 12 may perform a subsequent calibration that includes activating a subset of the set of signal paths to determine updated corresponding eye diagrams for the signal paths in the subset. More specifically, in the illustrated embodiment, the signal paths in the first subset 18 may be calibrated. For the remaining signal paths in the set of signal paths, corresponding updated eye diagrams may be determined based on information obtained during the initial calibration. Thus, the subsequent calibration is performed without activating the remaining signal paths in the set of signal paths (e.g., the signal paths in the second subset 19).

[0035] Based on the information obtained during the initial calibration, for each signal path in the second subset 19, a proxy in the first subset 18 is determined. The proxy for a given signal path in the second subset 19 is the signal path in the first subset 18 that provides a basis for updating the eye diagram of the former. More specifically, in the illustrated embodiment, the memory controller 12 determines during the first calibration one of the signal paths in the first subset 18 that has an eye diagram that most closely matches the eye diagram of the selected one of the signal paths in the second subset 19. In addition, a voltage offset and a timing offset (based on the difference between the eye diagram of the one signal path in the first subset 18 and the eye diagram of the second subset) are also determined by the memory controller 12.

[0036] The selection of the proxy is performed by comparing the initial calibration results and calculating the offset value (e.g., difference). For example, after the initial calibration, the results obtained for signal path 9 (in the second subgroup 19) are compared with each of the signal paths 0 to 7 (in the first subgroup 18). One of the signal paths 0 to 7 is then selected as the proxy for signal path 9. The selection is based on which signal path in the first subgroup 18 has the closest calibration result to the calibration result of signal path 9 during the initial calibration. During the comparison, the offset is calculated. The offset represents the difference (if any) between the calibrated value of signal path 9 and the proxy selected from signal paths 0 to 7. During subsequent calibration, signal path 9, which is part of the second subgroup 19, is not calibrated directly. Instead, the subsequent calibration value for the selected proxy is combined with the offset to obtain an updated calibration value for signal path 9 (and therefore an updated eye diagram). The same process can be performed for signal path 8 (also of the second subgroup 19), and more generally, for any signal path in the second subgroup of a given implementation. In some examples, it is possible that two signal paths in the second subgroup may have the same agent within the first subgroup, although this is not always the case.

[0037] In some embodiments, calibration may be performed at multiple different clock frequencies because the memory subsystem 11 may experience performance state changes during operation due to, for example, workload demands, power demands, etc. Therefore, in such embodiments, the memory controller 12 selects a first signal path in the subset of signal paths as a basis for determining an eye diagram for a subsequent calibration performed at the first clock frequency, and further selects a second signal path in the subset of signal paths as a basis for determining an eye diagram for a subsequent calibration performed at the second clock frequency.

[0038] In one embodiment, the memory controller 12 performs an initial calibration during startup of the system in which the memory controller 12 and the memory 158 are implemented. The memory controller 12 also performs one or more instances of subsequent calibration during operation of the system. In some embodiments, these subsequent calibrations may be performed periodically. Since the initial calibration may be performed for a plurality of different clock frequencies, subsequent calibrations may also be performed when the clock frequency changes.

[0039] For both initial and subsequent calibrations, the memory controller 12 performs one or more writes of data to the memory 158, and also performs one or more reads of data from the memory 158. As described above, this also includes comparing the data written to and read from the memory 158 with expected values.

[0040] The boundaries of the eye diagram for a given signal path can be determined by the points where one or more bits transmitted on the signal path fail to match their expected values. Generally speaking, towards the middle of the eye, the bits transmitted on a given signal path will match the corresponding expected values ​​and will have a large amount of tolerance in both timing and voltage. These tolerances decrease towards the boundaries of the eye.

[0041] Figure 2 1 is a block diagram showing one embodiment of a memory controller. In the embodiment shown, the memory controller 12 includes a calibration control unit 21 and a physical interface 14. The calibration control unit 21 in the embodiment shown implements various circuit units, including a data comparator 218, an eye calculator 211, and a state machine 210. The physical interface 14 implements circuits for communicating with a memory (not shown here). The circuits of the physical interface 14 include a transceiver 22 and a delay circuit 30.

[0042] In the illustrated embodiment, the transceiver 22 of the physical interface 14 is coupled to a data bus including a data signal path DQ[7:0]. In addition, an error correction code (ECC) signal path is also coupled to the transceiver 22. In this embodiment, a data bus inversion (DBI) signal path is coupled to the transceiver 22. The DBI signal, when asserted, can cause all bits transmitted in the signal transmitted on the data signal path DQ[7:0] to be inverted, for example, all logical 0s are inverted to logical 1s. Other signal paths may exist, and in other embodiments, the data bus shown here may be implemented with a different number of bits. In this embodiment, the signal path coupled to the transceiver 22 may be calibrated as discussed above. It should be noted that in other embodiments, additional signal paths may be coupled to the transceiver 22, and some of the additional signal paths may undergo calibration from time to time. In addition, other signals may be transmitted from other circuit units (not explicitly shown here) within the physical interface 14. For example, the physical interface 14 may include a control circuit for generating a write enable signal and a read enable signal, which are transmitted to the memory during write and read operations, respectively. Similarly, a circuit unit for generating an address signal may also be included in the physical interface 14, but for the sake of simplicity, it is not shown in FIG. Figure 2 Omitted in .

[0043] During a read operation, the transceiver 22 can interpret the logic value of the signal received from the memory via the signal path DQ[7:0]. Similarly, the transceiver 22 can also determine the logic values ​​of the ECC signal and the DBI signal transmitted on its corresponding signal path. The transceiver 22 may also include an ECC circuit for correcting an erroneous value received during a read operation, and may also include an inverter circuit for inverting the logic value of the signal received via the data bus when the DBI signal is in its asserted state. It should be noted that the ECC circuit and the inverter circuit can be temporarily disabled for at least a portion of the calibration. The transceiver 22 can distinguish between logic 1 and logic 0 for a signal received via one of the illustrated signal paths based on the read voltage ReadV indicated by the eye calculator 211.

[0044] The delay circuit 30 in the illustrated embodiment is coupled to receive an input clock signal Clk_In provided from a source external to the memory controller 12. Although not explicitly shown, the delay circuit 30 may include one or more delay locked loops (DLLs) or other types of delay circuits. A delay may be applied to the input clock signal to generate a data strobe signal DQS, which is used to synchronize the transfer of other signals (e.g., DQ[7:0]) between the memory and the memory controller 12. The amount of delay applied may be based on a delay control signal Dly_Ctl provided by the eye calculator 211. In addition to passing the data strobe signal to the memory, the delay circuit 30 in the illustrated embodiment is also coupled to provide a clock signal to the transceiver 22.

[0045] During the calibration operation, the data comparison circuit 218 may receive data to be written to the memory via the DQ_In input. The data may then be transmitted from the transceiver 22 to the memory. The data read from the memory may be received by the data comparison circuit 218 from the transceiver 22 via the DQ_Out path. The data received from the memory may then be compared with the data written to the memory to determine whether any bit failures occur. A bit failure may be defined herein as a bit corresponding to a signal transmitted on a particular signal path of the data bus that does not match its expected value (e.g., read as a logic 0 when a logic 1 is expected). The bit failure may be reported to the eye calculation circuit 211. In response to receiving information about a bit failure, the eye calculation circuit 211 may record the failed bit together with a reference voltage value and a delay value (such as applied to the data strobe). Based on the data from the failed bit and the corresponding reference voltage and delay values, the eye calculation circuit 211 may calculate an eye diagram for each bit position and thus each signal path.

[0046] A given calibration operation may include multiple data writes to the memory and multiple data reads from the memory. Over multiple iterations, the eye calculator 211 may cause adjustments to both the delay used to generate the data strobe signal (via the Dly_Ctl signal) and the voltage used to distinguish between a logic 1 and a logic 0. Performing these operations for multiple different delay values ​​and read voltage values ​​may be used to define an eye diagram for the calibrated signal path. Figure 2 , wherein its height H is defined along a vertical voltage axis V, and its width W is defined along a time axis T. The voltage axis represents the value of the read voltage, while the time axis represents the delay value applied in the delay circuit 30 during the generation of the data strobe signal. Values ​​within the defined height and width of the eye diagram indicate the region where the data bits conveyed in the signal can be correctly interpreted as a logic 1 or logic 0. Regions toward the center of the eye diagram typically have a greater amount of timing tolerance and voltage tolerance than regions located toward the boundaries.

[0047] The state machine 210 in the illustrated embodiment is configured to coordinate calibration operations. In response to receiving a calibration signal (Cal) from an external source, the state machine 210 can start a calibration operation. The calibration signal can be received from, for example, a processor, system firmware, or other source. The assertion of the calibration signal is performed in conjunction with system startup, at regular intervals, and in response to changes in performance states and other conditions. During the calibration operation, the state machine 210 can communicate with the eye calculator 211, the data comparator 218, and the transceiver 22. One of the functions that the state machine 210 can perform is to issue a command to transmit data for a write operation, to cause the memory controller 12 to read data from the memory, and to cause the eye calculator 211 to cause changes to the delay and read voltage values.

[0048] Upon completion of a given calibration, the eye calculator 211 may store the read voltage and delay values ​​for each of the calibrated signal paths (or the write voltage and delay values ​​for a write calibration). These values ​​may then be used to set the read voltage and delay values ​​for normal (e.g., non-calibrated) operation. In some embodiments, these values ​​may be set based on an average of the calibrated values ​​for the various calibrated signal paths. The following embodiments are also possible and contemplated, in which offset information is communicated along with the delay and read voltage values ​​to allow the signal to be interpreted according to its own unique eye diagram for each signal path.

[0049] Figure 3 1 is a block diagram illustrating one embodiment of a system having an integrated circuit and a memory. In the illustrated embodiment, the integrated circuit 10 includes at least one processor core 105, a power management unit 108, a voltage regulator 11, and a memory controller 12. The memory controller 12 in the illustrated embodiment may be similar to the system described above with reference to FIG. Figure 2 The memory controller discussed is arranged to: The integrated circuit 10 (and more specifically, the memory controller 12 ) is coupled to a memory 158 .

[0050] Processor core 105 may be a single processor core implemented on integrated circuit 10 in some embodiments, or may be one of a plurality of different processor cores in other embodiments. In embodiments with a plurality of processor cores, the cores may be homogeneous or heterogeneous. Among other functions, processor core 105 may execute instructions of operating system 106 to perform various system-level functions. One of these functions may be a decision about when memory controller 12 performs calibration of various signal paths coupled between integrated circuit 10 and memory 158. Processor core 105 may also execute instructions of various software programs / applications. As shown here, processor core 105 is coupled to memory controller 12, and may send data to and receive data from the memory controller when performing its various operations.

[0051] The power management unit 108 in the illustrated embodiment includes various circuits for performing various power management functions of the system. Among these functions is the implementation of performance state changes. These performance state changes can include changes in the operating voltages of various circuit units in the system, and changes in the frequency of the clock signal received by the circuit unit. In some embodiments, higher performance can be achieved by increasing the clock frequency, the operating voltage, or both. Similarly, the reduction in power consumption can be achieved by reducing the operating voltage and / or reducing the clock frequency. In the illustrated embodiment, the power management unit 108 is configured to generate a voltage control signal Vctrl, which is provided to the voltage regulator 111.

[0052] In the illustrated embodiment, the voltage regulator 111 is coupled to receive a global supply voltage VddG from an external source and to provide a local supply voltage VddL to the memory controller 12. The power management unit 108 can increase or decrease the local voltage according to the state of the voltage control signal. The voltage regulator 111 can be any suitable type of circuit for supplying a regulated supply voltage, such as a switching converter (e.g., a buck converter, a boost converter) or a low dropout (LDO) regulator.

[0053] The clock control unit 109 of the power management unit 108 can perform various clock control functions. In some embodiments, the clock control unit 109 may include a circuit (e.g., a phase-locked loop) for generating a clock signal. In some embodiments, the clock signal can be provided from an external source. The clock control unit 109 may include parameters of the clock signal ClkIn. Such parameters include the frequency of the clock signal and may also include its duty cycle.

[0054] Figure 4 is a flow chart of one embodiment of a method for calibrating a signal path coupled between a memory controller and a memory. The method 400 as shown herein can be used in various device embodiments (such as the above referenced Figures 1 to 3 Device embodiments not explicitly discussed herein but capable of performing method 400 in other ways may also fall within the scope of the present disclosure.

[0055] The method 400 includes performing an initial calibration in a memory subsystem having a memory controller coupled to a memory via a set of signal paths, wherein performing the initial calibration includes activating each signal path in the set of signal paths to determine a corresponding eye diagram for the signal paths in the set (block 405). The method also includes performing a subsequent calibration, wherein performing the subsequent calibration includes activating a subset of the set of signal paths to determine updated corresponding eye diagrams for the signal paths in the subset (block 410). For remaining signal paths in the set of signal paths, the method includes determining corresponding updated eye diagrams, wherein the determining is based on information obtained during the initial calibration and is performed without activating remaining signal paths in the set of signal paths (block 415).

[0056] In various embodiments, the information obtained during the initial calibration includes voltage offsets and timing offsets between: one of the remaining signal paths in the set of signal paths and a signal path in a subset of the set of signal paths having an eye diagram that most closely matches an eye diagram of one of the remaining signal paths in the set of signal paths.

[0057] In some embodiments, method 400 includes determining an updated corresponding eye diagram for one of the signal paths in the subset of the set of signal paths during a subsequent calibration. Thus, such method embodiments may also include calculating a corresponding updated eye diagram for one of the remaining signal paths in the set of signal paths by applying a voltage offset and a timing offset to the updated corresponding eye diagram for one of the signal paths in the subset of the set of signal paths. Performing an initial calibration includes calibrating the subset of signal paths during a first scan and calibrating at least one remaining signal path in the set of signal paths during a second scan, and wherein performing a subsequent calibration includes a single scan in which the signal paths in the subset of signal paths are calibrated.

[0058] In some embodiments, calibration may be performed at different clock frequencies and more generally at different performance states. In such embodiments, for a subsequent calibration performed at a first clock frequency, the method includes: selecting calibration information for a first signal path in the subset of signal paths as a basis for determining a first updated eye diagram for a selected signal path in the remaining signal paths in the signal paths. For a subsequent calibration performed at a second clock frequency different from the first clock frequency, the method includes: selecting calibration information for a second signal path in the subset of signal paths as a basis for determining a first updated eye diagram for a selected signal path in the remaining signal paths in the signal paths.

[0059] In various embodiments, the method includes performing an initial calibration during startup of a system implementing the memory subsystem.The method then includes periodically performing one or more instances of subsequent calibration and performing the subsequent calibration instances in response to a performance state change.

[0060] Figure 5 is a flow chart of another embodiment of a method for calibrating a signal path coupled between a memory controller and a memory of a memory subsystem. Method 500 relates to an embodiment in which calibration is performed for at least two different performance states, wherein a proxy signal path is selected from a first subset to provide eye diagram information for a second subset of signal paths. Method 500 may be performed by various apparatus embodiments as discussed above. Apparatus embodiments capable of performing method 500 but not disclosed herein may be considered to fall within the scope of the present disclosure.

[0061] The method 500 includes performing a first calibration of a first signal path subgroup and a second signal path subgroup when operating in a first performance state (block 505). The first calibration may be an initial calibration performed in the particular performance state and may be performed, for example, during startup of a system in which a memory subsystem is implemented. Based on the performance of the first calibration, the method 500 further includes: for a signal path in the second subgroup, selecting a first proxy signal path from the first subgroup based on the calibration result for subsequent calibration in the first performance state, and determining an offset (block 510). The proxy signal path in the first subgroup is selected based on: having a calibration result that most closely matches the calibration result of a corresponding signal path in the second subgroup relative to other signal paths. The offset is determined based on the difference between the calibration results of the signal path in the second subgroup and its proxy in the first subgroup. For subsequent calibration in the first performance state, the signal path in the second subgroup is not directly calibrated. Instead, the calibration result of its corresponding proxy in the first subgroup is combined with the calculated offset to obtain a calibration result for the signal path in the second subgroup.

[0062] The method 500 also includes performing a second calibration of the first signal path subset and the second signal path subset when operating in the second performance state (block 515). The second performance state may differ from the first performance state in terms of clock frequency, operating voltage, or both. As with the first calibration, the second calibration is an initial calibration performed at that particular performance state. For the signal paths in the second subset, the method 500 also includes: selecting a second proxy signal path from the first subset for subsequent calibration in the second performance state based on the calibration results, and determining an offset (block 520). This may be performed in the same manner as the initial calibration performed in the first performance state. The selected signal path in the first subset may then act as a proxy for the corresponding signal path in the second subset, in lieu of direct calibration of the latter.

[0063] Note that for a given signal path in the second subset, a different proxy signal path may be selected for each of the first performance state and the second performance state. Figure 1 For brief reference, signal path 9 may have a proxy for signal path 0 for subsequent calibration performed in a first performance state while having a proxy for signal path 4 for subsequent calibration performed in a second performance state.

[0064] Generally speaking, in response to information obtained during an initial calibration for a given performance state, selection of a proxy signal path for a particular one of the second signal path subgroup is based on the differences in corresponding eye diagrams of individual signal paths in the first signal path subgroup and the particular one of the second signal path subgroup.

[0065] Referring to the difference of the calibration results between the signal paths in the second subset and their agents in the first subset, the difference can be considered as a difference in the corresponding eye diagrams. Therefore, determining the difference includes determining a voltage offset and a timing offset. In response to performing a subsequent calibration instance, the memory controller performing the calibration determines an updated eye diagram for a particular one of the second subset of signal paths by combining the voltage offset and the timing offset with the corresponding updated eye diagram of the agent signal path.

[0066] Because limitations on some embodiments may prohibit the memory controller from calibrating all signal paths in a single scan, the memory controller may perform an initial calibration in a first scan to determine corresponding eye diagrams for signal paths in a first subset and perform an initial calibration in a second scan to determine corresponding eye diagrams for signal paths in a second subset. The memory controller then performs subsequent instances of calibration in a single scan using individual ones of the signal paths in the first subset as proxies for signal paths in the second subset.

[0067] Next turn Figure 6 , which shows a block diagram of one embodiment of a system 150. In the illustrated embodiment, the system 150 includes at least one instance of the integrated circuit 10 coupled to an external memory 158. The integrated circuit 10 may include a memory controller coupled to the external memory 158. The integrated circuit 10 is coupled to one or more peripheral devices 154, and the external memory 158. A power supply 156 is also provided that supplies a supply voltage to the integrated circuit 10 and supplies one or more supply voltages to the memory 158 and / or the peripheral devices 154. In some embodiments, more than one instance of the integrated circuit 10 may be included (and more than one external memory 158 may also be included).

[0068] Depending on the type of system 150, peripherals 154 may include any desired circuitry. For example, in one embodiment, system 150 may be a mobile device (e.g., a personal digital assistant (PDA), a smart phone, etc.), and peripherals 154 may include devices for various types of wireless communications, such as WiFi, Bluetooth, cellular, global positioning systems, etc. Peripherals 154 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripherals 154 may include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc. In other embodiments, system 150 may be any type of computing system (e.g., a desktop personal computer, a laptop, a workstation, a tablet computer, etc.).

[0069] The external memory 158 may include any type of memory. For example, the external memory 158 may be an SRAM, a dynamic RAM (DRAM) such as a synchronous DRAM (SDRAM), a double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, a RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which memory devices are mounted, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc.

[0070] In various embodiments of system 150, a memory controller (e.g., implemented in IC 10) and a memory (e.g., external memory 158) may conform to various embodiments of the apparatus embodiments discussed above. Such embodiments may also be capable of performing various embodiments of the methods discussed above. IC 10 may also include other circuits disclosed herein, such as Figure 2 PMU 108 and voltage regulator 111 are shown.

[0071] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A device comprising: Memory; a memory controller coupled to the memory via a set of signal paths, wherein the memory controller is configured to: Perform an initial calibration, which includes: activating each signal path in the set of signal paths to determine a corresponding eye diagram for the signal paths in the set; Performing a subsequent calibration, the subsequent calibration comprising: activating a subset of the set of signal paths to determine updated corresponding eye diagrams for the signal paths in the subset; For remaining signal paths in the set of signal paths other than the signal paths in the subgroup, corresponding updated eye diagrams are determined, wherein the determination is based on information obtained during the initial calibration and is performed without activating the remaining signal paths in the set of signal paths.

2. The apparatus of claim 1 , wherein the information obtained during the initial calibration comprises: and, for the remaining signal paths in the set of signal paths, voltage offsets and timing offsets relative to corresponding selected signal paths in the subset of the set of signal paths.

3. An apparatus according to claim 2, wherein the memory controller is configured to: during the initial calibration, determine a signal path in the signal path subgroup having an eye diagram that most closely matches the eye diagram of the selected signal path in the remaining signal paths in the group of signal paths, and is further configured to: determine the voltage offset and the timing offset based on the difference between the eye diagram of the one signal path in the signal path subgroup and the eye diagram of the selected signal path in the remaining signal paths in the group of signal paths.

4. The apparatus of claim 1 , wherein when performing the initial calibration, the memory controller is configured to: performing a first calibration scan to determine corresponding eye diagrams for signal paths in the subset; A second calibration scan is performed to determine a corresponding eye diagram for at least one of the remaining signal paths in the set of signal paths.

5. The apparatus of claim 1 , wherein the memory controller is configured to: for one of the remaining signal paths in the set of signal paths: selecting a first signal path in the subset of signal paths as a basis for determining an eye diagram for a subsequent calibration performed at a first clock frequency; and A second signal path of the subset of signal paths is selected as a basis for determining an eye diagram for a subsequent calibration performed at a second clock frequency.

6. The apparatus of claim 1, wherein the memory controller is configured to perform the initial calibration during startup of a system in which the memory controller and the memory are implemented, and is further configured to perform one or more instances of the subsequent calibration during operation of the system.

7. The apparatus of claim 1 , wherein the memory controller is configured to: when performing the initial calibration and the subsequent calibration: performing one or more data writes to the memory; and One or more data reads from the memory are performed.

8. The apparatus of claim 1 , wherein performing the initial calibration and the subsequent calibration, the memory controller is configured to: determine the following for a given signal path in the set of signal paths: A signal transmitted on a signal path in the set of signal paths is used to distinguish a voltage of a logic 1 from a logic 0; and A time at which signals transmitted on a signal path in the set of signal paths are sampled according to a data strobe signal.

9. A method comprising: Performing an initial calibration in a memory subsystem having a memory controller coupled to a memory via a set of signal paths, wherein performing the initial calibration comprises: activating each signal path in the set of signal paths to determine a corresponding eye diagram for the signal paths in the set; Performing a subsequent calibration, wherein performing the subsequent calibration comprises: activating a subset of the set of signal paths to determine updated corresponding eye diagrams for the signal paths in the subset; For remaining signal paths in the set of signal paths other than the signal paths in the subgroup, corresponding updated eye diagrams are determined, wherein the determination is based on information obtained during the initial calibration and is performed without activating the remaining signal paths in the set of signal paths.

10. A method according to claim 9, wherein the information obtained during the initial calibration includes voltage offset and timing offset between: one of the remaining signal paths in the set of signal paths and one of the signal paths in the subset of the set of signal paths having an eye diagram that most closely matches the eye diagram of the one of the remaining signal paths in the set of signal paths.

11. The method according to claim 10, further comprising: determining, during the subsequent calibration, the updated corresponding eye diagram for the one signal path of the subset of the set of signal paths; as well as The corresponding updated eye diagram for the one of the remaining signal paths in the set of signal paths is calculated by applying the voltage offset and the timing offset to the updated corresponding eye diagram for the one of the signal paths in the subset of the set of signal paths.

12. A method according to claim 9, wherein performing the initial calibration includes calibrating the signal path subset during a first scan and calibrating at least one remaining signal path in the set of signal paths during a second scan, and wherein performing the subsequent calibration includes a single scan in which the signal paths in the signal path subset are calibrated.

13. The method according to claim 9, further comprising: for a subsequent calibration performed at the first clock frequency, selecting calibration information for a first signal path in the subset of signal paths as a basis for determining a first updated eye diagram for a selected one of the remaining ones of the signal paths; as well as For a subsequent calibration performed at a second clock frequency different from the first clock frequency, calibration information for a second signal path in the subset of signal paths is selected as a basis for determining a second updated eye diagram for the selected one of the remaining ones of the signal paths.

14. The method according to claim 9, further comprising: performing the initial calibration during startup of a system implementing the memory subsystem; periodically performing one or more instances of said subsequent calibration; as well as In response to the performance state changing, an instance of the subsequent calibration is performed.

15. A system comprising: Memory; a memory controller coupled to the memory via a plurality of signal paths including a first subset of signal paths and a second subset of signal paths, wherein the memory controller is configured to: performing an initial calibration to determine a respective eye diagram associated with each of the first subset of signal paths and the second subset of signal paths; For a first signal path in the second signal path subgroup, selecting a corresponding one of the first signal path subgroup as a proxy signal path; performing one or more instances of subsequent calibration, wherein a given instance of the one or more instances of subsequent calibration comprises: activating the first subset of signal paths to determine a first updated corresponding set of eye diagrams; An updated eye diagram for the first signal paths in the second subset of signal paths is determined based on the updated corresponding eye diagrams of the proxy signal paths.

16. A system according to claim 15, wherein the memory controller is configured to: in response to information obtained during the initial calibration, select the proxy signal path for the first signal path in the second signal path subgroup based on the difference between the corresponding eye diagrams of the individual signal paths in the first signal path subgroup and the first signal path in the second signal path subgroup.

17. A system according to claim 16, wherein the difference in the corresponding eye diagrams includes determining a voltage offset and a timing offset, and wherein the memory controller is configured to: in response to performing the subsequent calibration instance, determine an updated eye diagram for the first signal path in the second signal path subgroup by combining the voltage offset and the timing offset with the corresponding updated eye diagram of the proxy signal path.

18. The system of claim 15, wherein the memory controller is configured to periodically perform the subsequent instance of calibration and is further configured to perform the subsequent instance of calibration in response to a performance state change.

19. The system of claim 15, wherein the memory controller is further configured to: performing a portion of said initial calibration in a first performance state; selecting a first proxy path for the first signal path in the second subset of signal paths based on results obtained from the initial calibration at the first performance state; performing a portion of said initial calibration in a second performance state; as well as A second proxy path is selected for the first signal path in the second subset of signal paths based on results obtained from the initial calibration at the second performance state.

20. The system of claim 15, wherein the memory controller is further configured to: performing the initial calibration in a first scan to determine corresponding eye diagrams for signal paths in the first subset of signal paths, and performing the initial calibration in a second scan to determine corresponding eye diagrams for signal paths in the second subset of signal paths; This example of subsequent calibration is performed in a single scan.

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