Three-dimensional memory and methods of manufacturing the same

Abstract

This disclosure relates to a three-dimensional memory and a method for manufacturing the same. The method includes: forming a memory chip on a first substrate; disposing a semiconductor layer on the memory chip; forming contacts penetrating the semiconductor layer; and forming a first peripheral circuit chip based on the semiconductor layer, wherein the first peripheral circuit chip is electrically connected to the memory chip via the contacts.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a three-dimensional memory and a method for manufacturing the same. Background Technology

[0002] Three-dimensional memory has a higher storage density than traditional two-dimensional memory, but further increasing the storage density of three-dimensional memory remains a goal pursued by the industry.

[0003] To further improve the storage density of 3D memory, some existing methods involve fabricating the peripheral circuitry within a peripheral circuit chip, and then fabricating the memory chip on top of that peripheral circuit chip.

[0004] However, the high-temperature manufacturing process used in existing memory chip production technologies carries the risk of thermal degradation in peripheral circuit chips, which reduces the reliability of 3D memory to some extent. Furthermore, the choice of materials for peripheral circuit chips is limited by the memory chip manufacturing process; for example, copper interconnects cannot be used for metal interconnects, leading to performance bottlenecks in the peripheral circuits. In addition, as the number of stacked layers in memory chips continues to increase, the horizontal dimensions of the memory chip can be continuously reduced, posing a greater challenge to the horizontal dimensions of the peripheral circuit chips. Summary of the Invention

[0005] The embodiments disclosed herein can at least solve one or more of the technical problems in the prior art described above, or can be used to solve some other technical problems in the prior art.

[0006] One aspect of this disclosure provides a method for manufacturing a three-dimensional memory, the method comprising: forming a memory chip on a first substrate; disposing a semiconductor layer on the memory chip; forming contacts penetrating the semiconductor layer; and forming a first peripheral circuit chip based on the semiconductor layer, wherein the first peripheral circuit chip is electrically connected to the memory chip via the contacts.

[0007] A method for manufacturing a three-dimensional memory according to one embodiment further includes forming a second peripheral circuit chip on the first peripheral circuit chip.

[0008] In one embodiment, at least one of the first peripheral circuit chip and the second peripheral circuit chip includes copper interconnects.

[0009] A method for manufacturing a three-dimensional memory according to one embodiment further includes: removing at least a portion of the first substrate to expose the memory chip; and forming a common source layer on the exposed portion of the memory chip.

[0010] In one embodiment, the memory chip includes a channel structure. After removing at least a portion of the first substrate and before forming the common source layer, the method of manufacturing the three-dimensional memory further includes: ion implantation of the channel structure; and laser annealing of the common source layer after its formation.

[0011] In one embodiment, the memory chip includes a through-array of contacts. The method of manufacturing a three-dimensional memory further includes forming a lead-out structure on the side of the common-source layer opposite to the memory chip, wherein the lead-out structure is electrically connected to the common-source layer and electrically connected to the first peripheral circuit chip via the through-array of contacts.

[0012] In one embodiment, the step of forming a semiconductor layer on the memory chip includes: forming a first auxiliary wafer on the memory chip, wherein the first auxiliary wafer includes a bonding layer attached to the memory chip and a precursor located on the bonding layer; performing hydrogen ion implantation on the precursor to form a hydrogen-rich layer in the precursor; splitting the precursor based on the hydrogen-rich layer, such that a portion of the precursor located below the hydrogen-rich layer remains on the bonding layer; and performing mechanochemical polishing on the portion of the precursor located below the hydrogen-rich layer to form the semiconductor layer.

[0013] In one embodiment, the precursor material includes silicon.

[0014] In one embodiment, the step of setting a semiconductor layer on the memory chip includes: setting a second auxiliary wafer on the memory chip, wherein the second auxiliary wafer includes a connection layer, the semiconductor layer, a buried oxide layer and a second substrate sequentially disposed in a direction away from the memory chip; and removing the second substrate and the buried oxide layer from the second auxiliary wafer.

[0015] In one embodiment, the step of forming the first peripheral circuit chip includes: forming a shallow trench isolation structure that extends at least partially into the semiconductor layer; forming a gate structure between a pair of the shallow trench isolation structures and on the semiconductor layer; and forming a source region and a drain region, respectively located on both sides of the gate structure, in the portion of the semiconductor layer located between the pair of shallow trench isolation structures.

[0016] Another aspect of this disclosure provides a three-dimensional memory. The three-dimensional memory includes: a memory chip; and a first peripheral circuit chip including a semiconductor layer disposed on the memory chip, wherein a source region and a drain region disposed on the semiconductor layer are located on the side of the semiconductor layer opposite to the memory chip.

[0017] In one embodiment, the three-dimensional memory further includes a second peripheral circuit chip disposed on the first peripheral circuit chip and including copper interconnects.

[0018] In one embodiment, the three-dimensional memory further includes a common-source layer disposed under the memory chip.

[0019] In one embodiment, the memory chip includes through-array contacts; and the three-dimensional memory further includes: an outgoing structure electrically connected to the common source layer and electrically connected to the first peripheral circuit chip through the through-array contacts.

[0020] The method for manufacturing a three-dimensional memory according to some embodiments of this disclosure first manufactures the memory chip and then manufactures the peripheral circuit chip. This allows for greater flexibility in the material selection and process route of the peripheral circuit chip, avoiding the impact of the memory chip's manufacturing process on the performance of the peripheral circuit. The three-dimensional memory manufacturing method according to some embodiments of this disclosure also ensures the small size characteristics of the three-dimensional memory, thereby contributing to an increase in the storage density of the three-dimensional memory.

[0021] Furthermore, the three-dimensional memory manufactured according to some embodiments of this disclosure is suitable for further processing of the memory chip from the back side. This method of manufacturing a three-dimensional memory allows for gate-induced drain leakage (GIDL) type erasure and is also suitable for designing the common source as a back-side pickup structure. Attached Figure Description

[0022] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0023] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional memory according to embodiments of the present disclosure; and

[0024] Figures 2 to 21 This is a process diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Detailed Implementation

[0025] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this disclosure, for example, a first contact discussed below may also be referred to as a second contact, and vice versa.

[0027] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the first substrate and the thickness of the memory chip are not to scale in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0028] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0029] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. (See reference) Figure 1 The method 1000 for manufacturing a three-dimensional memory provided in this disclosure may include:

[0032] Step S101: Form a memory chip on the first substrate.

[0033] Step S102: Set a semiconductor layer on the memory chip.

[0034] Step S103: Form a contact that penetrates the semiconductor layer.

[0035] Step S104: A first peripheral circuit chip is formed based on the semiconductor layer. The first peripheral circuit chip is electrically connected to the memory chip through contacts.

[0036] The following combination Figures 2 to 21 Exemplary processing methods for manufacturing three-dimensional memory are described in detail according to some embodiments of the present disclosure.

[0037] Step S101

[0038] A memory chip 2 is formed on the first substrate 1.

[0039] refer to Figure 2 The first substrate 1 may be, for example, a composite substrate, comprising a first wafer 11, an isolation layer 12, and an etch stop layer 13. Exemplarily, the material of the first wafer 11 includes at least one of silicon (Si), germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. The material of the isolation layer 12 includes oxide. The material of the etch stop layer 13 may be selected according to the hierarchical structure and materials of the memory chip 2 to be formed. The etch stop layer 13 can be used as a stop layer for a corresponding etching process during the formation of the memory chip 2.

[0040] The memory chip 2 is used to implement memory functions. Exemplarily, the memory structure 21 of the memory chip 2 is a three-dimensional NAND memory structure. The memory structure 21 includes alternately stacked gate layers 211 and insulating layers 212. The gate layer 211 may include a control gate 211B and a select gate 211A, wherein the select gate 211A may be a top select gate or a bottom select gate. Figure 2 The selection gate is schematically represented as a bottom selection gate. In some exemplary embodiments, the memory chip 2 may also include a channel structure 22, an insulating fill layer 23, through-array contacts 24, and a first interconnect structure 25.

[0041] The channel structure 22 extends through the memory structure 21 along the stacking direction and partially extends into the etch stop layer 13. The channel structure 22 includes a functional layer, a channel layer, and an insulating core filling layer arranged sequentially. The functional layer of the channel structure 22, in the portion corresponding to the control gate, includes at least a barrier layer, a charge storage layer, and a tunneling layer (layered structure not shown). Other portions of the channel structure 22 may vary depending on different etching, via, and deposition processes. For example, the channel structure 22 may include a drain at the top and a source at the bottom. The portion of the channel structure 22 corresponding to each control gate, together with the control gate, constitutes a memory cell.

[0042] An insulating filler layer 23 may cover the storage structure 21. Through-array contacts 24 may be disposed on the side of the storage structure 21, for example... Figure 2 As shown, the through-array contact 24 is located on the right side of the storage structure 21 in a direction parallel to the first substrate 1. Furthermore, the through-array contact 24 can extend partially from the insulating fill layer 23 to the etch stop layer 13 of the first substrate 1 along the stacking direction.

[0043] The first interconnect structure 25 can be disposed on the memory structure 21 and electrically connected to the gate layer 211, the channel structure 22, and the through-array contacts 24, respectively. The specific arrangement of the first interconnect structure 25 can be designed according to requirements, and it can be used as an interface for electrical connection with peripheral circuit chips to be manufactured, such as the first peripheral circuit chip.

[0044] Step S102

[0045] A semiconductor layer is set on memory chip 2. Different methods can be used to set the semiconductor layer. Figures 3 to 6 This illustrates a process route for fabricating a semiconductor layer 302 on a memory chip 2. Figures 7 to 10 This illustrates another process route for setting a semiconductor layer 41 on the memory chip 2.

[0046] In some implementations, a first auxiliary wafer 3 may be disposed on the memory chip 2. (See reference...) Figure 3 The auxiliary wafer 3 includes a bonding layer 32 and a precursor 30. The bonding layer 32 is used for connection to the memory chip 2. Exemplarily, the top layer of the memory chip 2 and the bonding layer 32 may include the same oxide. The material of the top layer of the memory chip 2 may include, for example, silicon dioxide, and the material of the bonding layer 32 may include, for example, silicon dioxide. In this embodiment, a monolithic first auxiliary wafer 3 can be fabricated first, and then the bonding layer 32 can be connected to the memory chip 2 by bonding. Figure 4 As shown, the memory chip 2 can be located on the first substrate 1, and a thicker precursor 30 is also provided on the memory chip 2.

[0047] refer to Figure 5Hydrogen ion implantation is performed on the precursor 30 to form a hydrogen-rich layer 301 in the precursor 30. Exemplarily, the thickness of the precursor 30 is designed according to the process parameters of hydrogen ion implantation to ensure that the position of the hydrogen-rich layer 301 is at a certain height above the interconnect layer 32, thereby ensuring that the thickness of the portion of the precursor 30 below the hydrogen-rich layer 301 is not less than the thickness of the semiconductor layer 302 to be formed.

[0048] refer to Figure 5 and Figure 6 The precursor 30 is split based on the hydrogen-rich layer 301. Specifically, because the hydrogen-rich layer 301 is rich in hydrogen, its structural strength decreases. The precursor can be induced to break at the hydrogen-rich layer 301 through a certain induction method. The portion of the precursor 30 located below the hydrogen-rich layer 301 and a portion of the hydrogen-rich layer 301 remain on the connecting layer 32, i.e., on the memory chip 2. The portion 303 of the precursor 30 located above the hydrogen-rich layer 301 and another portion of the hydrogen-rich layer 301 detach together.

[0049] Since the top surface obtained after splitting the precursor 30 may be irregular, in this embodiment, the portion of the precursor 30 remaining in the connecting layer 32 can be further subjected to mechanochemical polishing. For example, the remaining portion of the hydrogen-rich layer 301 can be completely removed, and the portion of the precursor 30 located below the hydrogen-rich layer 301 can be mechanochemically polished to form the semiconductor layer 302.

[0050] In an exemplary embodiment, the material of precursor 30 may include, for example, silicon. Further, the material of semiconductor layer 302 may include, for example, silicon.

[0051] In some other embodiments, step S102 may include the following steps.

[0052] A second auxiliary wafer 4 is mounted on memory chip 2. (Reference) Figure 7 The second auxiliary wafer 4 includes a connection layer 42, a semiconductor layer 41, a buried oxide layer 43, and a second substrate 44 sequentially disposed. The second auxiliary wafer 4 can be prefabricated as a single unit and then bonded to the memory chip 2. For example, using silicon-on-insulator (SiI) fabrication techniques, the semiconductor layer 41 is formed on the buried oxide layer 43 on the second substrate 44, and then the connection layer 42 is formed on the semiconductor layer 41. This method results in a thinner semiconductor layer 41. Exemplarily, the top layer and the connection layer 42 of the memory chip 2 may, for example, comprise the same oxide. The material of the top layer of the memory chip 2 may, for example, comprise silicon dioxide, and the material of the connection layer 42 may, for example, comprise silicon dioxide. The connection layer 42 is bonded to the memory chip 2 by bonding. Figure 8 As shown, the structure formed through the above steps is similar to... Figure 4The structure shown is different. In this structure, the memory chip 2 is still located on the first substrate 1, but a semiconductor layer 41, a buried oxide layer 43, and a second substrate 44 are stacked on the memory chip 2 in sequence.

[0053] In one embodiment, step S102 further includes removing the second substrate 44 and the buried oxide layer 43 from the second auxiliary wafer 4. The material of the second substrate 44 may include, for example, silicon.

[0054] Specifically, the second substrate 44 can be removed first. For example... Figure 9 As shown, after the second substrate 44 is removed, a memory chip 2 is disposed on the first substrate 1, a semiconductor layer 41 is disposed on the memory chip 2, and a buried oxide layer 43 to be removed is disposed on the semiconductor layer 41.

[0055] The buried oxide layer 43 can be removed by etching to obtain, as shown below. Figure 10 The structure shown has the top of the memory chip 2 bonded to the interconnect layer 42, and the semiconductor layer 41 can be disposed on the memory chip 2 through the interconnect layer 42.

[0056] Steps S103 and S104

[0057] First contacts 53a-53b are formed through the semiconductor layer 50. In step S012, the semiconductor layer 50 described in the following exemplary steps can be formed using different process routes, and the specific route can be selected according to actual production needs.

[0058] The first contacts 53a-53b extend into the memory chip 2 and are electrically connected to the first interconnect structure 25. Exemplarily, step S103 may be performed before or after step S104 described below, or between multiple sub-steps of step S104 described below. Steps S103 and S104 will be described in detail below.

[0059] A first peripheral circuit chip 5 is formed on the semiconductor layer 50. The first peripheral circuit chip 5 is electrically connected to the memory chip 2 through the first contacts 53a to 53b.

[0060] In some exemplary embodiments, the preceding step of forming a semiconductor layer 50 on the memory chip 2, and then forming the first peripheral circuit chip 5, may include: forming a first peripheral circuit 51 based on the semiconductor layer 50; and forming a second interconnect structure 52 on the first peripheral circuit 51. The second interconnect structure 52 is electrically connected to the first peripheral circuit 51 and may be electrically connected to the first contacts 53a-53b. Step S103 may be performed before step S104; or it may be performed after forming the first peripheral circuit 51 and before forming the second interconnect structure 52.

[0061] refer to Figure 11The diagram illustrates the structure obtained after performing step S103 and forming the first peripheral circuit 51. In this structure, a memory chip 2 is disposed on a first substrate 1, and a semiconductor layer 50 on the memory chip 2 on which the first peripheral circuit 51 is disposed. Further, an insulating cover layer 54 is disposed on the semiconductor layer to cover the first peripheral circuit 51. First contacts 53a-53b penetrate the insulating cover layer 54 and the semiconductor layer 50 and are electrically connected to the first interconnect structure 25 in the memory chip 2.

[0062] Figure 12 The structure after the formation of the second interconnect structure 52 is shown. This structure includes a first substrate 1, a memory chip 2, a first peripheral circuit chip 5, and first contacts 53a-53b. The memory chip 2 is disposed on the first substrate 1. The first peripheral circuit chip 5 is disposed on the memory chip 2 and includes a first peripheral circuit 51 and a second interconnect structure 52. The first contacts 53a-53b extend from the first peripheral circuit chip 5 into the memory chip 2. The first peripheral circuit 51 can be electrically connected to the first contacts 53a-53b through the second interconnect structure 52, and further electrically connected to the first interconnect structure 25 in the memory chip 2.

[0063] For example, the material of the first contacts 53a-53b may include tungsten. The material of the second interconnect structure 52 may also include tungsten.

[0064] In other embodiments, the material of the first contacts 53a-53b may include copper. Exemplarily, when employing a partitioned manufacturing process, the regions containing the first contacts 53a for electrically connecting through the array contacts 24 and the first contacts 53b for electrically connecting the gate layer 211 may utilize different process technologies and thus be subjected to different temperatures. Therefore, some of the first contacts 53a-53b may be made of tungsten, while others may be made of copper. Exemplarily, the second interconnect structure 52 may be a copper interconnect.

[0065] The first circuit 51 may include various semiconductor devices such as complementary metal-oxide-semiconductor (CMOS), field-effect transistors, capacitors, inductors, and / or PN junction diodes, wherein the CMOS transistors may include high-voltage transistors and low-voltage transistors. These semiconductor devices in the first circuit 51 are used to implement different functions of the three-dimensional memory, such as operation of memory cells, caching, amplification, decoding, and data I / O.

[0066] In an exemplary embodiment, the step of forming the first peripheral circuit chip 5 includes: forming a shallow trench isolation structure 511 that extends at least partially into the semiconductor layer 50; forming a gate structure 512 between a pair of shallow trench isolation structures 511 and on the semiconductor layer 50; and forming a source region 513 and a drain region 514, respectively located on opposite sides of the gate structure 512, in a portion of the semiconductor layer 50 located between the pair of shallow trench isolation structures 511. Exemplarily, the first circuit 51 may also be covered with an isolation layer 515.

[0067] For example, the step of forming the first contacts 53a-53b includes the following sub-steps. First, a hole is formed that penetrates the insulating cover layer 54, the isolation layer 515, and the semiconductor layer 50 and extends into the memory chip 2, the bottom end of which exposes the interconnect layer of the memory chip 2. Then, the first contacts 53a-53b are formed in the hole, such that the first contacts 53a-53b are electrically connected to the interconnect layer of the memory chip 2.

[0068] In an exemplary embodiment, the method 1000 further includes forming a second peripheral circuit chip on the first peripheral circuit chip. Exemplarily, a third peripheral circuit chip may also be formed on the second peripheral circuit chip. The three-dimensional memory manufactured by the method of manufacturing three-dimensional memory provided in this disclosure may include only one layer of peripheral circuit chips on a single memory chip, which is then packaged; or it may include at least two stacked layers of peripheral circuit chips. The manufacturing process of the second peripheral circuit chip disposed on the bottommost first peripheral circuit chip is similar to the manufacturing process of the first peripheral circuit chip.

[0069] Specifically, the method 1000 may include the following steps: disposing a second semiconductor layer 60 on a first peripheral circuit chip 5; forming second contacts 63a-63b penetrating the second semiconductor layer 60; and forming a second peripheral circuit chip 6 based on the second semiconductor layer 60. In this embodiment, the aforementioned semiconductor layer 50 can be regarded as the first semiconductor layer.

[0070] The structure of the second semiconductor layer 60 can be substantially the same as that of the aforementioned semiconductor layer 50 (first semiconductor layer), and the manufacturing method of the second semiconductor layer 60 can also be the same as that of the semiconductor layer 50. For example... Figure 13 The diagram shows the structure after the formation of the second semiconductor layer 60. In this embodiment, the aforementioned semiconductor layer 50 can be considered as the first semiconductor layer. Figure 13The structure shown includes at least a first substrate 1, a memory chip 2, a first peripheral circuit chip 5, a second peripheral circuit chip 6, and second contacts 53a-53b. The memory chip 2 is disposed on the first substrate 1. The first peripheral circuit chip 5 is disposed on the memory chip 2 and includes a first peripheral circuit 51 and a second interconnect structure 52. The first contacts 53a-53b extend from the peripheral circuit chip 5 into the memory chip 2. The first peripheral circuit 51 can be electrically connected to the first contacts 53a-53b through the second interconnect structure 52, and further electrically connected to the first interconnect structure in the memory chip 2.

[0071] The structure and manufacturing method of the second contact can be the same as those of the first contact. In an exemplary embodiment, the material of the contacts in the outermost peripheral circuit chip can be copper, and the material of the inner contacts and contact sides can be tungsten. If a partitioned manufacturing process is used, the material of the inner contacts can also include copper. In summary, the method for manufacturing three-dimensional memory provided by this disclosure, since the memory chip is manufactured first, has fewer restrictions on the manufacturing process of the peripheral circuit chip, making the manufacturing process of the peripheral circuit more flexible and allowing for a wider range of material choices, which helps to improve the performance of the peripheral circuit.

[0072] Furthermore, the steps for forming the second peripheral circuit chip include: forming the second peripheral circuit; and forming the third interconnect structure. (See reference) Figure 14 The diagram illustrates the structure after the formation of the second peripheral circuit chip 6. In other embodiments, subsequent peripheral circuit chips, such as a third peripheral circuit chip, may be disposed on top of the second peripheral circuit chip 6.

[0073] like Figure 14 As shown, the second peripheral circuit chip 6 includes a second peripheral circuit 61 disposed on the second semiconductor layer 60 and a third interconnect structure 62. The second peripheral circuit 61 may include, for example, a low-voltage CMOS transistor and an ultra-low-voltage CMOS transistor. The third interconnect structure 62 may be electrically connected to the second peripheral circuit 61 and the second contacts 63a-63b, respectively. The third interconnect structure 62 may be electrically connected to the memory chip 2 through the second contacts 63a-63b.

[0074] By setting up multi-layered peripheral circuits, CMOS transistors manufactured using different processes can be placed in different layers of peripheral circuits. This simplifies the manufacturing process of each layer and allows for different optimizations to be applied to the peripheral circuits of different layers, thereby improving the overall performance of the peripheral circuits in the 3D memory. Furthermore, the horizontal dimensions of the peripheral circuit chips can be reduced to accommodate smaller memory chips, thus increasing the storage density of the 3D memory.

[0075] For example, the material of the third interconnect structure 62 may include copper. In this embodiment, the second peripheral circuit chip 6 is the uppermost peripheral circuit chip. Furthermore, a process layer 7 for picking up and manipulating the entire structure can be provided on the second peripheral circuit chip 6 to obtain... Figure 15 The structure is shown. Exemplarily, process layer 7 is a wafer. Furthermore, in the method provided in this embodiment, process layer 7 can be connected to the uppermost peripheral circuit chip via bonding. In other embodiments, when there is no second peripheral circuit chip, the process layer can be connected to the first peripheral circuit chip.

[0076] For example, the entire structure can be flipped over by manipulating the process layer, i.e., the process layer is on the bottom and the first substrate is on top.

[0077] The method for manufacturing a three-dimensional memory provided in this disclosure may further include the following steps: removing at least a portion of a first substrate to expose a memory chip; and forming a common source layer on the exposed portion of the memory chip.

[0078] Figure 16 The structure after removing the first substrate 1 is shown. The back side 201 of the memory chip 2 is exposed. Specifically, the ends of the channel structure 22 and the through array contacts 24 are exposed. The method for manufacturing a three-dimensional memory provided in this disclosure exposes the channel structure 22, thus allowing optimization of the portion of the channel structure 22 corresponding to the bottom select gate 211A, specifically optimizing the doping profile of the material in this portion.

[0079] In other embodiments, the material of the formed process layer 7 includes oxides. Exemplarily, a thick oxide layer is formed by physical vapor deposition or chemical vapor deposition to obtain... Figure 17 The structure shown is further shown. By operating process layer 7, the structure can be flipped over, thereby removing the first substrate 1, to obtain the structure shown. Figure 18 The structure shown.

[0080] In an exemplary implementation, reference Figure 19 Prior to the step of forming the common source layer, the channel structure 22 may be ion implanted. Figure 19 The diagram illustrates multiple channel structures 22, but in reality, a large number of channel structures 22 can be arranged in the memory chip 2.

[0081] After exposing the back surface 201 of the memory chip 2, a common-source layer 8 is formed. For example, as... Figure 20 In the structure shown, the memory chip 2 is located on the first peripheral circuit chip 5, and a common source layer 8 is disposed on the memory chip 2. The material of the common source layer 8 may include, for example, polysilicon. The common source layer 8 may be electrically connected to the channel structure 22.

[0082] For example, after forming the common source layer, the method for manufacturing a three-dimensional memory provided in this disclosure further includes: laser annealing the common source layer.

[0083] like Figure 20 As shown, the common source layer 8 can be laser annealed. Laser annealing helps to adjust the stress of the newly formed common source layer 8. Furthermore, if the channel structure 22 has undergone ion implantation, this laser annealing process also facilitates dopant activation in the channel structure 22.

[0084] Exemplarily, the method for manufacturing a three-dimensional memory provided in this disclosure exposes the back side of the memory chip, i.e., the common-source layer is now exposed. Therefore, the method may further include forming an lead-out structure on the side of the common-source layer opposite to the memory chip. Exemplarily, forming as... Figure 21 The three-dimensional memory shown.

[0085] The lead-out structure 9 is electrically connected to the common source layer 8. The lead-out structure 9 can also be electrically connected to the first peripheral circuit chip 5 through the array contacts 24. The lead-out structure 9 may include pads 91, which can be used for electrical connection to external devices.

[0086] The method for manufacturing a three-dimensional memory disclosed herein is suitable for manufacturing a back-lead type three-dimensional memory.

[0087] Another aspect of this disclosure provides a three-dimensional memory. (See reference...) Figure 21 The three-dimensional memory includes a memory chip 2 and a first peripheral circuit chip 5. The first peripheral circuit chip 5 includes a semiconductor layer 50 disposed beneath the memory chip 2. A source region 513 and a drain region 514 disposed on the semiconductor layer 50 are located on the side of the semiconductor layer 50 opposite to the memory chip 2. It can be understood that the description of the vertical and horizontal orientations in this embodiment is for... Figure 21 The placement of the three-dimensional memory is not a limitation on how the three-dimensional memory is used or manufactured.

[0088] Exemplarily, the three-dimensional memory further includes a second peripheral circuit chip 6. The second peripheral circuit chip 6 is disposed on the first peripheral circuit chip 5. Exemplarily, the second peripheral circuit chip 6 may include copper interconnects.

[0089] For example, the three-dimensional memory also includes a common source layer 8 disposed under the memory chip 2.

[0090] For example, the memory chip 2 includes through-array contacts 24. The three-dimensional memory also includes a lead-out structure 9. The lead-out structure 9 is electrically connected to the common source layer 8. The lead-out structure 9 can be electrically connected to the first peripheral circuit chip 5 through the through-array contacts 24. This three-dimensional memory has high storage density and good performance. The memory chip can adopt a back-side lead-out structure to adapt to circuit requirements.

[0091] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this disclosure.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A memory chip is formed on the first substrate; A semiconductor layer is disposed on the memory chip; Forming contacts that penetrate the semiconductor layer; as well as A first peripheral circuit chip is formed based on the semiconductor layer. Wherein, the contact extends from the first peripheral circuit chip to the memory chip; and The first peripheral circuit chip is electrically connected to the memory chip through the contact.

2. The method according to claim 1, wherein, Also includes: A second peripheral circuit chip is formed on the first peripheral circuit chip.

3. The method according to claim 2, wherein, At least one of the first peripheral circuit chip and the second peripheral circuit chip includes copper interconnects.

4. The method according to claim 1, wherein, Also includes: At least a portion of the first substrate is removed to expose the memory chip; as well as A common source layer is formed on the exposed portion of the memory chip.

5. The method according to claim 4, wherein, The memory chip includes a channel structure; and After removing at least a portion of the first substrate and before forming the common source layer, the method further includes: ion implantation into the channel structure; and After forming the common source layer, the method further includes: laser annealing the common source layer.

6. The method according to claim 5, wherein, The memory chip includes through-array contacts; as well as The method further includes: An outgoing structure is formed on the side of the common source layer opposite to the memory chip, wherein the outgoing structure is electrically connected to the common source layer and electrically connected to the first peripheral circuit chip through the through-array contacts.

7. The method according to claim 1, wherein, The step of forming a semiconductor layer on the memory chip includes: A first auxiliary wafer is disposed on the memory chip, wherein the first auxiliary wafer includes a bonding layer attached to the memory chip and a precursor located on the bonding layer; The precursor is subjected to hydrogen ion implantation to form a hydrogen-rich layer in the precursor; Based on the hydrogen-rich layer, the precursor is split, so that the portion of the precursor located below the hydrogen-rich layer remains on the connecting layer; The portion of the precursor located below the hydrogen-rich layer is subjected to mechanochemical polishing to form the semiconductor layer.

8. The method according to claim 7, wherein, The precursor material includes silicon.

9. The method according to claim 1, wherein, The step of forming a semiconductor layer on the memory chip includes: A second auxiliary wafer is disposed on the memory chip, wherein the second auxiliary wafer includes a connection layer, a semiconductor layer, a buried oxide layer, and a second substrate sequentially disposed in a direction away from the memory chip; and The second substrate and the buried oxide layer are removed from the second auxiliary wafer.

10. The method according to claim 1, wherein, The steps for forming the first peripheral circuit chip include: A shallow trench isolation structure is formed that extends at least partially into the semiconductor layer; A gate structure is formed between the pair of shallow trench isolation structures and on the semiconductor layer; and A source region and a drain region are formed on both sides of the gate structure in the portion of the semiconductor layer located between the pair of shallow trench isolation structures.

11. A three-dimensional memory, characterized in that, include: Memory chips; The first peripheral circuit chip includes a semiconductor layer disposed on the memory chip, wherein the source region and drain region disposed on the semiconductor layer are located on the side of the semiconductor layer opposite to the memory chip; as well as The contacts extend in the first peripheral circuit chip, penetrate the semiconductor layer, and extend into the memory chip, connecting the first peripheral circuit chip and the memory chip.

12. The three-dimensional memory according to claim 11, wherein, Also includes: The second peripheral circuit chip is disposed on the first peripheral circuit chip and includes copper interconnects.

13. The three-dimensional memory according to claim 11, characterized in that, Also includes: The common source layer is located under the memory chip.

14. The three-dimensional memory according to claim 13, characterized in that, The memory chip includes through-array contacts; as well as The three-dimensional memory also includes: The lead-out structure is electrically connected to the common source layer and electrically connected to the first peripheral circuit chip through the through-array contacts.

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