Physical unclonable function device and operation method thereof, and electronic device

Abstract

The present disclosure provides a physical unclonable function device and an operation method thereof, and an electronic device. The physical unclonable function device includes: a first signal generating circuit, configured to generate a first clock signal of the nth period according to a control signal of the nth period and an input signal of the nth period, where n is an integer greater than or equal to 2; a second signal generating circuit, configured to generate a second clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period; an output circuit, configured to output an output signal of the nth period according to the first clock signal of the nth period and the second clock signal of the nth period; and a control circuit, configured to process an initial control signal of the nth period according to a reference value to obtain a control signal of the nth period, wherein the reference value includes a logic level of an output signal of an n-1th period.

Description

Technical Field

[0001] The present disclosure relates to the field of information security technology, and in particular to a PUF (physical unclonable function) device and an operation method thereof, and an electronic device. Background Art

[0002] With the development of information technology, the security issues of electronic devices have become increasingly prominent. Physically Unclonable Function (PUF) technology is one of the solutions to the security problem, which shows higher security at a lower cost. Summary of the invention

[0003] According to one aspect of an embodiment of the present disclosure, a physical unclonable function device is provided, including: a first signal generating circuit, configured to generate a first clock signal of the nth period according to a control signal of the nth period and an input signal of the nth period, where n is an integer greater than or equal to 2; a second signal generating circuit, configured to generate a second clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period; an output circuit, configured to output an output signal of the nth period according to the first clock signal of the nth period and the second clock signal of the nth period; and a control circuit, configured to process an initial control signal of the nth period according to a reference value to obtain a control signal of the nth period, wherein the reference value includes a logic level of the output signal of the n-1th period.

[0004] In some embodiments, the first signal generating circuit includes a first time average frequency direct period synthesis TAF-DPS circuit, and the second signal generating circuit includes a second TAF-DPS circuit; the control signal includes a control word, and the initial control signal includes an initial control word.

[0005] In some embodiments, the initial control word C=F+r, wherein F is an integer and r is a decimal greater than 0 and less than 1; the control word C(n) of the nth cycle is obtained by performing a mathematical operation on at least one of F and r and the reference value.

[0006] In some embodiments, each of the first clock signal and the second clock signal has a first period with probability r and a second period with probability 1-r, the first period is F+1, and the second period is F.

[0007] In some embodiments, C(n)=M+N, wherein M is one of F and r, and N is obtained by performing a mathematical operation on the other of F and r and the reference value.

[0008] In some embodiments, M is F, and N is obtained by performing a mathematical operation on r and the reference value.

[0009] In some embodiments, the mathematical operation comprises a multiplication operation.

[0010] In some embodiments, is the number of digits after the decimal point in r, ri = 0.p, p is the last i digits in r, Indicates the logic level of the output signal of the nith cycle; when ni is less than or equal to 0,

[0011] In some embodiments, r=0.5.

[0012] In some embodiments, each of the first TAF-DPS circuit and the second TAF-DPS circuit is configured to determine an input signal of an nth cycle according to a control word of the nth cycle.

[0013] In some embodiments, the physical unclonable function device further includes: a ring oscillator, configured to generate K clock signals with the same frequency, wherein the jth clock signal and the j-1th clock signal have the same time interval, K is an integer greater than or equal to 2, and j is any integer between 2 and K; the first TAF-DPS circuit includes: a first accumulator, configured to calculate the accumulated value A1(n) of the nth cycle in the first accumulator according to the following formula: A1(n)=(A1(n-1)+C(n))(mod K), wherein A1(n-1) is the accumulated value of the n-1th cycle in the first accumulator, C(n) is the control word of the nth cycle, C(n) is greater than or equal to 2 and less than or equal to 2K-1; a first multiplexer; and a first register, configured to control the first multiplexer to select one of K clock signals as the input signal of the nth cycle according to the integer in A1(n); and the second TAF-DPS circuit includes: a second accumulator, configured to calculate the accumulated value A2(n) of the nth cycle in the second accumulator according to the following formula: A2(n)=(A2(n-1)+C(n))(mod K), wherein A2(n-1) is the accumulated value of the n-1th cycle in the second accumulator, A2(1)=A1(1), A2(n)=A1(n); a second multiplexer; and a second register, configured to control the second multiplexer to select the one from K clock signals as the input signal of the nth cycle according to the integer in A2(n); wherein there exist positive integers q1 and f1, such that A1(q2) is always equal to A1(f2)(mod K), and f1 is greater than q1; and there exist positive integers q2 and f2, such that A2(q2) is always equal to A2(f2)(modK), and f2 is greater than q2.

[0014] In some embodiments, A2(1)=A1(1), A2(n)=A1(n), f1=q1, f2=q2.

[0015] In some embodiments, the control circuit is also configured to provide an initial value; and the first register and the second register are also configured to control the first multiplexer and the second multiplexer respectively according to the initial value to select the same one from K clock signals as the input signal of the first cycle.

[0016] In some embodiments, the control circuit is further configured to provide the same frequency.

[0017] In some embodiments, the first signal generating circuit is further configured to generate a first clock signal of the first cycle based on the control signal of the first cycle and the input signal of the first cycle; the second signal generating circuit is further configured to generate a second clock signal of the first cycle based on the control signal of the first cycle and the input signal of the first cycle; and the output circuit is further configured to output an output signal of the first cycle based on the first clock signal of the first cycle and the second clock signal of the first cycle.

[0018] In some embodiments, the cth rising edge of the first clock signal arrives at the output circuit at a first moment, and the cth rising edge of the second clock signal arrives at the output circuit at a second moment, where c is an integer greater than or equal to 1; and the output circuit is configured to determine the logic level of the output signal of the nth cycle based on at least the first moment and the second moment.

[0019] In some embodiments, the c+1th rising edge of the first clock signal arrives at the output circuit at a third moment, and the c+1th rising edge of the second clock signal arrives at the output circuit at a fourth moment; and the output circuit is configured to determine the logic level of the output signal of the nth cycle based on a first difference between the third moment and the first moment, and a second difference between the fourth moment and the second moment.

[0020] In some embodiments, when the first difference is greater than or equal to the second difference, the logic level of the output signal of the nth period is 1; when the first difference is less than the second difference, the logic level of the output signal of the nth period is 0.

[0021] In some embodiments, the probability that the logic level of the output signal is a first logic level is 0.5, and the probability that the logic level of the output signal is a second logic level is 0.5, and the first logic level and the second logic level are logically opposite.

[0022] According to another aspect of an embodiment of the present disclosure, there is provided an electronic device, comprising: a physical unclonable function device as described in any one of the above embodiments.

[0023] In some embodiments, the electronic device includes a display device.

[0024] According to another aspect of an embodiment of the present disclosure, there is provided an operation method of a physical unclonable function device, comprising: a control circuit processes an initial control signal of an nth period according to a reference value to obtain a control signal of an nth period, wherein the reference value includes a logic level of an output signal of an n-1th period, and n is an integer greater than or equal to 2; a first signal generating circuit generates a first clock signal of an nth period according to the control signal of the nth period and an input signal of the nth period; a second signal generating circuit generates a second clock signal of an nth period according to the control signal of the nth period and the input signal of the nth period; and an output circuit outputs an output signal of an nth period according to the first clock signal of the nth period and the second clock signal of the nth period.

[0025] According to another aspect of the embodiments of the present disclosure, there is provided an encryption method, comprising: encrypting data to be encrypted using the output signal of the physical unclonable function device described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0027] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0028] Figure 1 is a schematic diagram showing the structure of a PUF device according to an embodiment of the present disclosure;

[0029] Figure 2 is a schematic structural diagram showing a PUF device according to another embodiment of the present disclosure;

[0030] Figure 3A and Figure 3B The figure shows the change of the accumulated value of the accumulator under different conditions according to some embodiments of the present disclosure.

[0031] Figure 4 is a flow chart showing an operation method of a PUF device according to an embodiment of the present disclosure;

[0032] Figure 5A-5F Graph showing the distribution of recursive cycles according to some embodiments of the present disclosure.

[0033] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0035] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0037] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0038] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0039] Figure 1 FIG. 4 is a schematic diagram showing the structure of a PUF device according to an embodiment of the present disclosure.

[0040] like Figure 1 As shown, the PUF device includes a first signal generating circuit 11 , a second signal generating circuit 12 , an output circuit 13 and a control circuit 14 .

[0041] The first signal generating circuit 11 is configured to generate a first clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period. Here, n is an integer greater than or equal to 2. In some embodiments, the control signal includes a control word. It is understood that the control word can be an integer, or can include an integer part and a decimal part.

[0042] In some embodiments, the first signal generating circuit 11 includes a first TAF-DPS (Time-Average-Frequency Direct Period Synthesis) circuit 11. For example, the first TAF-DPS circuit selects one clock signal from a plurality of clock signals as an input signal of the nth period, and the input signal of the nth period is passed through a TFF (toglle Flip Flop) in the first TAF-DPS circuit to obtain a first clock signal of the nth period. For example, the first TAF-DPS circuit 11 selects one clock signal from a plurality of clock signals as an input signal of the nth period according to a control word of the nth period.

[0043] The second signal generating circuit 12 is configured to generate a second clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period.

[0044] In some embodiments, the second signal generating circuit 12 includes a second TAF-DPS circuit. Similarly, for example, the second TAF-DPS circuit selects one from a plurality of clock signals as an input signal of the nth cycle, and the input signal of the nth cycle is converted into a second clock signal of the nth cycle after passing through the TFF in the second TAF-DPS circuit 12.

[0045] The output circuit 13 is configured to output an output signal of the nth period according to the first clock signal of the nth period and the second clock signal of the nth period.

[0046] In some embodiments, the output circuit 13 can determine whether the logic level of the output signal of each cycle is 0 or 1 according to the moment when the first clock signal and the second clock signal arrive at the output circuit 13, which will be described in detail in combination with different implementations. It can be understood that the moment when the first clock signal of the nth cycle and the second clock signal of the nth cycle arrive at the output circuit 13 is unpredictable, so the logic level of the output signal is also unpredictable, that is, random.

[0047] The control circuit 14 is configured to process the initial control signal of the nth cycle according to the reference value to obtain the control signal of the nth cycle. Here, the reference value includes at least the logic level of the output signal of the n-1th cycle. In some embodiments, the probability that the logic level of the output signal is the first logic level is 0.5, and the probability that the logic level of the output signal is the second logic level is 0.5, and the first logic level and the second logic level are logically opposite. For example, the first logic level is 0, and the second logic level is 1; vice versa.

[0048] For example, the initial control signal is generated by the control circuit 14. It should be noted that the initial control signals of different periods may be the same or different. For example, the initial control signals of some periods are the same and different from the initial control signals of other periods. For another example, the initial control signals of all periods are the same, that is, the initial control signal does not change after it is generated once.

[0049] In some embodiments, the reference value only includes the logic level of the output signal of the n-1th cycle. In this case, the control circuit 14 processes the initial control signal of the nth cycle to obtain the control signal of the current cycle only according to the logic level of the output signal of the previous cycle.

[0050] In other embodiments, the reference value includes other values ​​in addition to the logic level of the output signal of the n-1th cycle, for example, the logic level of the output signal of the n-2th cycle, the logic level of the output signal of the n-3th cycle, etc. In this case, the control circuit 14 can process the initial control signal of the nth cycle according to the logic levels of the output signals of multiple cycles before the current cycle to obtain the control signal of the current cycle.

[0051] In some embodiments, the initial control signal includes an initial control word. For example, the processing of the initial control word of the nth cycle may include various mathematical operations, such as multiplication operations, addition operations, and the like.

[0052] In the above embodiment, the control circuit processes the initial control signal of the current cycle according to the reference value including the logic level of the output signal of the previous cycle to obtain the control signal of the current cycle. The logic level of the output signal of the PUF device is unpredictable. By introducing the logic level of the output signal of the previous cycle into the control signal of the current cycle, the unpredictability of the control signal of the current cycle is increased. In this way, the unpredictability of the first clock signal and the second clock signal generated based on the control signal of the current cycle is increased, thereby increasing the randomness and unpredictability of the output signal of the current cycle, and improving the security of the PUF device.

[0053] It should be understood that the first signal generating circuit 11 and the second signal generating circuit 12 can be implemented in different ways. In some embodiments, the first signal generating circuit 11 includes a first TAF-DPS circuit, and the second signal generating circuit 12 includes a second TAF-DPS circuit; accordingly, the control signal may include a control word, and the initial control signal may include an initial control word. Using a TAF-DPS circuit as a signal generating circuit can further increase the randomness and unpredictability of the output signal, and further improve the security of the PUF device.

[0054] Some implementations of processing the initial control word according to the reference value are introduced below in combination with different embodiments.

[0055] In some embodiments, the initial control word C=F+r, where F is an integer and r is a decimal greater than 0 and less than 1. The control word C(n) of the nth cycle is obtained by performing a mathematical operation on at least one of F and r and a reference value. Here, it can be understood that r can affect the cycle of the first clock signal and the second clock signal.

[0056] In some embodiments, each of the first clock signal and the second clock signal has a first period with probability r and a second period with probability 1-r, the first period is F+1, and the second period is F. The larger r is, the higher the proportion of the first period is.

[0057] As some implementations, the control word C(n) of the nth cycle is obtained by performing a mathematical operation on each of F and r and a reference value. In other words, the control word C(n) of the nth cycle is obtained by performing a mathematical operation on both F and r and a reference value.

[0058] As another implementation, the control word C(n) of the nth cycle is obtained by performing a mathematical operation on one of F and r and a reference value. For example, the control word C(n) of the nth cycle = M+N, where M is one of F and r, and N is obtained by performing a mathematical operation on the other of F and r and a reference value. In this way, the security of the PUF device can be increased with less overhead.

[0059] In some cases, the area occupied by the PUF device is limited. In some embodiments, in order to achieve greater security increase using the PUF device in a limited area, M is F, and N is obtained by mathematically calculating r and the reference value. In other words, the reference value affects the value of the decimal part of the initial control word without affecting the value of the integer part. In this way, the control circuit 14 can be implemented with a simple structure. On the one hand, the security of the PUF device can be improved; on the other hand, due to the simple structure, the area occupied by the control circuit 14 in the PUF device can be reduced, and the power consumption of the PUF device can be reduced.

[0060] In the case of the control word C(n)=F+N in the nth cycle, the above mathematical operation may include a multiplication operation. Some implementations of calculating N are given below.

[0061] In some implementations, In this case, the control word of the nth cycle here, is the logic level of the output signal in the n-1th cycle.

[0062] In other implementations, In this case, the control word of the nth cycle

[0063] Here, m is the number of digits after the decimal point in r, ri = 0.p, p is the last i digits in r, Indicates the logic level of the output signal of the nith cycle. In addition, when ni is less than or equal to 0, As an example, if r=0.125, then r1=0.5, r2=0.25, and r3=0.125.

[0064] In this way, the randomness and unpredictability of the output signal of the PUF device can be further improved, thereby further improving the security of the PUF device.

[0065] In some embodiments, when the control word C(n)=F+N in the nth cycle, r=0.5. In this way, the randomness and unpredictability of the output signal of the PUF device can be further improved, thereby further improving the security of the PUF device.

[0066] In some embodiments, each of the first TAF-DPS circuit 11 and the second TAF-DPS circuit 12 is configured to determine the input signal of the nth cycle according to the control word of the nth cycle. In this way, the control word of the nth cycle is random, so that the input signal of the nth cycle is also random.

[0067] Figure 2 FIG. 4 is a schematic diagram showing the structure of a physical unclonable function device according to another embodiment of the present disclosure.

[0068] and Figure 1 compared to, Figure 2The PUF device shown also includes a ring oscillator 15. In addition, the first signal generating circuit 11 includes a first TAF-DPS circuit, and the second signal generating circuit 11 includes a second TAF-DPS circuit. The first TAF-DPS circuit includes a first accumulator 111, a first multiplexer 112, and a first register 113, and the second TAF-DPS circuit includes a second accumulator 121, a second multiplexer 122, and a second register 123.

[0069] The ring oscillator 15 is configured to generate K clock signals with the same frequency, where K is an integer greater than or equal to 2. The jth clock signal and the j-1th clock signal have the same time interval, where j is any integer between 2 and K. For example, when K is 4, j can be 2, 3, and 4.

[0070] For example, the time interval between the first clock signal and the second clock signal, the time interval between the second clock signal and the third clock signal, ... and the time interval between the Kth clock signal and the K-1th clock signal are all the same. In some embodiments, the control circuit 14 is further configured to provide the same frequency. The ring oscillator 15 generates corresponding K clock signals according to the same frequency provided by the control circuit 14.

[0071] The first accumulator 111 is configured to calculate the accumulated value A1(n) of the nth cycle in the first accumulator 111 according to the following formula 1:

[0072] A1(n)=(A1(n-1)+C(n))(mod K)...(Formula 1).

[0073] Here, A1(n-1) is the accumulated value of the first accumulator 111 in the n-1th cycle. In some embodiments, the initial value of the accumulated value of the first accumulator 111 is 0, and the accumulated value A1(1) of the first cycle of the first accumulator 111 = the initial control word. For example, the control circuit 14 generates the initial control word and provides it to the first accumulator 111.

[0074] C(n) is the control word of the nth cycle, and C(n) is greater than or equal to 2 and less than or equal to 2K-1. C(n) can be determined in the various ways described above, which will not be described in detail here.

[0075] For Formula 1, there exist positive integers q1 and f1, such that A1(q1) is always equal to A1(f1)(mod K), and f1 is greater than q1. That is, f1 can be regarded as the recursive period of the chaotic recursive equation shown in Formula 1.

[0076] The first register 113 is configured to control the first multiplexer 112 to select one of the K clock signals as the input signal of the nth cycle according to the integer in A1(n). For example, the integer in A1(3) is 3, and the first multiplexer 112 can select the 4th clock signal as the input signal of the 3rd cycle.

[0077] The second accumulator 121 is configured to calculate the accumulated value A2(n) of the nth cycle in the second accumulator 121 according to the following formula 2:

[0078] A2(n)=(A2(n-1)+C(n))(mod K)…(Formula 2).

[0079] Here, A2(m-1) is the accumulated value of the n-1th cycle in the second accumulator 121. In some embodiments, the initial value of the accumulated value in the second accumulator 121 is 0, and the accumulated value of the first cycle in the second accumulator 111 A2(1)=A1(1)=initial control word.

[0080] Similarly, for Formula 2, there exist positive integers q2 and f2 such that A2(q2) is always equal to A2(f2)(mod K). f2 can be regarded as the recursive period of the chaotic recursive equation shown in Formula 2.

[0081] The second register 123 is configured to control the second multiplexer 122 to select one of the K clock signals as the input signal of the nth cycle according to the integer in A2(n). In some embodiments, the clock signal selected by the second multiplexer 122 is the same as the clock signal selected by the first multiplexer 112.

[0082] In the above embodiment, since the logic level of the output signal of the previous cycle is random, the control word of the current cycle is also random, so that the accumulated values ​​in the first accumulator and the second accumulator are random, and then the clock signals selected by the first multiplexer and the second multiplexer are random, and finally the first clock signal and the second clock signal are also random, which increases the randomness and unpredictability of the output signal and improves the security of the PUF device.

[0083] In some embodiments, A2(1)=A1(1), A2(n)=A1(n), q2=q1, f2=f1. In this case, for each cycle, the accumulated values ​​in the first accumulator 111 and the second accumulator 121 are the same, so that the recursive cycles of the chaotic recursive equations shown in Formula 1 and Formula 2 are the same. In this way, the clock signal selected by the second multiplexer 122 is the same as the clock signal selected by the first multiplexer 112, so that the logic level of the output signal output by the PUF device based on the same input signal is more random, which can further improve the randomness of the output signal of the PUF output device, thereby further improving the security of the PUF device.

[0084] In some embodiments, the control circuit 14 is further configured to provide an initial value; the first register 113 and the second register 123 are further configured to control the first multiplexer 112 and the second multiplexer 122 to select the same clock signal from the K clock signals as the input signal of the first cycle according to the initial value provided by the control circuit 14. It should be understood that the first register 113 is configured to control the first multiplexer 112 to select the clock signal from the K clock signals as the input signal of the first cycle according to the initial value provided by the control circuit 14, and the second register 123 is configured to control the second multiplexer 122 to select the clock signal from the K clock signals as the input signal of the first cycle according to the initial value provided by the control circuit 14.

[0085] It should be noted that the initial value here can be set according to actual conditions. For example, the initial value is 1, and each of the first multiplexer 112 and the second multiplexer 122 can select the second clock signal as the input signal of the first cycle.

[0086] In some embodiments, the first signal generating circuit 11 is further configured to generate a first clock signal of the first cycle according to the control signal of the first cycle and the input signal of the first cycle; the second signal generating circuit 12 is further configured to generate a second clock signal of the first cycle according to the control signal of the first cycle and the input signal of the first cycle; the output circuit 13 is further configured to output an output signal of the first cycle according to the first clock signal of the first cycle and the second clock signal of the first cycle. For example, the control word of the first cycle is the initial control word generated by the control circuit 14.

[0087] Figure 3A and Figure 3BThe figure shows the change of the accumulated value of the control word in the first accumulator and the second accumulator under different conditions according to some embodiments of the present disclosure. Here, it is assumed that the accumulated value of the control word in the first accumulator and the second accumulator is the same, the number of clock signals K=32, the integer of the initial control word F=42, and the initial value provided by the control circuit 14 is 0.

[0088] Figure 3A and Figure 3B The horizontal coordinate corresponding to the position of each arrow is the accumulated value of the current cycle, and the vertical coordinate corresponding to the position of each arrow is the accumulated value of the next cycle.

[0089] exist Figure 3A In the case shown, the initial control word is not processed according to the reference value, and the accumulated value is the same each time. Figure 3A It can be seen that the change of the accumulated value is regular. When the accumulated value returns to the initial value 0, according to Figure 3A The pattern shown changes cyclically, but the period is fixed.

[0090] exist Figure 3B In the case shown, the initial control word is processed according to the reference value, and the value accumulated each time is random. Figure 3B It can be seen that the change of the accumulated value is random, the change is more complex, and the cycle is no longer fixed. The accumulated value (diamond point) entering the cycle is not necessarily the initial value 0.

[0091] Through the above comparative analysis, it can be seen that, with the PUF device using the embodiment of the present disclosure, the response to the stimulation of the control word becomes more unpredictable, and the complexity and randomness are improved.

[0092] It should be noted that Figure 1 and Figure 2 The output circuit 13 in the embodiment can be realized by different structures, such as a D flip-flop, a bang-bang frequency detector, etc. It is understandable that, due to process deviation, for the same input signal, the first clock signal and the second clock signal obtained after being processed by the first TAF-DPS 11 and the second TAF-DPS 12 having the same structure may arrive at the output circuit 13 at different times, and therefore, the output circuit 13 can be encoded accordingly.

[0093] The following describes the implementation manner in which the output circuit 13 determines the logic level of the output signal of the nth cycle in conjunction with some embodiments.

[0094] In some embodiments, the cth rising edge of the first clock signal reaches the output circuit 13 at a first moment, and the cth rising edge of the second clock signal reaches the output circuit 13 at a second moment, where c is an integer greater than or equal to 1. In this case, the output circuit 13 is configured to determine the logic level of the output signal of the nth cycle based on at least the first moment and the second moment. For example, the output circuit 13 may include a D flip-flop.

[0095] For example, if the difference between the second moment and the first moment is greater than or equal to 0, the logic level of the output signal of the nth cycle is 1; if the difference between the second moment and the first moment is less than 0, the logic level of the output signal of the nth cycle is 0.

[0096] In some other embodiments, the cth rising edge of the first clock signal reaches the output circuit 13 at the first moment, the cth rising edge of the second clock signal reaches the output circuit 13 at the second moment, the c+1th rising edge of the first clock signal reaches the output circuit 13 at the third moment, and the c+1th rising edge of the second clock signal reaches the output circuit 13 at the fourth moment. In this case, the output circuit 13 is configured to determine the logic level of the output signal of the nth cycle according to the first difference between the third moment and the first moment, and the second difference between the fourth moment and the second moment. For example, the output circuit 13 may include a bang-bang frequency discriminator.

[0097] For example, when the first difference is greater than or equal to the second difference, the logic level of the output signal of the nth period is 1; when the first difference is less than the second difference, the logic level of the output signal of the nth period is 0.

[0098] It should be understood that the above encoding method is not restrictive, and the output circuit 14 can also be encoded according to other methods, which are not listed here.

[0099] Figure 4 FIG. 2 is a diagram illustrating an operation method of a PUF device according to some embodiments of the present disclosure.

[0100] In step 402, the control circuit processes the initial control signal of the nth cycle according to the reference value to obtain the control signal of the nth cycle. Here, the reference value includes the logic level of the output signal of the n-1th cycle, and n is an integer greater than or equal to 2.

[0101] In step 404 , the first signal generating circuit generates a first clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period.

[0102] In step 406 , the second signal generating circuit generates a second clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period.

[0103] In step 408 , the output circuit outputs an output signal of the nth period according to the first clock signal of the nth period and the second clock signal of the nth period.

[0104] It should be understood that the PUF device can be operated in the manner described above, which will not be described in detail here.

[0105] In the above embodiment, the control circuit processes the initial control signal of the current cycle according to the reference value including the logic level of the output signal of the previous cycle to obtain the control signal of the current cycle. The logic level of the output signal of the PUF device is unpredictable. By introducing the logic level of the output signal of the previous cycle into the control signal of the current cycle, the unpredictability of the control signal of the current cycle is increased. In this way, the unpredictability of the first clock signal and the second clock signal generated based on the control signal of the current cycle is increased, thereby increasing the randomness and unpredictability of the output signal of the current cycle, and improving the security of the PUF device.

[0106] The embodiment of the present disclosure also provides an encryption method, including: using the output signal of the PUF device of any of the above embodiments to encrypt the data to be encrypted. Here, the data to be encrypted can be any data to be encrypted. For example, the output signal of the PUF device can be used as a key to encrypt the data to be encrypted.

[0107] The disclosed embodiments further provide an electronic device, including: a physical unclonable function device of any of the above embodiments. In some embodiments, the electronic device includes a display device. For example, the display device can be any product or component with a display function, such as a mobile terminal, an Internet of Things terminal, a television, a display, a laptop, a digital photo frame, a navigator, or an electronic paper.

[0108] Some examples are given below to illustrate the changes in the recursive period f of the above-mentioned Formula 1 and Formula 2.

[0109] Table 1 shows the distribution of the recursive period f of Formula 1 and Formula 2 when the number K of clock signals is 4, the decimal part of the initial control word is 0.5, and the integer part F of the initial control word is 2 to 7.

[0110] Table 1

[0111]

[0112]

[0113] Figure 5A-5F: is a diagram showing the distribution of recursive cycles according to some embodiments of the present disclosure. In these embodiments, the number of clock signals K is 32, the fractional part of the initial control word is 0.5, and the integer part F of the initial control word corresponds to Figure 5A-5F 2 to 7 respectively.

[0114] exist Figure 5A-5F In the figure, the horizontal axis represents the recursive period f, and the vertical axis represents the probability that the recursive period f is the corresponding value.

[0115] From Table 1, and Figure 5A-5F It can be seen that when F has different values, the recursive period f changes randomly rather than being a fixed value.

[0116] In practical applications, the complexity of the recursive period f can be adjusted by adjusting the value of r. For example, the output signal of the PUF device consists of K bits as the key. When the recursive period f satisfies , the PUF device can be considered secure.

[0117] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0118] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A physically unclonable function device, comprising: a first signal generating circuit configured to generate a first clock signal of an nth period according to a control signal of an nth period and an input signal of an nth period, where n is an integer greater than or equal to 2; a second signal generating circuit configured to generate a second clock signal of an nth period according to a control signal of an nth period and an input signal of an nth period; an output circuit configured to output an output signal of an nth period according to a first clock signal of an nth period and a second clock signal of an nth period, wherein a logic level of the output signal of the nth period is determined according to a time when the first clock signal and the second clock signal arrive at the output circuit; and The control circuit is configured to process the initial control signal of the nth cycle according to a reference value to obtain the control signal of the nth cycle, wherein the reference value includes the logic level of the output signal of the (n-1)th cycle.

2. The physically unclonable function device according to claim 1, wherein: The first signal generating circuit includes a first time average frequency direct period synthesis TAF-DPS circuit, and the second signal generating circuit includes a second TAF-DPS circuit; The control signal includes a control word, and the initial control signal includes an initial control word.

3. The physically unclonable function device according to claim 2, wherein: The initial control word C=F+r, wherein F is an integer and r is a decimal greater than 0 and less than 1; The control word C(n) of the nth cycle is obtained by performing a mathematical operation on at least one of F and r and the reference value.

4. The physical unclonable function device according to claim 3, wherein: Each of the first clock signal and the second clock signal has a first period with a probability of r and a second period with a probability of 1-r, the first period is F+1, and the second period is F.

5. The physical unclonable function device according to claim 3, wherein: C(n)=M+N, wherein M is one of F and r, and N is obtained by performing a mathematical operation on the other of F and r and the reference value.

6. The physical unclonable function device according to claim 5, wherein: M is F, and N is obtained by performing a mathematical operation on r and the reference value.

7. The physical unclonable function device according to claim 6, wherein: The mathematical operation includes a multiplication operation.

8. The physically unclonable function device according to claim 7, wherein: m is the number of digits after the decimal point in r, ri = 0.p, p is the last i digits in r, Represents the logic level of the output signal of the ni-th cycle; When ni is less than or equal to 0, 9. The physical unclonable function device according to any one of claims 3 to 8, wherein: r＝0.5。 10. The physical unclonable function device according to any one of claims 2 to 8, wherein: Each of the first TAF-DPS circuit and the second TAF-DPS circuit is configured to determine an input signal of an n-th cycle according to a control word of the n-th cycle.

11. The physical unclonable function device according to claim 10, further comprising: A ring oscillator is configured to generate K clock signals having the same frequency, wherein the j-th clock signal and the j-1-th clock signal have the same time interval, K is an integer greater than or equal to 2, and j is any integer between 2 and K; The first TAF-DPS circuit comprises: A first accumulator is configured to calculate an accumulated value A1(n) of the nth cycle in the first accumulator according to the following formula: A1(n)=(A1(n-1)+C(n))(mod K), wherein A1(n-1) is the accumulated value of the n-1th cycle in the first accumulator, C(n) is the control word of the nth cycle, and C(n) is greater than or equal to 2 and less than or equal to 2K-1; a first multiplexer; and A first register is configured to control the first multiplexer to select one of the K clock signals as the input signal of the nth cycle according to the integer in A1(n); and The second TAF-DPS circuit comprises: A second accumulator is configured to calculate an accumulated value A2(n) of the nth cycle in the second accumulator according to the following formula: A2(n)=(A2(n-1)+C(n))(mod K), wherein A2(n-1) is the accumulated value of the n-1th cycle in the second accumulator, A2(1)=A1(1), A2(n)=A1(n); a second multiplexer; and A second register is configured to control the second multiplexer to select the one from the K clock signals as the input signal of the nth cycle according to the integer in A2(n); where there exist positive integers q1 and f1 such that A1(q1) is always equal to A1(f1)(mod K), and f1 is greater than q1; and There exist positive integers q2 and f2 such that A2(q2) is always equal to A2(f2)(mod K), f2 is greater than q2.

12. The physical unclonable function device according to claim 11, wherein: A2(1)=A1(1), A2(n)=A1(n), f1=q1, f2=q2.

13. The physical unclonable function device according to claim 12, wherein: The control circuit is further configured to provide an initial value; and The first register and the second register are further configured to control the first multiplexer and the second multiplexer respectively to select the same one from the K clock signals as the input signal of the first cycle according to the initial value.

14. The physical unclonable function device according to claim 12, wherein: The control circuit is further configured to provide the same frequency.

15. The physically unclonable function device according to any one of claims 1 to 8, wherein: The first signal generating circuit is further configured to generate a first clock signal of the first cycle according to the control signal of the first cycle and the input signal of the first cycle; The second signal generating circuit is further configured to generate a second clock signal of the first cycle according to the control signal of the first cycle and the input signal of the first cycle; and The output circuit is further configured to output an output signal of the first cycle according to the first clock signal of the first cycle and the second clock signal of the first cycle.

16. The physical unclonable function device according to any one of claims 1 to 8, wherein: The cth rising edge of the first clock signal reaches the output circuit at a first moment, and the cth rising edge of the second clock signal reaches the output circuit at a second moment, where c is an integer greater than or equal to 1; and The output circuit is configured to determine a logic level of an output signal of an nth period according to at least the first time and the second time.

17. The physical unclonable function device according to claim 16, wherein: The c+1th rising edge of the first clock signal reaches the output circuit at a third time, and the c+1th rising edge of the second clock signal reaches the output circuit at a fourth time; and The output circuit is configured to determine a logic level of an output signal of the nth period according to a first difference between the third time and the first time and a second difference between the fourth time and the second time.

18. The physical unclonable function device according to claim 17, wherein: When the first difference is greater than or equal to the second difference, the logic level of the output signal of the nth period is 1; When the first difference is smaller than the second difference, the logic level of the output signal in the nth period is 0.

19. The physical unclonable function device according to claim 1, wherein: The probability that the logic level of the output signal is a first logic level is 0.5, and the probability that the logic level of the output signal is a second logic level is 0.5, and the first logic level and the second logic level are logically opposite.

20. An electronic device, comprising: A physically unclonable function device as claimed in any one of claims 1 to 19.

21. The electronic device according to claim 20, wherein: The electronic device includes a display device.

22. A method for operating a physically unclonable function device, comprising: The control circuit processes the initial control signal of the nth cycle according to the reference value to obtain the control signal of the nth cycle, wherein the reference value includes the logic level of the output signal of the n-1th cycle, and n is an integer greater than or equal to 2; The first signal generating circuit generates a first clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period; The second signal generating circuit generates a second clock signal of the nth period according to the control signal of the nth period and the input signal of the nth period; and The output circuit outputs an output signal of the nth period according to the first clock signal of the nth period and the second clock signal of the nth period, wherein the logic level of the output signal of the nth period is determined according to the time when the first clock signal and the second clock signal arrive at the output circuit.

23. An encryption method comprising: The data to be encrypted is encrypted using the output signal of the physical unclonable function device as described in any one of claims 1 to 19.

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