An aero-engine rotating speed adaptive dynamic measurement method

Abstract

The application discloses an aero-engine rotating speed adaptive dynamic measurement method, which comprises the following steps: after a rotating speed signal is processed, the signal is sent to a programmable logic device; the programmable logic device counts the complete pulses of a system clock in a half cycle time window of the measured rotating speed signal and saves the count value N0; according to the count value N0, an adaptive dynamic optimization method is used to determine the multiple m between the gate time and the period of the measured rotating speed signal; the programmable logic device counts the complete pulses of the system clock in a time window of m periods of the measured rotating speed signal and saves the count value N1; a CPU accesses the programmable logic device through a bus and reads the count value N1, and according to the frequency of the system clock, the size of the gate time T w is determined; and the rotating speed of the engine is calculated according to the gate time and the number of gear teeth. The application can realize adaptive dynamic measurement of the rotating speed, so the rotating speed is suitable for a wide range, the programmable logic device is used to collect the rotating speed, the CPU is used to calculate the rotating speed, the system has a fast response, the measurement precision is high, and the reliability is good.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of aero-engine speed adaptive dynamic measurement method, it belongs to aero-engine control field. BACKGROUND

[0002] Speed is extremely important physical quantity in aero-engine, characterizes the engine thrust and working stability information, etc., and its accurate and reliable acquisition is the basic requirement to ensure the safe and reliable operation of engine.Currently commonly used speed measurement method includes two kinds of periodic measurement method and frequency measurement method, but since periodic measurement method is not suitable for high speed condition, frequency measurement method is not suitable for low speed condition, simultaneously aero-engine speed range is wide, change fast, therefore the above two methods cannot meet the demand of aero-engine distributed control system to speed high precision, fast measurement. SUMMARY

[0003] Therefore, the present application aims to provide a kind of aero-engine speed adaptive dynamic measurement method, compared with traditional speed measurement method, the method of the present application is high, low speed under both have the advantages of high acquisition precision, fast response, flexibility etc.

[0004] The present application adopts the following technical scheme:

[0005] A kind of aero-engine speed adaptive dynamic measurement method, the method includes the following steps:

[0006] Step A, speed signal is sent to programmable logic device after being conditioned by signal processing circuit;

[0007] Step A, the speed signal is sent to programmable logic device after being conditioned by signal processing circuit, from sine signal to frequency same standard square wave signal.

[0008] Step B, programmable logic device is in the half cycle time window of measured speed signal, the complete pulse of system clock is counted and the count value is saved, and is recorded as N0;

[0009] Further, step B includes:

[0010] a. system reset signal is generated using system clock and reset register, all data registers in programmable logic end are zero during reset, and keep readable and non-writable state;

[0011] b. system number signal is generated using system clock and number register, all data registers in programmable logic end become readable and writable state when system jumps out of reset state;

[0012] c. In the first half cycle time window of the measured rotational speed signal, the programmable logic counts the complete pulses of the system clock and saves the result in the clock count register 0, denoted as N0.

[0013] The first half cycle of the measured rotational speed signal in step c refers to the time period of the first measured signal rising edge and falling edge in each rotational speed measurement time period.

[0014] Step C, the programmable logic device divides N0 by an integer in the second half cycle time window of the measured rotational speed signal, and keeps the integer part of the quotient, denoted as m0.

[0015] Step C, the programmable logic device divides N0 by an integer in the second half cycle time window of the measured rotational speed signal, and keeps the integer part of the quotient, denoted as m0.

[0016]

[0017] Where [·] represents the floor function, and K represents an integer, the value of which is determined by the following formula

[0018]

[0019] Where f c is the system clock frequency.

[0020] The second half cycle of the measured rotational speed signal in step C refers to the time period of the first measured signal falling edge and the second measured signal rising edge in each rotational speed measurement time period.

[0021] Step D, the programmable logic device determines the value of m in the second half cycle time window of the measured rotational speed signal after judging the value of m0.

[0022] Step D, the programmable logic device determines the value of m in the second half cycle time window of the measured rotational speed signal after judging the value of m0.

[0023]

[0024] Step E, the programmable logic device counts the complete pulses of the system clock in the m cycle time window of the measured rotational speed signal and saves the count value, denoted as N1.

[0025] Further, step E includes:

[0026] a. In the programmable logic device, create a system synchronization register to synchronize the measured rotational speed signal and the system clock signal.

[0027] b. In the number period time window of m measured rotating speed, the counter counts the complete pulse of system clock and saves the counter result into clock counting register 1, recorded as N1.

[0028] F. CPU accesses programmable logic device through bus and reads the counting value N1, calculates the gate time T w according to the system clock frequency

[0029] Further, step F includes:

[0030] a. CPU times every 10 milliseconds to access clock counting register 1 in programmable logic device end, reads the counting value in the register;

[0031] b. CPU end calculates the gate time T w

[0032]

[0033] G. CPU further calculates the rotating speed of engine according to gate time T w , gear tooth number Z and the multiple optimization value m of measured rotating speed signal period according to the following formula

[0034]

[0035] Wherein, Z is the gear tooth number of engine, n is the rotating speed of engine.

[0036] The present application provides a kind of aviation engine rotating speed adaptive dynamic measurement method, compared with the existing rotating speed measurement method, the present application has the following advantages:

[0037] (1) the present application can be applicable at high and low rotating speed, and the rotating speed measurement precision is extremely high.

[0038] (2) the present application is programmable logic device to collect rotating speed, CPU accesses the register in programmable logic device through bus mode to calculate the rotating speed value, this method separates rotating speed collection and calculation, does not occupy the resource of the other party, system reliability is high, response is fast and the calculation precision is high. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is the flow chart of the aviation engine rotating speed adaptive dynamic measurement method of the present application;

[0040] Figure 2 is the 50Hz measured signal simulation timing diagram based on the method of the present application;

[0041] Figure 3 is the 180Hz measured signal simulation timing diagram based on the method of the present application;

[0042] Figure 4 is the simulation timing diagram of the 8000Hz measured signal based on the method of the application. DETAILED DESCRIPTION

[0043] The technical solutions of the application will be described in detail below with reference to the drawings:

[0044] Figure 1 is the flowchart of the adaptive dynamic measurement method of the aero-engine speed of the application. The entire speed measurement process can be divided into three steps from a macro perspective. Step 1 is to determine the value of N0 by using the periodic measurement method. It is worth noting that the calculation is performed in the time window of half of the measured signal period. Step 2 is to determine the value of m, that is, to determine the gate time in the actual speed measurement process. Step 3 is the actual speed measurement process. This process determines the actual speed value by solving the number of pulses of the system clock in the gate time, thereby determining the value of the gate time.

[0045] Figure 2 is the simulation timing diagram of the 50Hz measured signal based on the adaptive dynamic measurement method of the aero-engine speed of the application.

[0046] clk_fs is the system clock signal, which is set to 50MHz in the simulation;

[0047] clk_fx is the measured signal, which is set to 50Hz in this simulation;

[0048] rst_n is the system reset signal;

[0049] fre is the simulation result of the measured signal;

[0050] cnt_fx is the reference clock counter in half of the period of the measured signal;

[0051] GATE_TIME is the gate time,

[0052] able is the enable signal;

[0053] gate_fx is the gate signal in the domain of the measured signal;

[0054] gate_fs is the gate signal synchronized to the system clock;

[0055] gate_fs_r is the register for synchronizing the gate signal;

[0056] gate_fs_d0 is the falling edge of the gate signal under the system clock for acquisition;

[0057] gate_fs_d1 is the falling edge of the gate signal under the system clock for acquisition;

[0058] gate_fx_d0 is the falling edge of the measured signal gate signal;

[0059] gate_fx_d1 is the falling edge of the measured signal gate signal;

[0060] gate_cnt is the counter of the gate signal;

[0061] fs_cnt is the reference clock counter within the gate time;

[0062] fs_cnt_temp is the temporary storage of the reference clock counter within the gate time;

[0063] fx_cnt is the measured signal counter within the gate time;

[0064] fx_cnt_temp is the temporary storage of the measured signal counter within the gate time;

[0065] busy is the CPU access register enable signal;

[0066] neg_gate_fs is the falling edge of the system clock gate signal;

[0067] neg_gate_fx is the falling edge of the measured signal gate signal;

[0068] During the system simulation, the reset register rst_n is set to 0, at this time all the count registers in the system are cleared and remain in the read-only state. The system remains in this state for 20 system clock cycles, after which the reset register rst_n is set to 1, at this time the system exits the reset state, and all registers in the system become readable and writable.

[0069] After the system exits the reset state, when the programmable logic end detects the first rising edge of the measured signal, the counter cnt_fx enters the enable counting state, and the counter is triggered to count the value plus one at each rising edge of the system clock. When the programmable logic end detects the first falling edge of the measured signal, the counter cnt_fx enters the stop counting state, and the count value in the counter cnt_fx at this time is N0, and the value of N0 in this simulation is 500000.

[0070] After the programmable logic end detects the first falling edge of the measured signal, the system calculates the following formula

[0071]

[0072] In this simulation, the value of K is 2500000, the calculated m0 value is saved to the GATE_TIME register, and m0 is the initial value of the gate time. In this simulation, the calculated value of m0 is 2.

[0073] After detecting the second rising edge of the measured signal, the programmable logic end triggers the system to determine the value of m in the GATE_TIME register according to the following formula

[0074]

[0075] The value of m is determined to be 3. At the same time, the gate_fx signal is pulled high to 1, indicating that the programmable logic end has entered the speed measurement phase. The counters gate_cnt and fx_cnt_temp enter the allowed counting state, and the value of the counter is incremented by 1 at each rising edge of the measured signal.

[0076] After that, at the first rising edge of the system clock, the gate_fs_r signal is pulled high to 1; at the second rising edge of the system clock, the gate_fs signal is pulled high to 1. This step uses the direct latching method to synchronize the gate signal in the measured signal domain to the system clock. At the same time, the counter fs_cnt_temp enters the allowed counting state, and the value of the counter is incremented by 1 at each rising edge of the system clock.

[0077] The system maintains the above state, and the counters gate_cnt, fx_cnt_temp and fs_cnt_temp operate synchronously until the gate time ends, i.e. after 3 periods of the measured signal.

[0078] At the 5th rising edge of the measured signal, i.e. at the node where the counter gate_cnt jumps from 3 to 4, the cnt_fx signal is pulled low to 0, indicating that the programmable logic end has ended the speed measurement phase and entered the speed calculation phase. After that, the counter fx_cnt_temp stops counting, and at the first rising edge of the system clock, the cnt_fs_r signal is pulled low to 0; at the second rising edge of the system clock, the cnt_fs signal is pulled low to 0, and at the same time the counter fs_cnt_temp stops counting, and the value of the counter is n1. In this simulation, the value is 3000000.

[0079] The registers gate_fs_do and gate_fs_d1 are used to capture the falling edge of the system clock gated signal gate_fs after the gating time ends, and connect the signal to the neg_gate_fs register. When the system detects the falling edge of the neg_gate_fs register, the value in the counter fs_cnt_temp is saved to the fs_cnt register. The registers gate_fx_do and gate_fx_d1 are used to capture the falling edge of the measured signal gated signal gate_fx after the gating time ends, and connect the signal to the neg_gate_fx register. When the system detects the falling edge of the neg_gate_fx register, the value in the counter fx_cnt_temp is saved to the fx_cnt register.

[0080] When the system detects the falling edge of the neg_gate_fx register, the gating time T is calculated according to the following formula w

[0081]

[0082] At the rising edge of the next system clock, the system is triggered to calculate the engine speed according to the following formula

[0083]

[0084] In this simulation, the engine upper sound wheel is selected as 30 teeth, that is, z is equal to 30, and the related symbols in the above description are substituted with specific numerical values. The simulation theoretical result is 50 Hz, which is consistent with the simulation result.

[0085] Figure 3 and Figure 4 are the timing diagrams of the 180 Hz and 3000 Hz measured signals simulated based on the adaptive dynamic measurement method of the engine speed of the aircraft engine of the present application. The simulation specific process is the same as that of Figure 2 , and will not be repeated here.

Claims

1. An adaptive dynamic method of measuring the speed of an aeroengine, characterized in that, The method comprises: A. The rotational speed signal is sent to the programmable logic device after being conditioned by the signal processing circuit; B. The programmable logic device counts the complete pulses of the system clock in the first half cycle time window of the measured rotational speed signal and saves the count value, which is denoted as N0; C. The programmable logic device divides the integer K by 2N0 in the second half cycle time window of the measured rotational speed signal, retains the integer part of the quotient, and obtains the initial value of the multiple of the gating time and the period of the measured rotational speed signal, which is denoted as m0; D. The programmable logic device determines the optimized value of the multiple of the gating time and the period of the measured rotational speed signal according to the size of m0 in the second half cycle time window of the measured rotational speed signal by using the adaptive dynamic optimization method, which is denoted as m; E. The programmable logic device counts the complete pulses of the system clock in the m cycle time window of the measured rotational speed signal and saves the count value, which is denoted as N1; F. The CPU accesses the programmable logic device through the bus and reads the count value N1, determines the size of the gate time T according to the frequency of the system clock; w ; G. The CPU calculates the engine speed n based on the gate time T w , the number of teeth Z of the sound wheel, and the optimized value m of the multiple of the period of the measured speed signal. Step B comprises: a. A system reset signal is generated by using the system clock and the reset register, all data registers in the programmable logic end are cleared to zero during the reset period, and the data registers remain in the read-only and write-protected state; b. A system number setting signal is generated by using the system clock and the number setting register, all data registers in the programmable logic end become readable and writable after the system jumps out of the reset state; c. In the first half cycle time window of the measured rotational speed signal, a counter is used to count the complete pulses of the system clock in the programmable logic end, and the result of the counter is saved to the clock count register 0, which is denoted as N0; Step C specifies that the programmable logic device is in the second half cycle time window of the measured rotational speed signal, and the programmable logic device is triggered at the rising edge of the first system clock to calculate the following formula Wherein, [·] represents rounding down, K represents an integer, and the value of K is determined by the following formula wherein f c is the system clock frequency; Step D specifies that the programmable logic device is in the second half cycle time window of the measured rotational speed signal, and the programmable logic device is triggered at the rising edge of the second system clock to determine the value of m according to the size of m0 after the rising edge of the first system clock is triggered, according to the following formula Step E comprises: a. A system synchronization register is created in the programmable logic device to synchronize the measured rotational speed signal and the system clock signal; b. In the time window determined by m cycles of the measured rotational speed signal, a counter is used to count the complete pulses of the system clock, and the result of the counter is saved to the clock count register 1, which is denoted as N1; Step G specifies that the CPU further calculates the rotational speed of the engine according to the following formula Wherein, Z is the number of engine wheel teeth, and n is the rotational speed of the engine.

2. The method of claim 1, wherein, Step A specifies that the rotational speed signal is sent to the programmable logic device after being conditioned by the signal processing circuit, and the rotational speed signal is changed from a sine signal to a standard square wave signal with the same frequency.

3. The method of claim 1, wherein, The first half cycle of the measured rotational speed signal refers to the time period of the rising edge and the falling edge of the first measured signal in each rotational speed measurement time period.

4. The method of claim 1, wherein, The second half cycle of the measured rotational speed signal refers to the time period of the falling edge of the first measured signal and the rising edge of the second measured signal in each rotational speed measurement time period.

5. The method of claim 1, wherein, Step F comprises: a. The CPU times every 10 milliseconds to access the count register 1 in the programmable logic device and read the count value in the register; b.The CPU calculates the gate time T according to the following equation w the size of where f c is the system clock frequency.

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