Hardware accelerated k-mer graph generation

Abstract

Methods, systems, and apparatus for hardware-accelerated generation of K-mer graphs using programmable logic devices are provided.SOLUTION: In one aspect, a method includes acts of obtaining a first set of nucleic acid sequences, generating, using the obtained first set of nucleic acid sequences, a K-mer graph using a plurality of non-pipelined hardware logic units of a programmable logic device, and periodically updating, using a control machine, graph description data for the K-mer graph after execution of one or more operations by each hardware logic unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 006,668, filed April 7, 2020, the entire contents of which are incorporated herein by reference in their entirety. [Background technology]

[0002] A K-mer graph can be used to represent multiple sequencing reads. Summary of the Invention [Means for solving the problem]

[0003] According to one innovative aspect of the present disclosure, a method for hardware-accelerated generation of a K-mer graph using a programmable logic device is disclosed. In one aspect, the method includes: an operation of obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; and an operation of generating a K-mer graph using the obtained first set of nucleic acid sequences using a plurality of non-pipelined hardware logic units of the programmable logic device, each hardware logic unit comprising a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph is determined by the pair of K-mers. and during generation of the K-mer graph, using a control machine, periodically updating graph description data of the K-mer graph after execution of one or more operations by each hardware logic unit used to generate at least a portion of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, and wherein the control machine triggers execution of the one or more operations of each respective hardware logic unit during generation of the K-mer graph, thereby creating a workflow of operations using the non-pipelined hardware logic units.

[0004] Other versions include corresponding systems and apparatus configured to perform the operations of the aforementioned methods defined by the hardware logic circuitry of a hardware accelerated graph generation unit.

[0005] These and other versions may optionally include one or more of the following features: For example, in some implementations, the output of each hardware logic unit of the plurality of hardware logic units is stored via a hash table cache.

[0006] In some implementations, the control machine is implemented using hardware logic units of a programmable logic device.

[0007] In some implementations, the control machine is implemented using one or more CPUs or GPUs to execute software instructions to realize the functions of the control machine.

[0008] In some implementations, the operation may further include providing the generated K-mer graph to a variant calling unit, where the variant calling unit processes the K-mer graph to determine candidate variants between one or more of the plurality of reads and the reference sequence.

[0009] In some implementations, the software instructions may be executed by one or more CPUs or GPUs to implement one or more functions of the variant calling unit.

[0010] In some implementations, a programmable logic device is used to accelerate one or more functions of the variant calling unit.

[0011] In some implementations, the graph description data further includes (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0012] According to another innovative aspect of the present disclosure, a system for hardware-accelerated generation of K-mer graphs using a programmable logic device is disclosed. In one aspect, the system may include a hardware-accelerated graph generation unit including hardware digital logic circuitry configured to perform an operation. In some implementations, the operation includes obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence; and generating a K-mer graph using the obtained first set of nucleic acid sequences using multiple non-pipelined hardware logic units of the programmable logic device, each hardware logic unit comprising a different hardware logic circuitry configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a link between the pair of K-mers. and during generation of the K-mer graph, using a control machine, periodically updating graph description data of the K-mer graph after execution of one or more operations by each hardware logic unit used to generate at least a portion of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, and the control machine triggers execution of the one or more operations of each respective hardware logic unit during generation of the K-mer graph, thereby creating a workflow of operations using the non-pipelined hardware logic units.

[0013] Other versions include corresponding methods and apparatus for performing the above operations.

[0014] These and other versions may optionally include one or more of the following features: For example, in some implementations, the output of each hardware logic unit of the plurality of hardware logic units is stored via a hash table cache.

[0015] In some implementations, the operation may further include providing the generated K-mer graph to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more of the plurality of reads and the reference sequence.

[0016] In some implementations, the system may further include one or more computers and one or more memory devices storing instructions that, when executed by the one or more computers, cause the one or more computers to perform a second operation of the variant calling unit. In some implementations, the second operation of the variant calling unit may include obtaining, by the variant calling unit, the generated K-mer graph and identifying one or more candidate variants based on the variant calling unit processing the generated K-mer graph, where the candidate variants are differences between base calls of one or more reads in the pileup of reads and a nucleotide of the reference genome at a particular position in the reference genome.

[0017] In some implementations, the operation may further include obtaining, by a variant calling unit, the generated K-mer graph, and identifying one or more candidate variants based on the variant calling unit processing the generated K-mer graph, where the candidate variants are differences between base calls of one or more reads in the pileup of reads and nucleotides of the reference genome at particular positions in the reference genome.

[0018] In some implementations, the graph description data may further include (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0019] According to another innovative aspect of the present disclosure, a hardware-accelerated graph generation unit is disclosed. In one aspect, the hardware-accelerated graph generation unit may include a hardware digital logic circuit configured to perform an operation. In some implementations, the operation includes obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; and generating a K-mer graph using the obtained first set of nucleic acid sequences using multiple non-pipelined hardware logic units of a programmable logic device, each hardware logic unit comprising a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a link between the pair of K-mers. and during generation of the K-mer graph, using a control machine, periodically updating graph description data of the K-mer graph after execution of one or more operations by each hardware logic unit used to generate at least a portion of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, and the control machine triggers execution of the one or more operations of each respective hardware logic unit during generation of the K-mer graph, thereby creating a workflow of operations using the non-pipelined hardware logic units.

[0020] Other implementations may include methods and systems configured to perform operations on the hardware circuitry of a hardware accelerated graph generation unit.

[0021] These and other versions may optionally include one or more of the following features: For example, in some implementations, the output of each hardware logic unit of the plurality of hardware logic units is stored via a hash table cache.

[0022] In some implementations, the operation may further include providing the generated K-mer graph to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more of the plurality of reads and the reference sequence.

[0023] In some implementations, the operation may further include obtaining, by a variant calling unit, the generated K-mer graph, and identifying one or more candidate variants based on the variant calling unit processing the generated K-mer graph, where the candidate variants are differences between base calls of one or more reads in the pileup of reads and nucleotides of the reference genome at particular positions in the reference genome.

[0024] In some implementations, the graph description data may further include (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0025] According to another innovative aspect of the present disclosure, a method for hardware-accelerated generation of K-mer graphs in a programmable logic device is disclosed. In one aspect, the method includes operations of obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; for each particular nucleic acid sequence of the first set of nucleic acid sequences, generating, by a first hardware logic unit, data representing a graph node for each K-mer of the particular nucleic acid sequence for storage in a hash table cache; detecting, by a control machine, that the first hardware logic unit has completed generation of a graph node for each K-mer of the particular nucleic acid sequence; and detecting, by the control machine, for the generated graph node. The method may include operations of configuring a second hardware logic unit to perform graph edge generation; and, for one or more pairs of generated graph nodes, generating, by the second hardware logic unit and for storing in a graph hash table, data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

[0026] Other versions include corresponding systems and apparatus configured to perform the operations of the aforementioned methods defined by the hardware logic circuitry of a hardware accelerated graph generation unit.

[0027] These and other versions may optionally include one or more of the following features. For example, in some implementations, the method may further include periodically storing, by the control machine and in a memory unit accessible to the control machine, graph description data of the instance of the K-mer graph, the graph description data representing (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0028] In some implementations, the first hardware logic unit may be further configured to determine whether one or more of the specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and store data marking the one or more specific K-mers as non-unique K-mers based on a determination that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence.

[0029] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0030] In some implementations, the method may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to retrieve data representing the K-mer graph from the hash table cache and provide the retrieved data representing the K-mer graph to the variant calling unit.

[0031] In some implementations, the method may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively remove data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0032] In some implementations, the control machine is implemented using a third hardware logic unit of a programmable logic device.

[0033] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0034] In some implementations, the control machine is implemented using one or more CPUs or GPUs that execute software instructions to implement the functionality of the control machine.

[0035] In some implementations, the graph description data further includes (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0036] In some implementations, the method may further include evaluating the K-mer graph to check for the presence of a graph cycle. In such implementations, if a graph cycle is detected during the evaluation, the process may include terminating generation of the K-mer graph. Alternatively, if a graph cycle is not detected during the evaluation, the method may include retrieving data describing the structure of the K-mer graph from a hash table cache and providing the retrieved data describing the structure of the K-mer graph to a variant calling module.

[0037] According to another innovative aspect of the present disclosure, a system for hardware-accelerated generation of K-mer graphs using a programmable logic device is disclosed. The system may include a hardware-accelerated graph generation unit including a hardware digital logic circuit configured to perform an operation. In one aspect, the operation includes: obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating, for each specific nucleic acid sequence of the first set of nucleic acid sequences, data representing a graph node for each K-mer of the specific nucleic acid sequence for storage in a hash table cache, by a first hardware logic unit; detecting, by a control machine, that the first hardware logic unit has completed generation of a graph node for each K-mer of the specific nucleic acid sequence; and generating, by the control machine, a graph node for the generated graph node. configuring a second hardware logic unit to perform rough edge generation; and for one or more pairs of generated graph nodes, generating, by the second hardware logic unit and for storing in a graph hash table, data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

[0038] Other versions include corresponding methods and apparatus for performing the above operations.

[0039] These and other versions may optionally include one or more of the following features. For example, in some implementations, the operations may further include periodically storing, by the control machine and in a memory unit accessible to the control machine, graph description data of the instance of the K-mer graph, the graph description data representing (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0040] In some implementations, the first hardware logic unit is further configured to determine whether one or more of the specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and store data marking the one or more specific K-mers as non-unique K-mers based on a determination that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence.

[0041] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0042] In some implementations, the operation may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to retrieve data representing the K-mer graph from the hash table cache and provide the retrieved data representing the K-mer graph to the variant calling unit.

[0043] In some implementations, the operation may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively remove data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0044] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0045] In some implementations, the graph description data further includes (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0046] In some implementations, the method may further include evaluating the K-mer graph to check for the presence of a graph cycle. In such implementations, if a graph cycle is detected during the evaluation, the process may include terminating generation of the K-mer graph. Alternatively, if a graph cycle is not detected during the evaluation, the method may include retrieving data describing the structure of the K-mer graph from a hash table cache and providing the retrieved data describing the structure of the K-mer graph to a variant calling module.

[0047] According to another innovative aspect of the present disclosure, a hardware-accelerated graph generation unit is disclosed. The hardware-accelerated graph generation unit may include a hardware digital logic circuit configured to perform an operation. In one aspect, the operation includes: obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating, for each specific nucleic acid sequence of the first set of nucleic acid sequences, data representing a graph node for each K-mer of the specific nucleic acid sequence for storage in a hash table cache, by a first hardware logic unit; detecting, by a control machine, that the first hardware logic unit has completed generating a graph node for each K-mer of the specific nucleic acid sequence; and generating, by the control machine, a graph node for the generated graph node. configuring a second hardware logic unit to perform rough edge generation; and for one or more pairs of generated graph nodes, generating, by the second hardware logic unit and for storing in a graph hash table, data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

[0048] Other implementations may include methods and systems configured to perform operations on the hardware circuitry of a hardware accelerated graph generation unit.

[0049] These and other versions may optionally include one or more of the following features. For example, in some implementations, the operations may further include periodically storing, by the control machine and in a memory unit accessible to the control machine, graph description data of the instance of the K-mer graph, the graph description data representing (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0050] In some implementations, the first hardware logic unit can be configured to determine whether one or more of the specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and store data marking the one or more specific K-mers as non-unique K-mers based on a determination that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence.

[0051] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0052] In some implementations, the operation may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to retrieve data representing the K-mer graph from the hash table cache and provide the retrieved data representing the K-mer graph to the variant calling unit.

[0053] In some implementations, the operation may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively remove data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0054] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0055] In some implementations, the graph description data may further include (iii) data representing the nucleic acid sequence of the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or the pileup associated with the K-mer graph identifier.

[0056] In some implementations, the operation may further include evaluating the K-mer graph to check for the presence of a graph cycle, and terminating generation of the k-mer graph if a graph cycle is detected during the evaluation, or retrieving data describing the structure of the k-mer graph from a hash table cache if no graph cycle is detected during the evaluation, and providing the retrieved data describing the structure of the k-mer graph to the variant calling module.

[0057] These and other aspects of the present disclosure are discussed in more detail in the following detailed description, with reference to the accompanying drawings. [Brief explanation of the drawings]

[0058] [Figure 1] FIG. 1 illustrates an example system for hardware-accelerated generation of K-mer graphs. [Figure 2] 1 is a flowchart of an example of a process for hardware-accelerated generation of a K-mer graph. [Figure 3] 10 is a flowchart of another example of a process for hardware-accelerated generation of a K-mer graph. [Figure 4] FIG. 1 is a diagram illustrating an example of a K-mer graph. [Figure 5] FIG. 1 is a block diagram of an example of system components that can be used for hardware-accelerated K-mer graphs. DETAILED DESCRIPTION OF THE INVENTION

[0059] The present disclosure relates to hardware-accelerated generation of K-mer graphs. Generating a K-mer graph using hardware circuitry significantly reduces the amount of time required to generate a K-mer graph and offloads the computationally intensive K-mer graph generation process from a software processor to the hardware logic of an integrated circuit, e.g., a field programmable gate array or ASIC. This frees up the software resources of the software processor, which can be used to perform other genomic data processing tasks.

[0060] Hardware-accelerated generation of K-mer graphs can be achieved using a control machine configured to manage the workflow of operations performed by multiple non-pipelined hardware logic units. In particular, the control machine can use multiple non-pipelined hardware logic units to abstractly implement high-level pipeline functionality. The control machine can implement this functionality by storing and updating graph description data including (i) a K-mer graph identifier that identifies an instance of a K-mer graph and (ii) K-mer graph state information. The K-mer graph state information may include, for example, data indicating the last hardware logic unit that performed an operation based on the raw graph data of a particular instance of a K-mer graph, data indicating whether the last hardware logic unit aborted the operation, data indicating the K-mer length, data indicating a K-mer node list, data indicating a list of pointers that can be used to identify K-mer nodes in a cache, the length of the K-mer node list, data indicating a list of non-unique K-mers, or any subset or combination thereof. The control machine manages K-mer graph generation by invoking specific hardware logic units that will perform operations based on the raw graph data and providing the invoked hardware logic units with an updated set of graph description data.

[0061] This storage and updating of graph description data enables the control machine to manage the parallel processing of the non-pipelined hardware logic units in a manner that allows each of the non-pipelined hardware logic units to perform operations based on data corresponding to a different K-mer graph. Thus, in addition to the speedup advantage achieved by using hardware logic instead of executing software instructions to generate a K-mer graph, the present disclosure achieves even faster operations by improving throughput by simultaneously generating segments of different K-mer graphs using different hardware logic units managed by the control machine.

[0062] FIG. 1 illustrates an example of a system 100 for hardware-accelerated generation of K-mer graphs. In some implementations, the system 100 may include a nucleic acid sequencer 110, a reference sequence database 120, a hardware-accelerated graph generation unit 130, multiple hardware logic units 131, 132, 133, 134, 135, 136, 137, and 138, a control machine 140, a graph hash table cache 150, a DRAM 160, and a variant calling unit 180. In some implementations, the hardware-accelerated graph generation unit 130 may be implemented using a programmable logic circuit such as a field-programmable gate array (FPGA). In other implementations, the hardware-accelerated graph generation unit 130 may be implemented using an application-specific integrated circuit (ASIC). In either scenario, the functionality described with respect to the hardware-accelerated graph generation unit 130, and each component implemented thereon, is implemented using a hardware logic circuit configured to perform the functions described herein without executing software instructions to achieve the functions.

[0063] The term “unit” is used herein to describe a software module, a hardware module, or a combination of both used to perform a specified function. The determination of whether a particular “unit” described herein is hardware, software, or a combination of both can be made based on the context of its use. For example, the “input unit” 131, “graph node unit” 132, “graph edge unit” 133, etc., resident in a hardware-accelerated graph generation unit 130 implemented using an FPGA or an ASIC are hardware units whose functionality is realized by hardwired digital logic gates or hardwired digital logic blocks configured to achieve the functionality described herein for the particular “unit.” As another example, the “variant call unit” 180, which is not implemented using the hardware-accelerated graph generation unit 130 of FIG. 1, is a software module whose functionality is realized by one or more computers executing software instructions that define the functionality of the “variant call unit” 180. As another example, a computer or processing unit can be a hardware device that realizes functionality by processing software instructions, and thus the functionality of the computer or processing unit is a combination of hardware and software.

[0064] Although examples of one or more components of FIG. 1 are provided herein as hardware implementations, such as “control machine” 140, because the “control machine” is shown in FIG. 1 as being implemented in hardware-accelerated graph generation unit 130, the present disclosure is not limited to such examples. Instead, other implementations can be employed in which “control machine” 140 is implemented in software, as a software module, or a combination of hardware and software, and in which a computer or processing unit executes software instructions to perform the functions of “control machine” 140 described herein. Similarly, there can be implementations of the present disclosure in which certain components described as software with respect to FIG. 1, e.g., “variant calling unit” 180, are implemented as hardware implementations.

[0065] The nucleic acid sequencer 110 is a device configured to perform primary analysis. The primary analysis may include receiving a biological sample 105, such as a blood sample, a tissue sample, a sputum sample, or a nucleic acid, by the nucleic acid sequencer 110, and generating output data, such as one or more reads 112, each representing the order of nucleotides in a nucleic acid sequence of the received biological sample. In some implementations, sequencing by the nucleic acid sequencer 110 can be performed in multiple read cycles, where a first read cycle generates one or more first reads including a string of base calls representing the order of nucleotides from a first end of a nucleic acid sequence fragment, and a second read cycle generates one or more respective second reads including a string of base calls representing the order of nucleotides from the other end of one of the nucleic acid sequence fragments. In some implementations, the reads may be generated using clonal amplification. In the example of FIG. 1, the one or more reads 112 may include a pileup of reads for a particular reference genome location, where the reference genome location is composed of multiple contiguous reference genome locations.

[0066] Thus, each read represents a portion of the nucleic acid genome of an organism, such as an animal, insect, or plant. Assuming a short nucleic acid sequence fragment with approximately 600 base calls, a first read may represent 150 ordered nucleotides at one end of the nucleic acid sequence fragment, and a second read may represent 150 ordered nucleotides at the other end of the nucleic acid sequence fragment. However, these numbers are merely examples, and any nucleic acid sequencer 110 can be configured to generate reads that can be computed by the hardware-accelerated graph generation unit described herein using any sequencing method. Such reads may be of different lengths than those described herein. For example, in some implementations, the present disclosure can be used to generate hardware-accelerated K-mer graphs of reads generated by nucleic acid sequence fragments having up to 1,000 nucleotides or more, with each read having, for example, 50, 75, 150, 200, 300, 500, or more base calls from each end of the fragment. Each base call may correspond to a nucleotide. The present disclosure can also be used to generate hardware-accelerated K-mer graphs of long reads. Thus, the hardware-accelerated graph generation unit 130 can be used to generate K-mer graphs of any reads generated in any manner by any type of nucleic acid sequencer.

[0067] In some implementations, the biological sample 105 can include a DNA sample, and the nucleic acid sequencer 110 can include a DNA sequencer. In such implementations, the order of sequenced nucleotides in the reads generated by the nucleic acid sequencer can include one or more of guanine (G), cytosine (C), adenine (A), and thymine (T), in any combination. In some implementations, the nucleic acid sequencer 110 can be used to sequence an RNA sample. In some implementations, this can be done using an RNA-seq protocol. As an example, the RNA sample can be pre-processed using reverse transcription to form complementary DNA (cDNA) using a reverse transcriptase enzyme. In other implementations, the nucleic acid sequencer 110 can include an RNA sequencer, and the biological sample can include an RNA sample. Thus, although the example of FIG. 1 describes a nucleic acid sequencer generating reads composed of G, C, A, and T generated by a DNA sequencer based on a DNA sample, the disclosure is not so limited. Alternatively, other implementations can process reads generated by an RNA sequencer based on an RNA sample that are composed of C, G, A, and U. In some implementations, a DNA or RNA read generated by a nucleic acid sequencer can include a base call N, where N represents an unknown base call generated by the nucleic acid sequencer.

[0068] In some implementations, the nucleic acid sequencer 110 can include a next generation sequencer (NGS) configured to generate sequence reads, such as reads 112, for a given sample in a manner that achieves ultra-high throughput, scalability, and speed through the use of massively parallel sequencing technologies. NGS enables rapid sequencing of entire genomes and the ability to zoom in on deeply sequenced target regions, or utilize RNA sequencing (RNA-Seq) to discover novel RNA variants and splice sites, or gene expression analysis, analysis of epigenetic factors such as genome-wide DNA methylation and DNA-protein interactions, sequencing of cancer samples to study rare body variants and tumor subclones, and quantifying mRNA for the study of microbial diversity in humans or the environment.

[0069] The nucleic acid sequencer 110 can obtain the reference genome 122 from a reference genome database 120. In some implementations, only a portion of the reference genome 122 is obtained. The portion of the reference genome 122 obtained can correspond to a reference location in the reference genome 122 to which the pileup of reads 112 is mapped and aligned. The reference genome database 122 can include data storage that configures storage for multiple different reference genomes. In some implementations, the particular reference genome 122 selected from the reference genome database can be based on the type of DNA sample 105. In some implementations, the type of reference genome 122 selected from the reference genome database 120 can be selected based on input from a user of the nucleic acid sequencer 110. In such implementations, the user can, for example, select a reference genome 120 identifier that the nucleic acid sequencer 110 can use to select the particular reference genome 122 from the reference genome database 120. The reference genome 122 can include, for example, a nucleic acid sequence created as a representative set of genes for a particular species.

[0070] The combination of the pileup of reads 112 generated by the nucleic acid sequencer 110 and the resulting reference genome 122 may be provided as input to the hardware accelerated graph generation unit 130. These inputs may be processed by one or more of the hardware logic units 131-138 of the hardware accelerated graph generation unit 130 to generate an instance of a K-mer graph. For example, each hardware logic unit of the hardware logic units 131-138 may be configured to perform a respective operation on each read of the pileup of reads 112 included as input to the hardware accelerated graph generation unit 130.

[0071] The system 100 of FIG. 1 is described herein as including a nucleic acid sequencer. In some implementations, such as those described with reference to FIG. 1 , the system can include a sequencer 110 and a hardware-accelerated graph generation unit 130, and other components of the system 100 can be integrated within the nucleic acid sequencer 110. However, the present disclosure is not limited to integration within the nucleic acid sequencer 110. Instead, in some implementations, the hardware-accelerated graph generation unit 130 can be implemented in a programmable logic device or ASIC integrated into or housed within a computer that is separate from the nucleic acid sequencer 110 and communicatively coupled to the nucleic acid sequencer 110, such as by using one or more wired or wireless networks. Similarly, the database 120, the variant calling unit 180, or both, can be implemented external to the nucleic acid sequencer 110. Similarly, the system 100 need not include the nucleic acid sequencer 110 at all. Instead, in some implementations, the hardware-accelerated graph generation unit 130 and other components of FIG. 1 can be implemented in a computer system that does not include the nucleic acid sequencer 110. In such an implementation, the hardware-accelerated graph generation unit may obtain pileups of leads 112, reference sequences 122, or both, over a network, from storage locations in one or more memory devices, etc. Thus, system 100 illustrates one example of the present disclosure, but does not limit the disclosure to any particular configuration of system components.

[0072] The one or more hardware logic units of the hardware-accelerated graph generation unit 130 may include an input unit 131, a graph node unit 132, a graph edge unit 133, a backpropagation unit 134, a cycle unit 135, a pruning unit 136, a graph output unit 137, and an erasure unit 138. In some implementations, generating a K-mer graph by the hardware-accelerated graph generation unit 130 may include the control machine 140 invoking and configuring each of the hardware logic units 131-138 to perform respective hardware logic operations based on sets of data stored in the cache 150 or the DRAM 160. In other implementations, the control machine 140 may invoking and configuring only a subset of the hardware logic units 131-138 to perform respective hardware logic operations based on sets of raw graph data stored in the cache 150 or the DRAM 160.

[0073] As an example, in some implementations, the hardware-accelerated graph generation unit 130 can be used to generate a special form of a De Bruijn graph. This special form of the De Bruijn graph can be optimized so that non-unique K-mers are represented using multiple respective nodes in the graph, each with a single edge, rather than being represented by a single node with multiple edges. This can be achieved, in part, by using the graph unit 132 to identify non-unique K-mers and flagging them for further processing. A non-unique K-mer can be defined as a K-mer sequence that occurs at least twice in any single read or at least twice in a reference sequence. A unique K-mer can occur in multiple reads, but not more than once within the same read.

[0074] However, in other implementations, a De Bruijn graph can be generated without distinguishing between unique K-mers and non-unique K-mers. Thus, in some implementations, the graph node unit 132, which can identify non-unique K-mers, need not be implemented. In yet another example, the backpropagation unit 134 need not be used to generate all K-mer graphs. Instead, the backpropagation unit 134 may be limited to implementations that can improve performance. As an example, the backpropagation unit 134 can be used to improve the quality of edge weights in cases where later conversion of the generated K-mer graph to a sequence graph is expected.

[0075] The K-mer graph generation example described with respect to the example of FIG. 1 illustrates each hardware logic unit 131-138 as being invoked and configured by control machine 140. While this description generally describes each hardware logic unit 131-138 as being invoked by control machine 140 and configured by control machine 140 using, for example, graph description data stored by control machine 140, to obtain raw graph data, perform one or more particular processing operations based on the obtained raw graph data or other data, and then update the raw graph data, the graph description data, or both, the disclosure is not so limited. However, the disclosure is not limited to such implementations. Instead, in some implementations, each hardware logic unit 131-138 can be configured to perform multiple instances of its respective function. For example, the graph node unit 132 can be configured to accept up to three separate sets of raw graph data and simultaneously perform operations based thereon, the cycle hardware logic unit 135 can be configured to accept up to three separate sets of raw graph data and simultaneously perform operations based thereon, and the PRU can be configured to accept up to two separate sets of raw graph data and simultaneously perform operations based thereon. The number of separate sets or raw graph data, each corresponding to a different K-mer graph, that can be received and processed by a particular hardware logic unit 131-138 is limited only by the hardware resources available to the system 100. For example, assuming sufficient levels of DRAM and FPGA logic units are available, the number of separate sets of raw graph data that can be received and simultaneously processed by the hardware logic units 131-138 can be four or more. Similarly, one or more of the hardware logic units 131-138 can be configured to receive and simultaneously process fewer raw graph data sets if such resources are not readily available or if heavy use of a particular hardware logic unit is not expected.

[0076] In still other implementations, there need not be only one instance of each hardware logic unit 131-138, each capable of simultaneously processing a separate set of raw graph data corresponding to a different K-mer graph. Instead, in some implementations, multiple instances of each hardware-accelerated graph generation unit 130 can be configured to include multiple instances of one or more of the hardware logic units 131-138. In such cases, the control machine 140 can be configured to monitor the status and availability of each hardware logic unit 131-138, and then activate and configure each hardware logic unit in a manner that load-balances processing operations across each respective hardware logic unit. For example, in some implementations, the hardware-accelerated graph generation unit 130 can be configured to have three instances of the graph node unit 132, each capable of receiving up to three separate raw graph data sets and simultaneously performing operations based thereon, three instances of the graph edge unit 133, each capable of receiving up to three separate raw graph data sets and simultaneously performing operations based thereon, two backpropagation units 134, each capable of receiving up to two separate raw graph data sets and simultaneously performing operations based thereon, and three cycle units 135, each capable of receiving up to two separate raw graph data sets and simultaneously performing operations based thereon. The activation / deactivation of each hardware logic unit, the configuration of each hardware logic unit, the inputs to each hardware logic unit, the outputs from each hardware logic unit, and the updating of the graph description data by each hardware logic unit are managed and directed by the control machine 140.

[0077] Input Unit

[0078] The input unit 131 can receive input data, sometimes referred to herein as raw graph data, including a pileup of generated reads 112 and a selected reference genome 122. The selected reference genome 122 may include a portion of the reference genome. The raw graph data may include, for example, data processed by one or more hardware logic units 131-138 during generation of an instance of a K-mer graph. While the raw graph data includes, for example, the generated reads 112 and the selected reference genome 122, the raw graph data may also include, for example, K-mer nodes generated by the graph node unit 132 and edges generated by the graph edge unit 133. The input unit 131 can format the generated reads 112 and the resulting reference genome 122 for storage in the DRAM 160. Formatting the generated reads may include, for example, encoding the reads for storage in the DRAM 160. In some implementations, encoding the reads may include encoding each base call corresponding to a nucleotide in the read into a 4-bit value. For example, A can be encoded as 0000, C can be encoded as 0001, G can be encoded as 0010, T can be encoded as 0011, and N can be encoded as 0100, where N is an unknown base call. In some implementations, the encoded data may also include data representing a MAPQ score, a read number, a sequence length, a SAM flag, a base call or nucleotide of the read, one or more quality indicators of the read other than the MAPQ score, or any combination thereof. The encoded read data can range from a 16-bit value to a 64-bit value or more that describes the read. The input unit 131 can write the generated reads to the DRAM 160.

[0079] The control machine 140 can detect receipt of raw input data, activate the input unit 131, and initialize graph description data corresponding to an instance of a K-mer graph to be generated based on the raw input data. Activating the input unit 131 may include the control machine 140 sending one or more control messages to the input unit 131 instructing the input unit 131 to perform an operation defined by the hardware logic circuitry of the input unit 131 based on the raw data provided as input to the input unit 131. In some implementations, activating a hardware logic unit such as the input unit 131 may also include the control machine providing the hardware logic unit with graph description data that the control machine can use to configure the hardware logic unit to perform the operation. Configuring the hardware logic unit may include, for example, providing a K-mer node that is a pointer to a cache location that stores the K-mer, and providing information describing the length of the K-mer or similar information needed for the hardware logic unit to perform the operation.

[0080] Initializing the graph description data may include, for example, the control machine 140 generating a K-mer graph identifier for the raw input data, generating a graph state information data structure, or a combination thereof. The K-mer graph identifier includes a data string of one or more letters, one or more numbers, or a combination thereof that can be used to identify an instance of a K-mer graph throughout the K-mer graph generation process, from the time the raw graph data is received by the input unit 131 to at least the time the data associated with the K-mer graph identifier is removed from the cache 150, the DRAM 160, or both using the purging unit 138 after fully generating the K-mer graph for the particular raw graph data set. In some implementations, the K-mer graph identifier may include a number, such as a 6-bit number having a value between 0 and 63. In some implementations, the K-mer graph identifier may also be used to reference the K-mer graph after the purging unit is used to remove such data from the cache 150, the DRAM 160, or both. A graph state information data structure is a data structure having one or more fields that store data describing the current state of a K-mer graph instance to be generated for a particular set of raw input data. The state information may include, for example, data indicating the last hardware logic unit that performed an operation based on the raw graph data of a particular K-mer graph instance, data indicating whether the last hardware logic unit aborted the operation, data indicating the K-mer length, data indicating the K-mer node list, data indicating a list of pointers that can be used to identify K-mer nodes in cache, the length of the K-mer node list, data indicating a list of non-unique K-mers, data indicating the location of the raw input data in cache or DRAM, data indicating the base addresses in DRAM of the nodes of the K-mer graph instance, or any subset or combination thereof.

[0081] Input unit 131 may format input read 112 and reference genome 122 and write input read 112 and reference genome to DRAM 160. Control machine 140 may detect when input unit 131 has completed formatting and writing input read 112 and reference genome 122 to DRAM 160. When control machine 140 detects completion of formatting and writing input read 112 and reference genome 122 to DRAM, control machine 140 may update the graph state information to indicate that input unit 131's operation on the first raw graph data of the first instance of the K-mer graph is complete.

[0082] Once the first raw graph data is input, formatted, and stored in DRAM 160, the control machine 140 can determine the next hardware logic unit to be invoked and configured. For example, the control machine 140 can invoke and configure the graph node unit 132 to generate a K-mer node based on the portion of the reference genome 122 and the pileup of reads that have been formatted and stored in DRAM 160.

[0083] Graph Node Unit

[0084] The control machine 140 can continue generating the first instance of the K-mer graph by initiating and configuring the graph node unit 132 and processing the formatted reads 112 and reference genome 122 stored in DRAM. This can include, for example, sending control signals to the graph node unit 132, providing graph description data to the graph node unit 132, or a combination thereof. The graph description data can be used to configure the graph node unit 132 for the operation. For example, providing the graph description data to the graph node unit 132 from the control machine 140 can configure the graph node unit 132 to identify K-mers of a particular size defined by the graph description data. Other fields of the graph description data described herein can be used to configure hardware logic units such as the graph node unit 132 in a similar manner.

[0085] Additionally, the control machine 140 can detect, in substantially parallel fashion, that the input unit 131 has received second raw graph data as input. The control machine 140 can then activate the input unit 131 and instruct the unit 131 to format the reads and the reference genome for the second raw graph data, and generate second graph description data for a second instance of a K-mer graph to be generated based on the second raw graph data. In this manner, the control machine 140 can achieve a high level of throughput by simultaneously managing the operation of different hardware logic units 131, 132 performing the K-mer graph generation process based on different sets of raw graph data at different processing stages. The control machine 140 is configured to manage this parallel functionality across each of the hardware logic units 131, 132, 133, 134, 135, 136, 137, 138, such that at any particular time, there may be as many as eight hardware logic units operating on eight different sets of raw graph data, and the hardware-accelerated graph generation unit 130 operates to generate eight different K-mer graphs simultaneously. The control machine 140 manages this process throughout by using the graph description data to activate and configure each associated hardware logic unit, thereby achieving high-level pipeline functionality abstractly from non-pipelined hardware logic units 131, 132, 133, 134, 135, 136, 137, 138, which do not have direct physical input / output connections between each respective hardware logic unit. While an example of the simultaneous generation of eight K-mer graphs running simultaneously is shown, the present disclosure may be adapted to achieve the simultaneous generation of many more K-mer graphs, for example, by implementing multiple hardware-accelerated graph generation units 130 at once, multiple instances of multiple hardware logic units on one or more hardware-accelerated graph generation units 130, or a combination thereof.

[0086] The graph node unit 132 can analyze each read in the pileup of reads 112 to identify each of the read's K-mers. This can include, for example, sliding a K-mer access window along each position of each read to identify each particular K-mer for each read. The graph node unit 132 can store data representing a node of the K-mer graph for each identified K-mer for each read in cache 150. Similarly, the graph node unit 132 can also generate and store in DRAM a list of node pointers in a node pointer data structure, each node pointer pointing to a K-mer node cache location. The graph node unit 132 can also generate and store information indicating the location and length of the list of node pointers for each K-mer graph in graph description data maintained by the control machine. These pointers can be used as graph state information by the control machine 140 to configure other hardware logic units in subsequent portions of the K-mer graph generation process. The cache 150 may use one or more cache coherency policies, such as an LRU cache coherency policy configured to evict the oldest object from the cache 150, where the oldest object is determined based on the time the object was written to the cache 150.

[0087] An example of data generated by graph node unit 132 and stored in cache 150, DRAM 160, or both is shown with reference to Figure 4. Figure 4 shows a reference genome 410, a portion of a read 420, and presents a De Bruijn graph 400. De Bruijn graph 400, described in more detail below, includes a node for each K-mer in the genome 410 and the portion of the read 420, and an edge between each pair of K-mer nodes linking pairs of nodes that have k-1 overlapping nucleotides.

[0088] 4, the graph node unit 132 can generate data representing nodes 431, 432, 433, 434, 435, 436, 437, and 438 of a first path 430 of the DeBruijn graph 400 based on receiving a portion of the reference genome 410 and a read 420, and can generate nodes 441, 442, 443, and 444. First, the graph node unit 132 can align the overlapping portions of the reference genomes 410a and 410b and the overlapping portions of the reads 420a and 420b to identify overlapping regions, as shown in FIG. 4. The graph node unit 132 can identify each of the K-mers of the portions of the genome 410 and the read 420. This can be accomplished by using an access window of length k (equal to 4 in this example) at the first location of the portion of the reference genome 410 that captures the K-mer identified by the access window, generating data representing a node of a graph that includes the captured K-mer, storing the data representing the node in cache 150, advancing the access window by one nucleotide, and then iteratively repeating the process. In this example, the graph node unit 132 can identify the K-mers ATCG, TCGC, CGCC, GCCT, CCTA, CTAG, TAGA, and AGAA for the portion of the reference genome 410 and generate respective nodes 431, 432, 433, 434, 435, 436, 437, and 438, one of which corresponds to each K-mer. Each node has length k (4 in this example) and is created to overlap with the next adjacent node by k−1 K-mers. The graph node unit 132 can store the generated nodes in cache 150, DRAM 160, or both. In some implementations, the cache may include a hash table cache. In such implementations, nodes may be stored as keys in a hash table. The graph node unit 132 may store data describing pointers to K-mer node locations within graph description data maintained by the control machine 140.

[0089] The graph node unit 132 can perform the same operation on the read 420. For the read 420, the graph node unit 132 can identify the K-mers ATCG, TCGC, CGCG, GCGT, CGTA, GTAG, TAGA, and AGAA. This can similarly be achieved by using an access window of length k (equal to 4 in this example) at the beginning of the portion of the read 420 that captures the K-mer identified by the access window, and then advancing the access window and repeating the process. The graph node unit 132 can begin by identifying each K-mer for the portion of the genome 410. In some implementations, the graph node unit 132 can generate a corresponding node for each of the K-mers. In other implementations, the graph node unit 132 can generate only K-mer nodes 431, 432, 433, 434, 435, 436, 437, 438 corresponding to identified K-mers that differ from the K-mer nodes for the portion of the reference genome 410. In each scenario, each node is created to have length k (in this example, 4) and overlap with the next adjacent node by k-1 K-mers. This can continue until a node has been created for each K-mer in the portion of the reference genome 410 and stored in cache 150 or DRAM 160.

[0090] In some implementations, the graph node unit 132 may also be configured to identify non-unique K-mers. In such implementations, the graph node unit 132 may determine, for each particular read in the initial pileup of reads, whether the identified K-mer is a unique K-mer or a non-unique K-mer. If the graph node unit 132 determines that a particular K-mer is a unique K-mer, the graph node unit 132 may advance the access window by one nucleotide to evaluate the next K-mer. Alternatively, if the graph node unit 132 determines that a particular K-mer is a non-unique K-mer, the graph node unit 132 may store data indicating that the particular K-mer is a non-unique K-mer. For example, the graph node unit 132 may store a data flag in the graph description data maintained by the control machine for a particular instance of the K-mer graph indicating that the K-mer is a non-unique K-mer. However, such data may be stored by any other component of the hardware accelerated graph generation unit 130, or in any other memory unit of the hardware accelerated graph generation unit 130, or a combination thereof. Subsequent hardware logic units may then perform operations to handle non-unique K-mers in order to reduce or eliminate cycles in the K-mer graph instance.

[0091] At this point in the process, graph node unit 132 stores data representing the nodes of the K-mer graph for each K-mer in cache 150, DRAM 160, or both. That is, hardware-accelerated graph generation unit 130 has not yet generated graph edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a, graph edge weights, etc. These features of this instance of the K-mer graph may be generated by one or more other hardware logic units of hardware-accelerated graph generation unit 130.

[0092] The control machine 140 may monitor the operation of the graph node unit 132. When the graph node unit 132 generates data representing a K-mer node for each K-mer of each read of the first raw graph data of this first instance of the K-mer graph, the control machine may update the graph description data to indicate that the hardware-accelerated graph generation unit 130 has completed the operation of the graph node unit 132 based on the first raw graph data. In addition, the control machine 140 may also store the graph description data including, for example, a flag identifying each non-unique K-mer, the storage location of the graph node for the K-mer, and data indicating that the graph node unit 132 has completed the operation.

[0093] Once K-mer graph nodes are created and stored in cache 150, control machine 140 can determine the next hardware logic unit to invoke and configure. For example, control machine 140 can invoke and configure graph edge unit 133 to create and / or weight graph edges between pairs of nodes.

[0094] Graph Edge Unit

[0095] The graph edge unit 133 may generate graph edges between pairs of K-mer nodes generated by the graph node unit 132. The control machine 140 may initiate the graph edge unit 133 when it is determined that the graph node unit 132 for the first K-mer graph instance has completed and the graph edge unit 133 is available. In some implementations, the control machine 140 may provide or otherwise make accessible to the graph edge unit 133 a location for storing the K-mer graph nodes generated by the graph node unit 132 for a particular instance of a K-mer graph. For example, the control machine 140 may access K-mer graph description data generated and stored by the graph node unit 132 during generation of K-mer nodes for the instance of the K-mer graph. The accessed K-mer graph description data may indicate or otherwise describe a list of K-mers.

[0096] Once the graph edge unit 133 obtains the locations of the K-mer graph nodes of the first instance of the K-mer graph, the graph edge unit can begin generating one or more graph edges between data representing the K-mer nodes. In some implementations, the graph edge unit 133 can access data representing the graph nodes for each of the K-mers of a particular read from a hash table cache. The graph edge unit 133 can generate data representing graph edges between the graph nodes for the K-mers for storage in the hash table cache. For example, the data representing the graph edges can be stored in the hash table cache as part of the graph node record of the edge's source node. In some implementations, the graph edge unit 133 can assign an edge weight to each edge of the K-mer graph. For example, the graph edge unit 133 can add +1 or another weight to each generation of a graph edge linking each K-mer pair.

[0097] As an example, the graph edge unit 133 can identify adjacent nodes using graph description data obtained from the control machine 140. Nodes can be determined to be adjacent based on various factors, such as determining that the nodes share k-1 overlapping nucleotides or that the nodes are observed at two consecutive positions in a sliding K-mer access window. For example, the graph edge unit 133 can slide a K-mer access window along each position of each read in the raw graph data. In some implementations, the graph edge unit 133 can create an edge or increase the edge weight by one when it determines that two consecutive K-mers that overlap in all but one base are observed in a read. The graph node 133 creates an edge or increments the edge weight in such a scenario because this scenario represents an edge between the graph nodes corresponding to those two consecutive K-mers.

[0098] In some implementations, data representing graph nodes may be stored as hash keys in a hash table. In such implementations, graph edge unit 133 may generate an edge from a first node (or hash key) to a second node (or hash key) by accessing the hash location to which the first node (or hash key) is mapped and generating a pointer to store in the hash location that points to the second node (or hash key). Subsequent edges may be generated in the same manner, thereby creating a path 430 or 440 through the graph that can be walked using one or more graph walking algorithms.

[0099] 4, the graph edge unit 133 may generate data representing one or more edges between pairs of nodes 431, 432, 433, 434, 435, 436, 437, 438 of a first path 430, pairs of nodes 441, 442, 443, 444 of a second path 440, or one or more pairs of nodes of the first path 430 and the second path 440. Examples of these edges are shown in FIG. 4 as edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a.

[0100] In this example, the sequence of nucleotides 420 is referred to as a read. However, in some implementations, low-quality base removal can occur such that the sequence of nucleotides 420 is part of a contig or read. In such implementations, graph edges linking paired nodes only create a path of one or more links within a particular contig, and do not create a path from a K-mer node of a first contig to a K-mer node of a second contig. A contig can include the sequence of nucleotides that results after low-quality bases are removed.

[0101] Backpropagation Unit

[0102] The hardware-accelerated graph generation unit 130 may include a backpropagation unit 134. However, the control machine 140 need only invoke and configure the backpropagation unit 134 in certain implementations. For example, the control machine 140 may invoke the backpropagation unit 134 when the control machine 140 determines that a K-mer graph being generated by a current set of raw graph data will later be converted to a sequence graph. Once invoked, the backpropagation module 134 may receive graph description data from the control machine 140. In such an implementation, adjusting the graph edge weights may make the weights more reliable when inherited by the sequence graph.

[0103] The graph edge unit 133 can build edges between the K-mer nodes of a contig by identifying corresponding K-mer nodes in the cache 150, generating edges linking the K-mer nodes, and then incrementing the edge weight by +1 for each generation. In some implementations, after the K-mer nodes of a contig are added to the K-mer graph and weighted using the graph edge unit 134, the backpropagation unit 134 can be used to backpropagate the +1 edge weight increments k−1 steps through a linear chain of graph edges “left” of the contig's starting node in the K-mer graph. In this case, the “left” of the contig's starting node in the K-mer graph is the direction of the K-mer graph opposite the directed edge of the K-mer graph. To illustrate this concept, the “left” of node 434 in the De Bruijn graph 400 are nodes 433, 432, and 431.

[0104] For example, in some implementations, backpropagation module 134 can access data representing a K-mer graph, including its K-mer nodes, corresponding graph edges, etc., in a hash table cache, and then adjust the edge weights of the K-1 nodes that occur before the start of a new contig. Backpropagation unit 135 can find the appropriate K-mer nodes and edges to adjust based on graph description data received from control machine 160, which includes pointers to cache locations that store this information. The graph description data can be updated with any changes that occur during backpropagation.

[0105] In some implementations, an N-based contig may be advantageous for performing the aforementioned backpropagation because it only requires incrementing a series of (N-K) edge weights. However, if this K-mer graph is later converted to a sequence graph with (N-1) internal edges corresponding to this contig, the first (K-1) edge weights will not inherit the appropriately incremented edge weights. The aforementioned backpropagation addresses most instances of this problem. Therefore, backpropagation can be used to address this problem in order to increase the reliability of the inherited edge weights when the K-mer graph is converted to a sequence graph.

[0106] Cycle Unit

[0107] The hardware-accelerated graph generation unit 130 may include a cycle unit 135. In some implementations, the cycle unit 135 may be activated and configured by the control machine 140 to detect cycles in the K-mer graph instance. For example, the cycle unit 135 may evaluate K-mer nodes and K-mer edges in raw graph data of the K-mer graph instance generated by one or more of the input unit 131, the graph node unit 132, the graph edge unit 133, and the backpropagation unit 134. The cycle unit 135 is configured to receive graph description data from the control machine 140. The cycle unit 135 may iteratively flag head nodes for deletion. A head node may include a node that does not contain any in-edges. Here, an in-edge is an edge that points from a first node to itself. After each head node is flagged for deletion, the cycle unit 135 may determine whether a node pointed to by an out-edge became a head node as a result of the deleted node. If such nodes are determined, they are flagged for deletion. An out-edge is a graph edge that points from the first node to another node. The cycle unit 135 can continue to execute this process until there are no more head nodes.

[0108] Once it is determined that no head nodes remain, cycle unit 135 can determine whether the graph is empty, which means that all nodes in the graph are flagged for deletion. If the headless graph is empty, then there was no cycle. Alternatively, if the headless graph is not empty, then the graph must contain a cycle. Cycles are resistant to this type of deletion because deleting a node outside the cycle prevents any node in the cycle from becoming a head node.

[0109] Upon making any of these determinations, cycle unit 135 may provide an indication to control machine 140 as to whether a cycle has been detected. Control machine 140 may then determine which hardware logic unit to activate and configure next based on the indication provided by cycle unit 135. For example, if a cycle is detected and generation of the K-mer graph instance should be aborted, control machine 140 may activate and configure pruning unit 138. In such a case, the pruning unit may remove raw graph data corresponding to the aborted K-mer graph instance from cache 150 and DRAM 160. Alternatively, if generation of the K-mer graph instance is to continue, control machine 140 may activate and configure another hardware logic unit to perform subsequent operations based on the raw graph data to generate the K-mer graph instance. For example, if generation of the K-mer graph is to continue, control machine 140 may activate and configure either pruning unit 136 or graph output unit 137.

[0110] Cycle unit 135 may be used by hardware-accelerated graph generation unit 130 to detect cycles in an instance of a K-mer graph being generated, but cycle unit 135 may be selectively activated and configured similarly to backpropagation unit 134. This is because it is predictable that some K-mer graphs may contain cycles. However, for certain types of K-mer graphs, it may be beneficial to not have graphs with cycles. Thus, hardware-accelerated graph generation unit 130 may be configured, for example, so that control machine 140 receives input indicating whether cycle unit 135 should be executed for a particular instance of a graph.

[0111] Pruning Unit

[0112] The hardware-accelerated graph generation unit 130 may include a pruning unit 135. The pruning unit 136, like the backpropagation unit 134 and the cycle unit 135, may be selectively activated and configured by the control machine 160. When activated and configured, the pruning unit 135 may evaluate the weight of each graph edge in the raw graph data for the K-mer graph instances generated up to this point by the hardware-accelerated graph generation unit 130. In some implementations, if the pruning unit 136 determines that the weight value of a graph edge does not meet a predetermined threshold, the pruning unit 136 may remove the graph edge and any K-mer nodes that occur after the identified graph edge. Alternatively, if the pruning unit 136 determines that the weight value of a graph edge meets the predetermined threshold, the pruning unit 136 leaves the graph edge as is.

[0113] In other implementations, pruning unit 136 can identify linear chains, which are maximal paths through the graph in which all internal nodes between a start node and an end node have exactly one in-edge and one out-edge. In such implementations, pruning unit 136 can determine whether all internal edges of the linear chain do not satisfy a pruning threshold. If such a scenario occurs, pruning unit 136 can remove the entire linear chain, including all internal edges and all internal nodes, except for the start node and / or end node of the chain, which pruning unit 136 can retain if they have non-internal edges.

[0114] Graph Output Unit

[0115] The hardware-accelerated graph generation unit 130 may include a graph output unit 137. When the K-mer graph instance is described by the graph description data and the cache data, the hardware-accelerated graph generation unit 130 may use the graph output unit 137 to generate a final version 170 of the K-mer graph instance. For example, the graph output unit 137 may retrieve data representing the K-mer graph from the hash table cache 150, e.g., using the graph description data including a pointer to a location in the hash table cache that stores the K-mer graph data. The graph output unit 137 may then provide the data obtained from the hash table cache 150 describing the final version of the K-mer graph 170 to the variant calling unit 180. The variant calling unit 180 may perform variant calling analysis based on the final version of the K-mer graph 170 to generate a set of variants 190. The set of variants 190 may include one or more candidate variants. A variant is a change in the genomic data of an organism. A candidate variant is a call made by the variant calling unit that is inferred by the variant calling unit based on processing of the K-mer graph 170. In some implementations, a candidate variant may have a threshold level of error in the variant call.

[0116] The variant calling unit 180 can identify candidate variants by processing the K-mer graph 180. In some implementations, for example, the variant calling unit 180 can identify candidate variants when one or more reads in a pileup of reads differ in a base call or nucleotide from a nucleotide in the reference genome at a particular position in the reference genome. Data describing the set of variants 190 can be generated or determined in various ways. For example, in some implementations, the variant calling operation can be performed as described in more detail in, for example, U.S. Patent Application Publication Nos. 2016 / 0180019, 2016 / 0306922, and 2019 / 0259468, the entire contents of each of which are incorporated herein by reference in their entirety. Data describing the set of variants 190 can be provided for output in various ways. For example, data describing the set of variants 190 can be displayed on the display of the nucleic acid sequencer 110, can be displayed on the display of a different computer, can be output audibly via one or more speakers of a computing device, can be output via a printer, or any combination thereof.

[0117] Erasure Unit

[0118] The erasure unit 138 may be used to perform memory reclamation tasks upon completion and output of an instance of a K-mer graph by the hardware-accelerated graph generation unit 130. For example, the erasure unit may delete all raw graph data associated with a particular instance of a K-mer graph completed and output by the hardware-accelerated graph generation unit 130. Alternatively, or in addition, the erasure unit 138 may delete all data associated with a particular instance of the graphics unit 130 stored by the control machine, delete all data associated with a particular instance of the graphics unit 130 stored in DRAM 160, etc. This allows the erasure unit 138 to selectively delete data representing graph nodes and graph edges of the K-mer graph from the hash table cache. Such deletion is selective because only a portion of the contents of the cache, the control machine, or DRAM need be deleted. Furthermore, when a graph is stored as a hash table, the hash table is often sparsely populated, and it is faster for the erasure unit 138 to selectively delete only occupied hash table entries rather than deleting the entire hash table, thereby improving performance.

[0119] However, in some implementations, non-hash table data associated with a graph need not be cleared item by item, in which case the clearing unit 138 may set list lengths to zero in the graph description data or simply free allocated memory space for reuse without clearing the contents.

[0120] 2 is a flowchart of an example process 200 for hardware-accelerated generation of a K-mer graph. Generally, process 200 includes: obtaining a first set of nucleic acid sequences (210), the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating a K-mer graph using the obtained first set of nucleic acid sequences with a plurality of non-pipelined hardware logic units of a programmable logic device, each hardware logic unit comprising a different hardware logic circuit configured to perform one or more operations; generating a K-mer graph (220), wherein each node of the K-mer graph represents a K-mer, each edge of the graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a number of occurrences of the K-mer sequence represented by the pair of K-mers; and, during generation of the K-mer graph, using a control machine to generate a K-mer graph (221). periodically updating graph description data of the K-mer graph after execution of one or more operations by each hardware logic unit used to generate at least a portion of the graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, and wherein the control machine triggers execution of the one or more operations of each respective hardware logic unit during generation of the K-mer graph, thereby creating a workflow of operations using the non-pipelined hardware logic units (230); and providing the K-mer graph to a variant calling module, wherein the variant calling module processes the K-mer graph to determine one or more candidate variants between one or more of the plurality of reads and the reference sequence.

[0121] 3 is a flowchart of another example of a process 300 for hardware-accelerated generation of a K-mer graph. Generally, process 300 includes obtaining a first set of nucleic acid sequences (310), the first set of nucleic acid sequences including (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating, for each particular nucleic acid sequence of the first set of nucleic acid sequences, data representing a graph node for each K-mer of the particular nucleic acid sequence for storage in a hash table cache, by a first hardware logic unit (320); detecting, by a control machine, that the first hardware logic unit has completed generation of a graph node for each K-mer of the particular nucleic acid sequence (330); and, for one or more pairs of generated graph nodes, generating (350) by the second hardware logic unit and for storing in a graph hash table, data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

[0122] 4 is an example of a K-mer graph 400. In this example, the K-mer graph 400 is generated based on at least a portion of a reference genome 410 and reads 420. In this example, the K-mer graph 400 is a De Bruijn graph.

[0123] The K-mer graph 400 is generated using a plurality of nodes and one or more edges between pairs of nodes. Each node represents a K-mer of length k, where k=4 in this example. Each edge provides an indication that there is a k-1 nucleotide overlap of the K-mers linked by the edge. In the K-mer graph 400, a path 430 includes a plurality of nodes and edges representing each K-mer of a portion of the reference sequence 410. A path 440 then includes a plurality of nodes and edges representing portions of the reads 420 that differ from portions of the reference genome 410.

[0124] FIG. 5 is a block diagram of an example of components of a system 500 that can be used to hardware accelerate K-mer graphs.

[0125] Computing device 500 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Computing device 550 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, and other similar computing devices. In addition, computing device 500 or 550 may include a Universal Serial Bus (USB) flash drive. A USB flash drive may store an operating system and other applications. A USB flash drive may include input / output components, such as a wireless transmitter or a USB connector, that can be inserted into a USB port of another computing device. The components, their connections and relationships, and their functions illustrated herein are intended to be examples only and are not intended to limit the implementation of the invention(s) described and / or claimed herein.

[0126] Computing device 500 includes a processor 502, memory 504, a storage device 506, a high-speed interface 508 connecting to memory 504 and a high-speed expansion port 510, and a low-speed interface 512 connecting to a low-speed bus 514 and storage device 506. Each of the components 502, 504, 506, 508, 510, and 512 are interconnected using various buses and may be implemented on a common motherboard or in other manners as appropriate. Processor 502 processes instructions for execution within computing device 500, including instructions stored in memory 504 or storage device 508, and can display graphical information for a GUI on an external input / output device, such as a display 516 coupled to high-speed interface 506. In other implementations, multiple processors and / or multiple buses can be used, along with multiple memories and types of memory, as appropriate. Multiple computing devices 500 can also be connected, each providing a portion of the required computations, for example, as a server bank, a cluster of blade servers, or a multiprocessor system.

[0127] The memory 504 stores information within the computing device 500. In one implementation, the memory 504 is a volatile memory unit or units. In another implementation, the memory 504 is a non-volatile memory unit or units. The memory 504 may also be another form of computer-readable medium, such as a magnetic disk or optical disk.

[0128] The storage device 506 can provide mass storage for the computing device 500. In one implementation, the storage device 506 can be or contain a computer-readable medium such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid-state memory device, or an array of devices including devices in a storage area network or other configuration. The computer program product can be tangibly embodied in an information carrier. The computer program product can also contain instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable or machine-readable medium, such as the memory 504, the storage device 506, or memory on the processor 502.

[0129] The high-speed controller 508 manages bandwidth-intensive operations for the computing device 500, while the low-speed controller 512 manages low-bandwidth-intensive operations. This allocation of functionality is merely one example. In one implementation, the high-speed controller 508 is coupled to the memory 504, the display 516, e.g., via a graphics processor or accelerator, and to a high-speed expansion port 510 that can accept various expansion cards (not shown). In this implementation, the low-speed controller 512 is coupled to the storage device 506 and the low-speed expansion port 514. The low-speed expansion port, which can include various communication ports, e.g., USB, Bluetooth, Ethernet, wireless Ethernet, can be coupled, e.g., via a network adapter, to one or more input / output devices, such as a keyboard, a pointing device, a microphone / speaker pair, a scanner, or a networking device, such as a switch or router. The computing device 500, as shown in the figure, can be implemented in several different forms. For example, the computing device can be implemented as a standard server 520, or multiple times in a cluster of such servers. The computing device can also be implemented as part of a rack server system 524. Additionally, the computing device can be implemented in a personal computer, such as a laptop computer 522. Alternatively, components from computing device 500 can be combined with other components in a mobile device (not shown), such as device 550. Each such device can contain one or more of computing devices 500, 550, and the overall system can be made up of multiple computing devices 500, 550 in communication with each other.

[0130] Computing device 500 can be implemented in several different forms, as shown. For example, the computing device can be implemented as a standard server 520, or multiple times in a cluster of such servers. The computing device can also be implemented as part of a rack server system 524. Additionally, the computing device can be implemented in a personal computer, such as a laptop computer 522. Alternatively, components from computing device 500 can be combined with other components in a mobile device (not shown), such as device 550. Each such device can contain one or more of computing devices 500, 550, and the entire system can be made up of multiple computing devices 500, 550 in communication with each other.

[0131] Computing device 550 includes, among other components, a processor 552, memory 564, and input / output devices such as a display 554, a communications interface 566, and a transceiver 568. Device 550 may also include a storage device, such as a microdrive or other device, to provide additional storage. Each of components 550, 552, 564, 554, 566, and 568 are interconnected using various buses, and some of the components may be implemented on a common motherboard or in other manners as appropriate.

[0132] The processor 552 can execute instructions within the computing device 550, including instructions stored in the memory 564. The processor can be implemented as a chipset of chips including separate and multiple analog and digital processors. In addition, the processor can be implemented using any of several architectures. For example, the processor 510 can be a Complex Instruction Set Computer (CISC) processor, a Reduced Instruction Set Computer (RISC) processor, or a Minimal Instruction Set Computer (MISC) processor. The processor can provide coordination of other components of the device 550, such as control of a user interface, applications run by the device 550, and wireless communication by the device 550.

[0133] The processor 552 can communicate with a user via a control interface 558 and a display interface 556 coupled to a display 554. The display 554 can be, for example, a TFT (Thin-Film-Transistor Liquid Crystal Display) display, an OLED (Organic Light Emitting Diode) display, or other suitable display technology. The display interface 556 can include appropriate circuitry for driving the display 554 to present graphical and other information to the user. The control interface 558 can receive commands from the user and translate the commands for submission to the processor 552. Additionally, an external interface 562 can be provided in communication with the processor 552 to enable proximity-range communication between the device 550 and other devices. The external interface 562 can provide, for example, wired communication in some implementations or wireless communication in other implementations, and multiple interfaces can also be used.

[0134] Memory 564 stores information within computing device 550. Memory 564 may be implemented as one or more of a computer-readable medium or media, a volatile memory unit or units, or a non-volatile memory unit or units. Additionally, expansion memory 574 may be provided and connected to device 550 via expansion interface 572, which may include, for example, a single in-line memory module (SIMM) card interface. Such expansion memory 574 may provide additional storage space for device 550 or may store applications or other information for device 550. Specifically, expansion memory 574 may include instructions that perform or complement the processes described above and may also include secure information. Thus, for example, expansion memory 574 may be provided as a security module for device 550 and may be programmed with instructions that enable secure use of device 550. Additionally, secure applications may be provided via a SIMM card along with additional information, such as placing identifying information on the SIMM card in an unhackable manner.

[0135] The memory may include, for example, flash memory and / or NVRAM memory, as described below. In one implementation, a computer program product is tangibly embodied in an information carrier. The computer program product contains instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable or machine-readable medium, such as memory 564, expansion memory 574, or memory on processor 552, which may be received via transceiver 568 or external interface 562.

[0136] Device 550 can communicate wirelessly via communication interface 566, which may include digital signal processing circuitry as needed. Communication interface 566 can provide for communication under various modes or protocols, such as GSM voice calls, SMS, EMS, or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS, among others. Such communication can occur, for example, via radio frequency transceiver 568. Additionally, short-range communication can occur, such as using Bluetooth, Wi-Fi, or other such transceivers (not shown). Additionally, a Global Positioning System (GPS) receiver module 570 can provide additional navigation-related and location-related wireless data to device 550, for use by applications running on device 550, as appropriate.

[0137] Device 550 can also communicate audibly using audio codec 560, which can receive speech information from a user and convert this speech information into usable digital information. Audio codec 560 can also generate audible sounds for the user, such as through a speaker in the handset of device 550. Such sounds can include sounds from a voice telephone call, recorded sounds such as voice messages, music files, etc., and can also include sounds generated by applications running on device 550.

[0138] The computing device 550 can be implemented in several different forms, as shown in the figure. For example, the computing device can be implemented as a mobile phone 580. The computing device can also be implemented as part of a smartphone 582, personal digital assistant, or other similar mobile device.

[0139] Various implementations of the systems and methods described herein can be realized in digital electronic circuitry, integrated circuits, specially designed ASICs (application-specific integrated circuits), computer hardware, firmware, software, and / or combinations of such implementations. These various implementations can be special-purpose or general-purpose, and can include implementations in one or more computer programs executable and / or interpretable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0140] These computer programs (also known as programs, software, software applications, or code) include machine instructions for a programmable processor and may be implemented in high-level procedural and / or object-oriented programming languages ​​and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device, such as a magnetic disk, optical disk, memory, programmable logic device (PLD), used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0141] To provide for interaction with a user, the systems and techniques described herein can be implemented on a computer that has a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user, and a keyboard and pointing device, such as a mouse or trackball, by which the user can provide input to the computer. Other types of devices can also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user can be received in any form, including acoustic input, speech input, or tactile input.

[0142] The systems and techniques described herein can be implemented in a computing system that includes back-end components, e.g., as a data server, or in a computing system that includes middleware components, e.g., an application server, or in a computing system that includes front-end components, e.g., a client computer having a graphical user interface or web browser through which a user can interact with an implementation of the systems and techniques described herein, or in any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communications network. Examples of communications networks include a local area network ("LAN"), a wide area network ("WAN"), and the Internet.

[0143] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0144] Other embodiments

[0145] Several embodiments have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the present invention. Additionally, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desired results. Additionally, other steps can be provided or eliminated from the described flows, and other components can be added to or removed from the described systems. Accordingly, other embodiments are within the scope of the following claims. [Explanation of symbols]

[0146] 100 systems 110 Nucleic Acid Sequencer 120 Reference Sequence Database 130 Hardware Accelerated Graph Generation Unit 131, 132, 133, 134, 135, 136, 137, 138 Hardware logic unit 140 Control Machine 150 Graph Hash Table Cache 160 DRAM 170 K-mer graphs 180 variant call units

Claims

1. 1. A method for hardware accelerated generation of K-mer graphs in a programmable logic device, comprising: obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences comprising (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; For each particular nucleic acid sequence of the first set of nucleic acid sequences: generating, by a first hardware logic unit, data representing a graph node for each K-mer of the particular nucleic acid sequence for storage in a hash table cache; detecting, by a control machine, that the first hardware logic unit has completed generating a graph node for each K-mer of the specific nucleic acid sequence; configuring, by said control machine, a second hardware logic unit to perform generation of graph edges for said generated graph nodes; For one or more pairs of the generated graph nodes, generating, by the second hardware logic unit, data representing graph edges between one or more pairs of the generated graph nodes generated by the first hardware logic unit for storage in a graph hash table, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

2. The method comprises:

2. The method of claim 1, further comprising periodically storing, by said control machine and in a memory unit accessible to said control machine, graph description data of said K-mer graph instance, said graph description data representing (i) a K-mer graph identifier and (ii) K-mer graph state information.

3. the first hardware logic unit: determining whether one or more of the specific K-mers of the specific nucleic acid sequence matches another K-mer of the specific nucleic acid sequence; 2. The method of claim 1, further comprising storing data marking the one or more particular K-mers as non-unique K-mers based on a determination that the one or more particular K-mers of the particular nucleic acid sequence match another K-mer of the particular nucleic acid sequence.

4. The method comprises: a third hardware logic unit of the programmable logic device; obtaining data representing the K-mer graph from the hash table cache; 10. The method of claim 1, further comprising instructing to execute hardware logic configured to provide the obtained data representing the K-mer graph to a variant calling unit.

5. The method comprises: a third hardware logic unit of the programmable logic device; 2. The method of claim 1, further comprising: instructing to execute hardware logic configured to selectively remove data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

6. the control machine is implemented using a third hardware logic unit of the programmable logic device; or The method of claim 1 , wherein the control machine is implemented using one or more CPUs or GPUs that execute software instructions to implement the functionality of the control machine.

7. The method comprises: evaluating the K-mer graph to check for the presence of graph cycles; If a graph cycle is detected during said evaluation, Finish generating the K-mer graph, or If no graph cycle is detected during said evaluation, retrieving data describing the structure of the K-mer graph from the hash table cache; and providing the obtained data describing the structure of the K-mer graph to a variant calling module.

8. 1. A system for hardware-accelerated generation of K-mer graphs using a programmable logic device, comprising: a hardware accelerated graph generation unit including hardware digital logic circuitry configured to perform operations, said operations comprising: obtaining a first set of nucleic acid sequences, the first set of nucleic acid sequences comprising (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; For each particular nucleic acid sequence of the first set of nucleic acid sequences: generating, by a first hardware logic unit, data representing a graph node for each K-mer of the particular nucleic acid sequence for storage in a hash table cache; detecting, by a control machine, that the first hardware logic unit has completed generating a graph node for each K-mer of the specific nucleic acid sequence; configuring, by said control machine, a second hardware logic unit to perform generation of graph edges for said generated graph nodes; For one or more pairs of the generated graph nodes, generating, by the second hardware logic unit, data representing graph edges between one or more pairs of the generated graph nodes generated by the first hardware logic unit for storage in a graph hash table, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

9. The operation is 9. The system of claim 8, further comprising periodically storing, by said control machine and in a memory unit accessible to said control machine, graph description data of said K-mer graph instance, said graph description data representing (i) a K-mer graph identifier and (ii) K-mer graph state information.

10. the first hardware logic unit: determining whether one or more of the specific K-mers of the specific nucleic acid sequence matches another K-mer of the specific nucleic acid sequence; 9. The system of claim 8, further configured to store data marking the one or more particular K-mers as non-unique K-mers based on a determination that the one or more particular K-mers of the particular nucleic acid sequence match another K-mer of the particular nucleic acid sequence.

11. the second hardware logic comprising: The method of claim 1 or the system of claim 8, further configured to assign an edge weight to each edge of the K-mer graph.

12. The operation is (i) instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to retrieve data representing the K-mer graph from the hash table cache and provide the retrieved data representing the K-mer graph to a variant call unit; or 10. The system of claim 8, further comprising: (ii) instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively remove data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

13. 10. The method of claim 1 or the system of claim 8, wherein the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

14. The method of claim 1 or the system of claim 8, wherein the graph description data further includes data representing (iii) the last hardware logic unit of the plurality of hardware logic units that executed hardware logic on the K-mer graph, or a nucleic acid sequence of a pileup associated with a K-mer graph identifier.

15. The operation is evaluating the K-mer graph to check for the presence of graph cycles; If a graph cycle is detected during said evaluation, Finish generating the K-mer graph, or If no graph cycle is detected during said evaluation, retrieving data describing the structure of the K-mer graph from the hash table cache; and providing the obtained data describing the structure of the K-mer graph to a variant calling module.

Images