Pipeline clock driving circuit, computing chip, computing power board and computing device
By introducing multi-stage clock drive circuits and delay modules into the pipeline clock drive circuit, the pulse clock width and delay are optimized, solving the system performance problem caused by excessive delay between adjacent operation stages, and improving the operating frequency and system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN MICROBT ELECTRONICS TECH CO LTD
- Filing Date
- 2023-02-02
- Publication Date
- 2026-04-24
AI Technical Summary
In existing pipelined clock drive circuits, the delay between the pulse clocks of two adjacent operational stages is relatively long, resulting in a low actual operating frequency of the latch and limiting system performance.
A multi-stage clock driving circuit is adopted. Each stage of the clock driving circuit includes a flip-flop, a delay module, and a combinational logic module. The pulse signal is processed with different delays through the first and second delay sub-modules to generate a pulse clock signal that meets the minimum pulse width requirement, thereby optimizing the pulse clock width and delay.
The pipeline's operating frequency was increased, system performance was optimized, and the pipeline's computation time requirements were met.
Smart Images
Figure CN116088635B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to circuitry for performing hash algorithms. More specifically, it relates to a pipelined clock drive circuit, and to a computing chip, computing board, and computing device including the pipelined clock drive circuit. Background Technology
[0002] Chips used to generate cryptocurrencies typically employ a pipelined architecture comprising multiple operational stages. Depending on the algorithm used, the computational logic is divided into several operational stages, each with a similar functional design and operational structure. Specifically, when latches are used as timing devices in the various operational stages of the pipeline, each latch requires an operating clock (i.e., a pulse clock). Therefore, for each operational stage, a pulse clock is input to it through a corresponding first-stage clock driver circuit. Typically, the operating clock for each operational stage originates from the same clock source, and the clock signal generated by this source is passed stage by stage through the pipeline clock driver circuit.
[0003] The basic principle of generating the operating clock for the latches at each operational stage is to input both the input clock signal from the current stage's clock driver circuit and the delayed input clock signal into a gate circuit (such as a NOR gate or NAND gate) to generate a pulse clock. The delayed input clock signal is generated after the input clock signal has passed through a delay module. The width of this pulse clock is essentially determined by the delay time of the delay module. Furthermore, the delayed input clock signal is also output to the next stage's clock driver circuit as its input clock signal. This ensures that the width of the generated pulse clock is the same as the delay between the input clock signals of the two adjacent clock driver circuits; that is, the width of the pulse clock is the same as the delay between the pulse clocks of two adjacent operational stages.
[0004] It's important to note that in a pipeline, the data generated by the k-th operation stage in the m-th clock cycle needs to be acquired and used by the (k+1)-th operation stage in the (m+1)-th clock cycle. Therefore, with the computation time required for each operation stage remaining constant, the closer the rising edge of the k-th operation stage's clock pulse in the m-th clock cycle is to the rising edge of the (k+1)-th clock cycle of the (k+1)-th operation stage's clock pulse (i.e., the smaller the ratio of this distance to the clock cycle), the longer the required clock cycle. In other words, the longer the delay between the clock pulses of two adjacent operation stages (i.e., the larger the ratio of the distance between the rising edges of the same clock cycle of two adjacent operation stages to the clock cycle), the lower the actual operating frequency of the latches in the pipeline, and the worse the system performance. Therefore, a shorter delay between the clock pulses of two adjacent operation stages is desirable.
[0005] However, the pulse clock width needs to meet the pipeline's minimum pulse width requirement. That is, when the pulse clock is active, the state (high or low) of the input clock signal to the clock drive circuit of that stage needs to remain unchanged, thereby maintaining the generated pulse clock state for a time exceeding the minimum pulse width. As mentioned above, the delay between the pulse clocks of two adjacent operational stages is the same as the pulse clock width. Therefore, the delay between the pulse clocks of two adjacent operational stages also needs to meet this minimum pulse width requirement, which results in a lower pipeline operating frequency and limits system performance.
[0006] Therefore, there is a demand for new technologies. Summary of the Invention
[0007] One of the purposes of this disclosure is to provide an improved pipelined clock drive circuit.
[0008] According to one aspect of the present invention, a pipeline clock driving circuit is provided for providing a pulse clock signal to a pipeline including multiple operational stages. The pipeline clock driving circuit includes: a multi-stage clock driving circuit, wherein each stage clock driving circuit provides a pulse clock signal to a corresponding operational stage among the multiple operational stages of the pipeline; and a clock source coupled to the input of a first-stage clock driving circuit for providing a basic clock signal, wherein the inputs of the other stages of the multi-stage clock driving circuit besides the first-stage clock driving circuit are coupled to the output of the previous-stage clock driving circuit, and wherein each stage clock driving circuit includes: a flip-flop coupled to the input of its own stage clock driving circuit; and a delay module including a first delay submodule coupled to the flip-flop. The circuit includes a clock drive module and a combinational logic module coupled to the output of the flip-flop and the first delay submodule. The combinational logic module performs combinational logic operations on the pulse signal output by the flip-flop and the feedback pulse signal output by the first delay submodule to generate a pulse clock signal to be provided to a corresponding operation stage of the pipeline. In the multi-stage clock drive circuit, except for the last stage clock drive circuit, the delay module also includes a second delay submodule. The second delay submodule is coupled to the output of the flip-flop and delays the pulse signal output by the flip-flop, outputting the delayed pulse signal as a clock drive signal to the next stage clock drive circuit.
[0009] According to another aspect of the invention, a computing chip is provided, which includes one or more pipelined clock drive circuits as described above.
[0010] According to another aspect of the invention, a computing board is provided, which includes one or more computing chips as described above.
[0011] According to another aspect of the invention, a computing device is provided, which includes one or more computing boards as described above.
[0012] Other features and advantages of the present invention will become clear from the following description with reference to the accompanying drawings. Attached Figure Description
[0013] The accompanying drawings are for illustrative purposes and are intended only to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying it to computing devices. These drawings are in no way intended to limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar structural elements.
[0014] Figure 1 A schematic diagram of a prior art pipeline clock drive circuit is shown.
[0015] Figure 2A A schematic diagram of a pipeline clock drive circuit according to an embodiment of the present invention is shown.
[0016] Figure 2B A timing diagram of the pulse clock signal generated by a pipeline clock drive circuit according to an embodiment of the present invention is shown.
[0017] Figure 3A A schematic diagram of a pipeline clock drive circuit according to another embodiment of the present invention is shown.
[0018] Figure 3B A timing diagram of the pulse clock signal generated by a pipeline clock drive circuit according to another embodiment of the present invention is shown.
[0019] Figure 4 A schematic diagram of a delay module of a pipelined clock drive circuit according to an embodiment of the present invention is shown.
[0020] Figure 5 A schematic diagram of a delay module of a pipeline clock drive circuit according to another embodiment of the present invention is shown.
[0021] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0022] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation
[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.
[0024] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. That is, the hash engines described herein are shown in an exemplary manner to illustrate different embodiments of the circuitry in this disclosure and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement the invention, and not exhaustive ways.
[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0026] Figure 1 A schematic diagram of a prior art pipeline clock drive circuit 100 is shown. The pipeline clock drive circuit 100 is used to provide pulse clock signals for a pipeline 101 including multiple operational stages 101-1, ..., 101-(N-1), 101-N.
[0027] like Figure 1 As shown, the pipeline clock drive circuit 100 includes a clock source 110 and multiple clock drive circuits 120-1, 120-2, ..., 120-N. The clock source 110 is coupled to the input of the first-stage clock drive circuit 120-1 to provide a basic clock signal. Each of the multiple clock drive circuits 120-1, 120-2, ..., 120-N provides a pulse clock signal to a corresponding operational stage among the multiple operational stages 101-N, 101-(N-1), ..., 101-1 of the pipeline 101.
[0028] Each stage of the clock drive circuit 120-1, 120-2, ..., 120-N includes delay modules 130-1, 130-2, ..., 130-N and combinational logic modules 140-1, 140-2, ..., 140-N (such as NOR gates, NAND gates, etc.). Delay modules 130-1, 130-2, ..., 130-N are used to delay the input clock signals of the corresponding stage of the clock drive circuit 120-1, 120-2, ..., 120-N. Combinational logic modules 140-1, 140-2, ..., 140-N are used to perform logical operations (such as NOR, NAND, etc.) on the input clock signals of the clock drive circuits 120-1, 120-2, ..., 120-N and the input clock signals delayed by delay modules 130-1, 130-2, ..., 130-N, and output the operation results as the output pulse clock signals of the clock drive circuits 120-1, 120-2, ..., 120-N, which are used to provide to the corresponding operation stages 101-N, 101-(N-1), ..., 101-1 of pipeline 101.
[0029] Furthermore, the input clock signals delayed by delay modules 130-1, 130-2, ... are also output to the next-stage clock drive circuits 120-2, ..., 120-N as their input clock signals. This ensures that the width of the generated pulse clock signal is the same as the delay between the input clock signals of the two adjacent clock drive circuits; that is, the width of the pulse clock signal is the same as the delay between the pulse clock signals of the two adjacent operational stages.
[0030] As mentioned earlier, the longer the delay between the clock pulses of two adjacent operational stages, the lower the actual operating frequency of the latches in the pipeline, and the worse the system performance. Therefore, a shorter delay between the clock pulses of two adjacent operational stages is desirable. However, the delay between the clock pulses of two adjacent operational stages also needs to meet the minimum pulse width requirement, which makes the delay relatively long, thus limiting the system performance.
[0031] To address this problem, this invention proposes an improved pipelined clock drive circuit, wherein the pulse width of the pulse clock signal generated by the clock drive circuit is independent of the delay between the pulse clocks of two adjacent operational stages.
[0032] Figure 2A A schematic diagram of a pipeline clock drive circuit 200 according to an embodiment of the present invention is shown. Figure 2B The timing diagram of the pulse clock signal generated by the pipeline clock drive circuit 200 is shown.
[0033] The pipeline clock drive circuit 200 is used to provide pulse clock signals for the pipeline 201, which includes multiple operational stages 201-1, ..., 201-N.
[0034] like Figure 2A As shown, the pipeline clock drive circuit 200 includes a clock source 210 and multi-stage clock drive circuits 220-1, ..., 220-N.
[0035] Clock source 210 is coupled to the input of the first-stage clock drive circuit 220-1 to provide a basic clock signal. The duty cycle of the basic clock signal provided by clock source 210 can be 0.5, and the frequency can be several hundred megahertz, such as 400-700MHz.
[0036] The inputs of all clock driving circuits in the multi-stage clock driving circuits 220-1, ..., 220-N except for the first-stage clock driving circuit 220-1 are coupled to the output of the previous-stage clock driving circuit. Each stage clock driving circuit 220-1, ..., 220-N is used to provide a pulse clock signal to a corresponding operational stage in the multiple operational stages 201-N, ..., 201-1 of the pipeline 201.
[0037] Each stage of the clock drive circuit 220-1, ..., 220-N includes flip-flops 230-1, ..., 230-N, delay modules 240-1, ..., 240-N, and combinational logic modules 250-1, ..., 250-N.
[0038] Flip-flops 230-1, ..., 230-N are coupled to the input of the clock drive circuit of this stage. That is, flip-flop 230-1 in the first-stage clock drive circuit 220-1 is coupled to the output of clock source 210, while the flip-flops in other stages of the clock drive circuit are coupled to the output of the previous stage's clock drive circuit. Flip-flops 230-1, ..., 230-N can be edge-triggered flip-flops. The type and connection method of flip-flops 230-1, ..., 230-N can be configured as needed.
[0039] exist Figure 2A The diagram illustrates an embodiment of flip-flops 230-1, ..., 230-N as rising-edge D flip-flops. Figure 2AIn the illustrated embodiment, the SET pin of flip-flops 230-1, ..., 230-N is coupled to the output of delay modules 240-1, ..., 240-N. The D pin is fixed at a low level (i.e., logic "0"). The CP pin is coupled to the output of the previous stage clock drive circuit, and the output Q is coupled to delay modules 240-1, ..., 240-N as its input. When the SET pin signal of the rising edge D flip-flop is high, the output Q is always high. When the SET pin signal is low, the output Q changes to the D pin signal value whenever the rising edge of the CP pin signal arrives. In other embodiments, flip-flops 230-1, ..., 230-N can be, for example, falling edge flip-flops, and their connection method can also be adjusted accordingly (hereinafter referred to as...). Figure 3A (Detailed description in the illustrated embodiments).
[0040] The inputs of delay modules 240-1, ..., 240-N are coupled to the outputs of flip-flops 230-1, ..., 230-N. Delay modules 240-1, ..., 240-N include first delay sub-modules 241-1, ..., 241-N, which are coupled to the outputs of flip-flops 230-1, ..., 230-N and delay the pulse signals output by flip-flops 230-1, ..., 230-N, feeding the delayed pulse signals back to flip-flops 230-1, ..., 230-N as feedback pulse signals.
[0041] In the multi-stage clock drive circuits 220-1, ..., 220-N, except for the last stage clock drive circuit 220-N, the delay modules 240-1, ... also include second delay sub-modules 242-1, ..., which are coupled to the outputs of flip-flops 230-1, ... and delay the pulse signals output by flip-flops 230-1, ..., and output the delayed pulse signals as clock drive signals to the next stage clock drive circuit.
[0042] In a preferred embodiment, the first delay submodule 241-1, ..., 241-N and the second delay submodule 242-1, ... further invert the pulse signals output by the triggers 230-1, ..., 230-N, respectively.
[0043] In a preferred embodiment, the delay times of the pulse signals output by the first delay submodules 241-1, ..., 241-N and the second delay submodules 242-1, ... to the triggers 230-1, ..., 230-N are different. In a further preferred embodiment, the delay times of the pulse signals output by the first delay submodules 241-1, ..., 241-N to the triggers 230-1, ..., 230-N can be greater than the delay times of the pulse signals output by the second delay submodules 242-1, ... to the triggers 230-1, ...
[0044] The first delay submodules 241-1, ..., 241-N and the second delay submodules 242-1, ... can be implemented by a plurality of buffers and / or inverters. In a preferred embodiment, such as Figure 2A As shown, the first delay submodules 241-1, ..., 241-N and the second delay submodules 242-1, ... can each be composed of an odd number of inverters. In other embodiments, the first delay submodules 241-1, ..., 241-N and the second delay submodules 242-1, ... can each be composed of a plurality of buffers and an odd number of inverters. In a further preferred embodiment, the number of inverters constituting the first delay submodules 241-1, ..., 241-N can be greater than the number of inverters constituting the second delay submodules 242-1, ...
[0045] Combinational logic modules 250-1, ..., 250-N are coupled to the outputs of flip-flops 230-1, ..., 230-N and the first delay submodules 241-1, ..., 241-N. Combinational logic modules 250-1, ..., 250-N perform combinational logic operations on the pulse signals output from flip-flops 230-1, ..., 230-N and the delayed pulse signals (feedback pulse signals) output from the first delay submodules 241-1, ..., 241-N to generate pulse clock signals to provide to a corresponding operation stage 201-N, ..., 201-1 in pipeline 201. Combinational logic modules 250-1, ..., 250-N can be designed accordingly based on the type of flip-flops 230-1, ..., 230-N. Figure 2A In the illustrated embodiment, when flip-flops 230-1, ..., 230-N are rising-edge D flip-flops, the combinational logic modules 250-1, ..., 250-N can be constructed from OR gates or NOR gates. In other embodiments, the combinational logic modules 250-1, ..., 250-N can be constructed from AND gates or NAND gates (hereinafter referred to as AND gates). Figure 3A (Detailed description in the illustrated embodiments).
[0046] In a preferred embodiment, such as Figure 2AAs shown, the direction of pulse signal propagation in the multi-stage clock drive circuits 220-1, ..., 220-N is opposite to the direction of data signal propagation in the multiple operational stages 201-1, ..., 201-N of the pipeline. That is, the first-stage clock drive circuit 220-1 provides a pulse clock signal to the last operational stage 201-N, while the last-stage clock drive circuit 220-N provides a pulse clock signal to the first operational stage 201-1, and so on. This arrangement makes it easier to meet the timing requirements of each operational stage 201-1, ..., 201-N.
[0047] In an alternative embodiment, the second delay submodule can be arranged before the flip-flop in each stage of the clock drive circuit. Specifically, in each stage of the clock drive circuit, the flip-flop is directly or via the second delay submodule coupled to the input of the current stage of the clock drive circuit and outputs a pulse signal as the input signal of the next stage of the clock drive circuit. The first delay submodule delays the pulse signal output by the flip-flop and feeds back the delayed pulse signal as a feedback pulse signal to the flip-flop. A combinational logic module is coupled to the outputs of the flip-flop and the first delay submodule to generate a pulse clock signal. In the first stage of the clock drive circuit, the flip-flop is directly coupled to the input of the current stage of the clock drive circuit and receives the basic clock signal output by the clock source. In other stages of the multi-stage clock drive circuit besides the first stage, the flip-flop is coupled to the input of the current stage of the clock drive circuit via the second delay submodule. The input of the second delay submodule is coupled to the input of the current stage of the clock drive circuit, delays the input signal of the current stage of the clock drive circuit (i.e., the pulse signal output by the flip-flop of the previous stage of the clock drive circuit), and outputs the delayed pulse signal to the flip-flop. This arrangement can achieve [the desired effect] Figure 2A The illustrated embodiments exhibit similar technical effects.
[0048] refer to Figure 2B The timing of the generation of pulse clock signals is described below using the first-stage clock drive circuit 220-1 as an example.
[0049] The CP terminal of flip-flop 230-1 receives the basic clock signal S201 from clock source 210 as an input signal (correspondingly, the CP terminals of subsequent flip-flops receive the clock drive signal S204 from the output of the second delay submodule in the previous stage clock drive circuit as input signals), and provides the pulse signal S202 at the output terminal Q to one input terminal of delay module 240-1 and combinational logic module 250-1 (in this embodiment, a NOR gate). The first delay submodule 241-1 in delay module 240-1 inverts and delays the pulse signal S202 to obtain the feedback pulse signal S203, and provides it to the SET terminal of flip-flop 230-1 and the other input terminal of combinational logic module 250-1. The second delay submodule 242-1 in delay module 240-1 inverts and delays the pulse signal S202 to obtain the clock drive signal S204, and outputs it to the next stage clock drive circuit as the input signal of the next stage clock drive circuit. The combinational logic module 250-1 receives signals S202 and S203 as inputs to obtain the output pulse clock signal S205, and outputs the pulse clock signal S205 to the arithmetic stage 201-N.
[0050] After the entire system is powered on, before the clock source 210 outputs the basic clock signal S201, the pulse signal S202 at the output terminal Q of the flip-flop 230-1 will stabilize at a high level. The output signal S203 of the first delay submodule 241-1 will stabilize at a low level, meaning the SET terminal of the flip-flop 230-1 will be low. The output signal S204 of the second delay submodule 242-1 will also stabilize at a low level, meaning the input signal of the next-stage clock drive circuit will also be low (corresponding to the input signal S201 of the first-stage clock drive circuit 220-1). Therefore, the input signals of the combinational logic module 250-1 (or NOT gate) are high (S202) and low (S203), respectively, and its output pulse clock signal S205 will be low.
[0051] At time t1, clock source 210 begins outputting the basic clock signal S201. The period of the basic clock signal S201 is T.
[0052] like Figure 2B As shown, when signal S201 changes from low to high, the rising edge of the signal at the CP terminal of flip-flop 230-1 arrives, and the SET terminal signal (S203) remains low. This causes the signal S202 at the output terminal Q of flip-flop 230-1 to become the signal value at the D terminal, i.e., low. Therefore, the input signals of combinational logic module 250-1 (OR gate) are low (S202) and low (S203), respectively, and its output pulse clock signal S205 becomes high.
[0053] After time T1, at time t2, the output signal S203 of the first delay submodule 241-1 goes high. T1 is the delay between signal S203 and signal S202, determined by the configuration of the first delay submodule 241-1. Figure 2A In the embodiment shown, T1 is the sum of the delay times of the multiple inverters in the first delay submodule 241-1.
[0054] Therefore, as Figure 2B As shown, on one hand, the SET terminal of flip-flop 230-1 becomes high, causing the output Q signal S202 of flip-flop 230-1 to become high. On the other hand, the input signals of combinational logic module 250-1 (OR gate) are high (S202) and high (S203), respectively, and its output pulse clock signal S205 becomes low.
[0055] After T1, at time t3, the output signal S203 of the first delay submodule 241-1 goes low.
[0056] Therefore, as Figure 2B As shown, on one hand, the SET terminal of flip-flop 230-1 goes low, but there is no rising edge at the CP terminal yet, so the output Q signal S202 of flip-flop 230-1 remains high. On the other hand, the input signals of combinational logic module 250-1 (OR gate) are high (S202) and low (S203), respectively, and its output pulse clock signal S205 remains low.
[0057] On the other hand, from time t1 (when signal S202 goes low) for a period of time T2, the output signal S204 of the second delay submodule 242-1 goes high. Then, from time t2 (when signal S202 goes high) for another period of time T2, the output signal S204 of the second delay submodule 242-1 goes low. T2 is the delay between signals S204 and S202, determined by the configuration of the second delay submodule 242-1. Figure 2A In the embodiment shown, T2 is the sum of the delay times of the multiple inverters in the second delay submodule 242-1.
[0058] After this, the values of signals S202, S203, S204, and S205 remain unchanged. The next cycle of the basic clock signal S201 begins at time t4. From time t1 to time t4, one cycle T of the basic clock signal S201 is elapsed.
[0059] At time t4, signal S201 goes high.
[0060] like Figure 2BAs shown, when signal S201 changes from low to high, the rising edge of the signal at the CP terminal of flip-flop 230-1 arrives, and the SET terminal signal (S203) remains low, causing the signal S202 at the output terminal Q of flip-flop 230-1 to go low. Consequently, the pulse clock signal S205 at the output terminal of combinational logic module 250-1 (OR gate) goes high.
[0061] After T1, at time t5, the output signal S203 of the first delay submodule 241-1 becomes high.
[0062] Therefore, as Figure 2B As shown, on one hand, the SET terminal of flip-flop 230-1 goes high, causing the signal S202 of the output Q terminal of flip-flop 230-1 to go high. On the other hand, the pulse clock signal S205 at the output terminal of combinational logic module 250-1 goes low.
[0063] After T1, at time t6, the output signal S203 of the first delay submodule 241-1 goes low.
[0064] Therefore, as Figure 2B As shown, the output Q signal S202 of the flip-flop 230-1 remains high, and the pulse clock signal S205 at the output of the combinational logic module 250-1 remains low.
[0065] On the other hand, starting from time t4 (when signal S202 goes low), after time T2, the output signal S204 of the second delay submodule 242-1 goes high. Then, starting from time t5 (when signal S202 goes high), after time T2, the output signal S204 of the second delay submodule 242-1 goes low.
[0066] Thus, a pulse clock signal S205 with a period of T and a pulse width of T1 is generated at the output of the combinational logic module 250-1. This pulse clock signal S205 is provided to the corresponding operational stage 201-N as the operating clock.
[0067] Furthermore, a clock drive signal S204 is generated at the output of the second delay submodule 242-1 as the input signal for the next-stage clock drive circuit (equivalent to the input signal S201 of the first-stage clock drive circuit 220-1). The rising edge of the clock drive signal S204 is used to trigger the flip-flop of the next-stage clock drive circuit. Figure 2B As shown, the rising edge of the clock drive signal S204 is delayed by T2 compared to the rising edge of the input signal S201. Correspondingly, the pulse clock signal generated by each stage of the clock drive circuit is delayed by T2 compared to the pulse clock signal generated by the previous stage of the clock drive circuit.
[0068] exist Figure 2B In the example shown, time period T1 is longer than T2, which means that the pulse width T1 of the pulse clock signal S205 generated by the first-stage clock drive circuit is greater than the delay time T2 between the rising edges of the input clocks of the two adjacent clock drive circuits (i.e., S201 and S204). In other words, the pulse width of the pulse clock signal is greater than the delay between the pulse clock signals of the two adjacent operational stages. However, in other embodiments, time period T1 may be shorter than T2, which means that the pulse width of the pulse clock signal is less than the delay between the pulse clock signals of the two adjacent operational stages.
[0069] In this way, the pulse width of the pulse clock signal and the delay between the pulse clock signals of two adjacent operational stages can be set separately according to actual needs, thereby enabling more precise adjustment and optimization of the pipeline's pulse clock signal to maximize computational efficiency and optimize system performance.
[0070] Figure 3A A schematic diagram of a pipeline clock drive circuit 300 according to another embodiment of the present invention is shown. Figure 3B The timing diagram of the pulse clock signal generated by the pipeline clock drive circuit 300 is shown.
[0071] The pipeline clock drive circuit 300 is used to provide pulse clock signals to the pipeline 301, which includes multiple operational stages 301-1, ..., 301-N. For example... Figure 3A The pipeline clock drive circuit 300 shown includes a clock source 310 and multi-stage clock drive circuits 320-1, ..., 320-N.
[0072] Clock source 310 is coupled to the input of the first-stage clock driver circuit 320-1 to provide a basic clock signal. The inputs of all clock driver circuits in the multi-stage clock driver circuits 320-1, ..., 320-N except for the first-stage clock driver circuit 320-1 are coupled to the output of the previous-stage clock driver circuit. Each stage clock driver circuit 320-1, ..., 320-N provides a pulse clock signal to a corresponding operational stage in the multiple operational stages 301-N, ..., 301-1 of the pipeline 301.
[0073] Each stage of the clock drive circuit 320-1, ..., 320-N includes flip-flops 330-1, ..., 330-N, delay modules 340-1, ..., 340-N, and combinational logic modules 350-1, ..., 350-N.
[0074] Flip-flops 330-1, ..., 330-N are coupled to the input of the clock drive circuit of this stage. That is, flip-flop 330-1 in the first-stage clock drive circuit 320-1 is coupled to the output of the clock source 310, while flip-flops in other stages of the clock drive circuit are coupled to the output of the previous stage clock drive circuit.
[0075] exist Figure 3A The diagram illustrates an embodiment of flip-flops 330-1, ..., 330-N as a falling-edge D flip-flop. Figure 3A In the illustrated embodiment, the RESET pins of flip-flops 330-1, ..., 330-N are coupled to the outputs of delay modules 340-1, ..., 340-N. The D pin is fixed at a high level (i.e., logic "1"). The CPN pin is coupled to the output of the previous stage clock drive circuit, while the output Q is coupled to the delay modules 340-1, ..., 340-N as its input. When the RESET pin signal of the D flip-flop is low on the falling edge, the output Q is always low. When the RESET pin signal is high, the output Q changes to the D pin signal value whenever the falling edge of the CPN pin signal arrives.
[0076] The inputs of delay modules 340-1, ..., 340-N are coupled to the outputs of flip-flops 330-1, ..., 330-N. Delay modules 340-1, ..., 340-N include first delay sub-modules 341-1, ..., 341-N, which are coupled to the outputs of flip-flops 330-1, ..., 330-N and delay the pulse signals output by flip-flops 330-1, ..., 330-N, feeding the delayed pulse signals back to flip-flops 330-1, ..., 330-N as feedback pulse signals.
[0077] In the multi-stage clock drive circuits 320-1, ..., 320-N, except for the last stage clock drive circuit 320-N, the delay modules 340-1, ... also include second delay sub-modules 342-1, ..., which are coupled to the outputs of flip-flops 330-1, ... and delay the pulse signals output by flip-flops 330-1, ..., and output the delayed pulse signals as clock drive signals to the next stage clock drive circuit.
[0078] In a preferred embodiment, the first delay submodules 341-1, ..., 341-N and the second delay submodules 342-1, ... further invert the pulse signals output by the triggers 330-1, ..., 330-N. In a preferred embodiment, the delays of the first delay submodules 341-1, ..., 341-N and the second delay submodules 342-1, ... on the pulse signals output by the triggers 330-1, ..., 330-N are different. In a further preferred embodiment, the delay of the first delay submodules 341-1, ..., 341-N on the pulse signals output by the triggers 330-1, ..., 330-N can be greater than the delay of the second delay submodules 342-1, ... on the pulse signals output by the triggers 330-1, ...
[0079] The first delay submodules 341-1, ..., 341-N and the second delay submodules 342-1, ... can be implemented by a plurality of buffers and / or inverters. In a preferred embodiment, such as Figure 3A As shown, the first delay submodules 341-1, ..., 341-N and the second delay submodules 342-1, ... can each be composed of an odd number of inverters. In other embodiments, the first delay submodules 341-1, ..., 341-N and the second delay submodules 342-1, ... can each be composed of a plurality of buffers and an odd number of inverters. In a further preferred embodiment, the number of inverters constituting the first delay submodules 341-1, ..., 341-N can be greater than the number of inverters constituting the second delay submodules 342-1, ...
[0080] Combinational logic modules 350-1, ..., 350-N are coupled to the outputs of flip-flops 330-1, ..., 330-N and the first delay submodules 341-1, ..., 341-N. Combinational logic modules 350-1, ..., 350-N perform combinational logic operations on the pulse signals output from flip-flops 330-1, ..., 330-N and the delayed pulse signals (feedback pulse signals) output from the first delay submodules 341-1, ..., 341-N to generate pulse clock signals to provide to a corresponding operation stage 301-N, ..., 301-1 in pipeline 301. Figure 3A In the embodiment shown, when the flip-flops 330-1, ..., 330-N are falling-edge D flip-flops, the combinational logic modules 350-1, ..., 350-N can be composed of NAND gates.
[0081] refer to Figure 3B The timing of the generation of pulse clock signals is described below using the first-stage clock drive circuit 320-1 as an example.
[0082] The CPN terminal of flip-flop 330-1 receives the basic clock signal S301 from clock source 310 as an input signal (correspondingly, the CPN terminals of subsequent flip-flops receive the clock drive signal S304 from the output of the second delay submodule in the previous stage clock drive circuit as input signals), and provides the pulse signal S302 at the output terminal Q to one input terminal of delay module 340-1 and combinational logic module 350-1 (in this embodiment, a NAND gate). The first delay submodule 341-1 in delay module 340-1 inverts and delays the pulse signal S302 to obtain the feedback pulse signal S303, and provides it to the RESET terminal of flip-flop 330-1 and the other input terminal of combinational logic module 350-1. The second delay submodule 342-1 in delay module 340-1 inverts and delays the pulse signal S302 to obtain the clock drive signal S304, and outputs it to the next stage clock drive circuit as the input signal of the next stage clock drive circuit. The combinational logic module 350-1 receives signals S302 and S303 as inputs to obtain the output pulse clock signal S305, and outputs the pulse clock signal S305 to the arithmetic stage 301-N.
[0083] After the entire system is powered on, before the clock source 310 outputs the basic clock signal S301, the pulse signal S302 at the output terminal Q of the flip-flop 330-1 will stabilize at a low level. The output signal S303 of the first delay submodule 341-1 will stabilize at a high level, that is, the RESET terminal of the flip-flop 330-1 will be at a high level, and the input signal of the next stage clock drive circuit will also be at a high level (corresponding to the input signal S301 of the first stage clock drive circuit 320-1). Therefore, the input signals of the combinational logic module 350-1 (NAND gate) are low level (S302) and high level (S303), respectively, and its output pulse clock signal S305 is at a high level.
[0084] At time t1, clock source 310 begins outputting the basic clock signal S301. The period of the basic clock signal S301 is T.
[0085] like Figure 3B As shown, when signal S301 changes from high to low, the falling edge of the CPN terminal of flip-flop 330-1 arrives, and the RESET terminal signal (S303) remains high. This causes the output Q signal S302 of flip-flop 330-1 to become the signal value of the D terminal, i.e., high. Therefore, the input signals of combinational logic module 350-1 (NAND gate) are high (S302) and high (S303), respectively, and its output pulse clock signal S305 becomes low.
[0086] After time T1, at time t2, the output signal S303 of the first delay submodule 341-1 goes low. T1 is the delay between signal S303 and signal S302, determined by the configuration of the first delay submodule 341-1. Figure 3A In the embodiment shown, T1 is the sum of the delay times of the multiple inverters in the first delay submodule 341-1.
[0087] Therefore, as Figure 3B As shown, on one hand, the RESET terminal of flip-flop 330-1 goes low, causing the output signal S302 of flip-flop 330-1 to go low. On the other hand, the input signals of combinational logic module 350-1 (NAND gate) are low (S302) and low (S303), respectively, and its output pulse clock signal S305 goes high.
[0088] After T1, at time t3, the output signal S303 of the first delay submodule 341-1 becomes high.
[0089] Therefore, as Figure 3B As shown, on one hand, the RESET terminal of flip-flop 330-1 goes high, but there is no falling edge at the CPN terminal yet, so the output Q signal S302 of flip-flop 330-1 remains low. On the other hand, the input signals of combinational logic module 350-1 (NAND gate) are low (S302) and high (S303), respectively, and its output pulse clock signal S305 remains high.
[0090] On the other hand, from time t1 (when signal S302 goes high) for a period of time T2, the output signal S304 of the second delay submodule 342-1 goes low. Then, from time t2 (when signal S302 goes low) for another period of time T2, the output signal S304 of the second delay submodule 342-1 goes high. T2 is the delay between signals S304 and S302, determined by the configuration of the second delay submodule 342-1. Figure 3A In the embodiment shown, T2 is the sum of the delay times of the multiple inverters in the second delay submodule 342-1.
[0091] After this, the values of signals S302, S303, S304, and S305 remain unchanged. The next cycle of the basic clock signal S301 begins at time t4. From time t1 to time t4, one cycle T of the basic clock signal S301 is elapsed.
[0092] At time t4, signal S301 goes low.
[0093] like Figure 3BAs shown, when signal S301 changes from high to low, a falling edge arrives at the CPN terminal of flip-flop 330-1, causing signal S302 at the output terminal Q of flip-flop 330-1 to go high. Consequently, the pulse clock signal S305 at the output terminal of combinational logic module 350-1 (NAND gate) goes low.
[0094] After T1, at time t5, the output signal S303 of the first delay submodule 341-1 goes low.
[0095] Therefore, as Figure 3B As shown, on one hand, the RESET terminal of flip-flop 330-1 goes low, causing the signal S302 at the output terminal Q of flip-flop 330-1 to go low. On the other hand, the pulse clock signal S305 at the output terminal of combinational logic module 350-1 goes high.
[0096] After T1, at time t6, the output signal S303 of the first delay submodule 341-1 goes high.
[0097] Therefore, as Figure 3B As shown, the output Q signal S302 of the flip-flop 330-1 remains low, and the pulse clock signal S305 at the output of the combinational logic module 350-1 remains high.
[0098] On the other hand, starting from time t4 (when signal S302 goes high), after time T2, the output signal S304 of the second delay submodule 342-1 goes low. Then, starting from time t5 (when signal S302 goes low), after time T2, the output signal S304 of the second delay submodule 342-1 goes high.
[0099] Thus, a pulse clock signal S305 with a period of T and a pulse width of T1 is generated at the output of the combinational logic module 350-1. This pulse clock signal S305 is provided to the corresponding operational stage 301-N as the operating clock.
[0100] Furthermore, a clock drive signal S304 is generated at the output of the second delay submodule 342-1 as the input signal for the next-stage clock drive circuit (equivalent to the input signal S301 of the first-stage clock drive circuit 320-1). The falling edge of the clock drive signal S304 is used to trigger the flip-flop of the next-stage clock drive circuit. For example... Figure 3B As shown, the falling edge of the clock drive signal S304 is delayed by T2 compared to the falling edge of the input signal S301. Correspondingly, the pulse clock signal generated by each stage of the clock drive circuit is delayed by T2 compared to the pulse clock signal generated by the previous stage of the clock drive circuit.
[0101] As described above, the pulse width of the pulse clock generated by the pipelined clock drive circuit according to the present invention is determined by the delay time T1 of the first delay submodule, while the delay between the pulse clocks of two adjacent operational stages is determined by the delay time T2 of the second delay submodule. In a preferred embodiment, the first delay submodule and the second delay submodule are composed of inverters. The longer the delay time, the more inverters are required. To further optimize the circuit and reduce the number of inverters used, the present invention provides an improved delay module.
[0102] Figure 4 A schematic diagram of a delay module 440 of a pipeline clock drive circuit according to an embodiment of the present invention is shown.
[0103] The input of delay module 440 is coupled to a pulse signal S402 output by a flip-flop (not shown). Delay module 440 includes a first delay submodule 441 and a second delay submodule 442. The first delay submodule 441 delays signal S402 and feeds back the delayed pulse signal S403 as a feedback pulse signal to the flip-flop. The second delay submodule 442 delays signal S402 and outputs the delayed pulse signal S404 as a clock drive signal to the next-stage clock drive circuit. A portion of the multiple inverters constituting the first delay submodule 441 constitutes the second delay submodule 442, making the delay time T1 of the first delay submodule longer than the delay time T2 of the second delay submodule. In other embodiments, a portion of the multiple inverters constituting the second delay submodule can constitute the first delay submodule, making the delay time T2 of the second delay submodule longer than the delay time T1 of the first delay submodule.
[0104] exist Figure 4 The delay module 440 shown makes better use of the inverters in the circuit, reducing the number of inverters used.
[0105] In engineering practice, it is desirable to be able to flexibly adjust the delay of the delay module, thereby maximizing the operating frequency of the pipeline while meeting actual requirements for various parameters. To this end, this invention provides a further improved pipeline clock drive circuit, wherein the number of inverters constituting the delay module can be flexibly adjusted.
[0106] Figure 5 A schematic diagram of a delay module 540 of a pipeline clock drive circuit according to another embodiment of the present invention is shown.
[0107] The input of delay module 540 is coupled to the pulse signal S502 output by a flip-flop (not shown). Delay module 540 includes a first delay submodule 541 and a second delay submodule 542. The first delay submodule 541 delays signal S502 and feeds back the delayed pulse signal S503 as a feedback pulse signal to the flip-flop. The second delay submodule 542 delays signal S502 and outputs the delayed pulse signal S504 as a clock drive signal to the next-stage clock drive circuit.
[0108] The first delay submodule 541 and the second delay submodule 542 are each composed of multiple inverters and one or more data selectors. The one or more data selectors are configured such that the inverters in the first delay submodule 541 and the second delay submodule 542 form multiple signal paths, each signal path including a different number of inverters, and the number of inverters in each signal path in the first delay submodule 541 and the second delay submodule 542 is odd.
[0109] exist Figure 5 In the illustrated embodiment, the first delay submodule 541 consists of three data selectors forming four signal paths and several inverters, while the second delay submodule 542 consists of six data selectors forming sixteen signal paths and several inverters. Therefore, in Figure 5 In the illustrated embodiment, by switching the state of the data selector, the delay of signals S503 and S504 relative to signal S502 can be adjusted respectively, thereby adjusting the pulse width of the generated clock pulse signal and the delay between the clock pulse signals of two adjacent operational stages.
[0110] This allows for flexible and convenient adjustment of the delay module's delay according to actual work requirements, thereby improving the chip's efficiency and accuracy.
[0111] In a preferred embodiment, the first delay submodule 541 (represented by dashed lines) and the second delay submodule 542 (represented by dotted lines) may jointly include a common delay submodule 543 (represented by solid lines), which is composed of multiple inverters and one or more data selectors. At least one of the first delay submodule 541 and the second delay submodule 542 further includes multiple inverters connected in series with the common delay submodule 543. Figure 5 In the illustrated embodiment, the common delay submodule 543 consists of 12 inverters and 4 data selectors, and the first delay submodule 541 and the second delay submodule 542 each further include multiple inverters connected in series with the common delay submodule 543. This makes better use of the inverters and data selectors in the circuit, reducing the number of circuit components used.
[0112] Figure 5 The configuration of delay module 540 shown is merely illustrative. In other embodiments, delay module 540, its first delay submodule 541, and its second delay submodule 542 (and optional common delay submodule 543) can be configured with any suitable number of inverters and data selectors in any suitable configuration to form multiple signal paths, such that each signal path includes an appropriate number of inverters. In a preferred embodiment, the number of inverters in each signal path is different.
[0113] The computing circuit according to this disclosure can be implemented in various suitable ways, such as software, hardware, or a combination of software and hardware. In one implementation, a computing chip may include one or more of the above-described pipelined clock drive circuits. In one implementation, a computing board may include one or more computing chips. In one implementation, a computing device may include one or more computing boards. Multiple computing boards can execute computing tasks in parallel.
[0114] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0115] It should also be understood that when the term "includes / contains" is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.
[0116] While specific embodiments of the invention have been illustrated in detail by way of example, those skilled in the art should understand that the examples are intended to be illustrative only and do not limit the scope of the invention. It should be understood that the embodiments described above can be modified without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims
1. A pipeline clock driving circuit for providing pulse clock signals to a pipeline including multiple operational stages, the pipeline clock driving circuit comprising: A multi-stage clock drive circuit, wherein each stage of the clock drive circuit is used to provide a pulse clock signal to a corresponding one of the multiple operational stages in the pipeline; as well as The clock source, coupled to the input of the first-stage clock driver circuit, is used to provide the basic clock signal. In the multi-stage clock driving circuit, the inputs of all clock driving circuits except the first-stage clock driving circuit are coupled to the output of the previous-stage clock driving circuit, and Each stage of the clock drive circuit includes: A flip-flop, coupled to the input of the clock drive circuit at this level; The delay module includes a first delay submodule, which is coupled to the output of the flip-flop and delays the pulse signal output by the flip-flop, feeding the delayed pulse signal back to the flip-flop as a feedback pulse signal; and A combinational logic module, coupled to the outputs of a flip-flop and a first delay submodule, performs combinational logic operations on the pulse signal output by the flip-flop and the feedback pulse signal output by the first delay submodule to generate a pulse clock signal to be provided to a corresponding operation stage in the pipeline. In the multi-stage clock driving circuit, except for the last stage clock driving circuit, the delay module also includes a second delay sub-module. The second delay sub-module is coupled to the output of the flip-flop and delays the pulse signal output by the flip-flop, and outputs the delayed pulse signal as a clock driving signal to the next stage clock driving circuit.
2. The pipelined clock drive circuit as described in claim 1, wherein the flip-flop is a rising edge flip-flop.
3. The pipelined clock drive circuit as described in claim 2, wherein the combinational logic module is an OR gate or a NOR gate.
4. The pipelined clock drive circuit as described in claim 1, wherein the flip-flop is a falling edge flip-flop.
5. The pipelined clock drive circuit as described in claim 4, wherein the combinational logic module is an AND gate or a NAND gate.
6. The pipelined clock drive circuit according to any one of claims 1-5, wherein the first delay submodule and the second delay submodule are each composed of an odd number of inverters.
7. The pipelined clock drive circuit as claimed in claim 6, wherein a portion of the plurality of inverters constituting the first delay submodule constitutes the second delay submodule, or a portion of the plurality of inverters constituting the second delay submodule constitutes the first delay submodule.
8. The pipelined clock drive circuit as described in any one of claims 1-5, wherein the first delay submodule and the second delay submodule are respectively composed of a plurality of inverters and one or more data selectors, wherein the one or more data selectors are configured such that the inverters in the first delay submodule and the second delay submodule respectively form a plurality of signal paths, wherein each signal path includes a different number of inverters, and the number of inverters in each signal path in the first delay submodule and the second delay submodule is an odd number.
9. The pipelined clock drive circuit as claimed in claim 8, wherein the first delay submodule and the second delay submodule together include a common delay submodule, the common delay submodule being composed of a plurality of inverters and one or more data selectors, and at least one of the first delay submodule and the second delay submodule further includes a plurality of inverters connected in series with the common delay submodule.
10. A computing chip comprising one or more pipelined clock drive circuits as described in any one of claims 1-9.
11. A computing board comprising one or more computing chips as described in claim 10.
12. A computing device comprising one or more computing boards as described in claim 11.
Citation Information
Patent Citations
Pipeline clock driving circuit, computing chip, computing power board and computing equipment
CN220154843U