A method for calibrating a flash memory data path

Abstract

The present invention provides a method for flash memory data path calibration, a read calibration method, including a read calibration process and a write calibration process. A page standard data is pre-written; during system operation, read calibration is preferentially performed, and P_read is read every once in a while. When reading P_read, the length of P_read is equally divided into N parts, and different X_read parameters are used for each part during reading. The read data is compared with the standard data, and the X_read parameter with the smallest number of error bits is selected as the X_read parameter for subsequent system operation. If the smallest number of error bits is greater than the set threshold, X_read is not updated and the write calibration process is entered. The write calibration process first erases B_data, performs a write process on the X_write parameter. After each write is completed, the X_read with the smallest number of error bits is obtained using the read calibration method. If the number of error bits is less than the threshold Y, the entire write calibration process is exited, and X_write and X_read are updated as the physical layer parameters for subsequent system operation. The present invention improves the data stability of flash memory access.

Description

Technical Field

[0001] The present invention relates to a method for calibrating a flash memory data path, belonging to the technical field of data storage. Background Art

[0002] The interface frequency of NAND Flash access is getting higher and higher, and the data access rate is getting faster and faster. Therefore, the requirement for the transmission stability of the data path is getting stricter. The access of data requires the flash memory controller to adjust the parameters of the physical layer (PHY) to achieve stable data transmission. In practical applications, different flash memory particles correspond to different parameters of the physical layer of the flash memory controller. The same flash memory particles may also have differences in the parameters of the physical layer of the flash memory controller due to different processes of the flash memory controller. In addition, other factors such as temperature and voltage will also affect the parameter settings of the same device. A method for adjusting the parameters of the physical layer of the flash memory controller is needed to achieve online adjustment of the parameters and improve the data stability of flash memory data access. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for calibrating a flash memory data path to improve the data stability of flash memory access.

[0004] To achieve the above purpose, the present invention is realized through the following technical solutions:

[0005] Pre-write a page standard data P_read in the SLC block and record the value of P_read as 0;

[0006] The read calibration process is as follows:

[0007] 1) Read the P_read data of the SLC block every period of time T. After the calibration process ends, P_read will be updated;

[0008] 2) When reading P_read, divide the length of P_read into N equal parts. Each part uses different X_read parameters when reading. The X_read parameter is the read dqs delay in the parameters of the physical layer of the flash memory controller. Set the initial physical layer parameter X_read as X_read - S_read*(n - 1) / 2, where n is the count value, and set the step size of each adjustment of the X_read parameter as S_read.

[0009] 3) Compare the read data with the standard data every time it is read, count the number of error bits M_n of each part of the data, and find the minimum value of the number of error bits M_min.

[0010] 4) Determine whether M_min is less than the threshold Y. If so, select the X_read parameter with the smallest number of error bits as the X_read parameter for subsequent system operation; if the smallest number of error bits is greater than the set threshold Y, do not update X_read and enter the write calibration process;

[0011] The write calibration process is as follows:

[0012] 1) Erase the SLC block and set the adjustment step size to S_write.

[0013] 2) Set the write page number P_write to 0, set the count value n to 1, and increase X_write by S_write;

[0014] 3) Configure with the current X_write parameter, where the X_write parameter is the writeclock delay of the flash controller physical layer. Write the standard data to P_write, and then execute the read calibration process to obtain M_min. Determine whether M_min is less than the threshold Y. If so, update P_read to P_write, update X_write to the X_write corresponding to the current M_min; update X_read to the X_read corresponding to the current M_min, and then end the write calibration process; if not, continue with the following steps:

[0015] Set P_write to increase by 1, set the count value n to increase by 1, and determine the parity of P_write. If it is odd, subtract from X_write, and then execute step 3; if it is even, add to X_write, and then execute step 3.

[0016] Preferably, before calibration, select a block from the reserved blocks as the SLC block, and select the data stored in the SLC block as the standard data source.

[0017] The advantages of the present invention are as follows: This application can complete the read and write calibration of the flash data path without system downtime, so that the read and write parameters of the flash controller are always the best values, improving the data stability of flash access. Compared with the traditional empirical value setting, this method takes into account the parameter differences caused by the individual differences of the system, improving the stability of system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation to the present invention.

[0019] Figure 1This is a schematic diagram of the process structure of the present invention. Specific embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] Flash access mainly refers to the read and write of flash memory. The corresponding physical layer parameters of the flash controller mainly include read dqs delay and write clock delay. In the present invention, X_read is used to represent read dqs delay, and X_write is used to represent write clock delay.

[0022] The present invention is described by taking 3D TLC NAND Flash as an example. First, select a block (B_data) from the reserved blocks as an SLC block for use. Since the SLC block has good stability and the data stored in the NAND Flash is not likely to undergo bit flipping, it is selected as the source of standard data. Write a page of standard data in the SLC block in advance and record the P_read value as 0.

[0023] Then, during the operation of the system, read calibration is preferentially performed. Every period of time (T), read the page (P_read) of the SLC block (B_data). After the calibration process is completed, P_read will be updated. When reading P_read, divide the length of P_read into N equal parts, and use different X_read parameters for each part during reading. Assume that the step size of each adjustment of X_read is S_read. The X_read parameters corresponding to the N readings are X_read - S_read * ( ), X_read - S_read * ( ), …, X_read - S_read, X_read, X_read + S_read, …, X_read + S_read * ( ), X_read + S_read * ( ). After the reading is completed, compare the N pieces of data with the standard data in turn, count the number of error bits M_n of each piece of data, and finally select the X_read parameter with the smallest number of error bits as the X_read parameter for the subsequent system operation. If the smallest number of error bits is greater than the set threshold Y, do not update X_read and enter the write calibration process.

[0024] The write calibration process first erases B_data, and then, with an adjustment step size of S_write each time, for the X_write parameter, it first increases by S_write and writes to page0 of the B_data block, then decreases X_write by S_write and writes to page1, then increases X_write by 2 times S_write and writes to page2, and then decreases X_write by 2 times S_write and writes to page3, and so on. After each write is completed, the X_read with the minimum number of error bits is obtained using the read calibration method. If the number of error bits is less than the threshold Y, the entire write calibration process is exited, the page number at this time is updated to P_read, and at the same time, X_write and X_read are updated for use as the physical layer parameters for the subsequent operation of the system.

[0025] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for calibrating a flash memory data path, characterized in that, it includes a read calibration process and a write calibration process, specifically as follows: Pre-write a page standard data P_read in the SLC block and record the value of P_read as 0; The read calibration process is as follows: 1) Read the P_read data of the SLC block every period of time T. After the calibration process ends, P_read will be updated; 2) When reading P_read, divide the length of P_read into N equal parts. Each part uses different X_read parameters during reading. The X_read parameter is the read dqs delay in the physical layer parameters of the flash memory controller. Set the initial physical layer parameter X_read as X_read - S_read*(n - 1) / 2, where n is the count value, and set the step size of each adjustment of the X_read parameter as S_read. 3) Compare the read data with the standard data each time it is read, count the number of error bits M_n of each part of the data, and find the minimum value of the number of error bits M_min. 4) Judge whether M_min is less than the threshold Y. If so, select the X_read parameter with the minimum number of error bits as the X_read parameter used for the subsequent system operation; if the minimum number of error bits is greater than the set threshold Y, do not update X_read and enter the write calibration process. The write calibration process is as follows: 1) Erase the SLC block and set the adjustment step size as S_write. 2) Set the write page number P_write as 0, set the count value n as 1, and increase X_write by S_write. 3) Configure with the current X_write parameter. The X_write parameter is the writeclock delay in the physical layer parameters of the flash memory controller. Write the standard data to P_write, and then execute the read calibration process to obtain M_min; judge whether M_min is less than the threshold Y. If so, update P_read to P_write, update X_write to the X_write corresponding to the current M_min; update X_read to the X_read corresponding to the current M_min, and then end the write calibration process; if not, continue with the following steps: Set P_write to increment by 1, set the count value n to increment by 1, and determine the parity of P_write. If it is odd, subtract from X_write , and then execute step 3; if it is even, add to X_write , and then execute step 3.

2. The method for calibrating a flash memory data path according to claim 1, characterized in that, Before calibration, select a block as the SLC block from the reserved blocks, and select the data stored in the SLC block as the standard data source.

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