Memory controller, memory access system, electronic device and memory training method

Abstract

The present invention provides a memory controller, a memory access system, an electronic device, and a memory training method. The memory controller includes: a first sampling module for continuously sampling a first reference signal sent by a memory chip and determining whether sampling has failed based on the sampled data while the memory controller is reading data from the memory chip, wherein the period and initial phase of the first reference signal are the same as those of a first data signal, and the first reference signal has a dynamically configured phase compensation value; a first phase offset determination module for determining a first phase offset between a middle position of a normal sampling interval of the first reference signal and a jump position of a first selection signal based on the phase compensation value configured when sampling of the first reference signal fails; and a first phase compensation module for performing phase compensation on the first data signal based on the first phase offset, so that the middle position of the first data signal is aligned with the jump position of the first selection signal.

Description

Technical Field

[0001] The present invention relates to the field of memory training technology, and in particular to a memory controller, a memory access system, an electronic device, and a memory training method. Background Art

[0002] In existing memory access systems, the memory controller and memory chip are connected via a memory bus, which mainly includes at least one data signal line and a strobe signal line. Each data signal line can transmit a data signal. In this application, DQ is used to represent the data signal, which is the abbreviation of the data signal defined in the DDR protocol. The strobe signal line can transmit a data strobe pulse signal. In this application, DQS is used to represent the data strobe pulse signal, which is the abbreviation of the data strobe pulse signal defined in the DDR protocol. DQ and DQS are both periodic signals, and they generally have the same cycle length.

[0003] When accessing data from a memory chip, the memory controller transmits data via DQ and DQS. When writing data to a memory chip, the memory controller sends DQ and DQS to the memory chip. The DQ carries the data the memory controller wants to write to the memory chip, and the DQS triggers the memory chip to identify the DQ level and write the data to the memory chip. Conversely, when reading data from a memory chip, the memory chip sends DQ and DQS to the memory controller, and the memory controller collects DQ data based on the DQS.

[0004] According to the operating principles of DQ and DQS, the DQ receiver collects the instantaneous level state of DQ as data when DQS transitions. To ensure sufficient DQ timing margin, the ideal operating state is to align the middle position of DQ with the transition position of DQS. This allows the DQ receiver to have a low bit error rate, thereby ensuring the accuracy of data transmission. Therefore, adjusting the phase position of DQS and DQ, namely memory training, has become a common strategy for improving memory reliability. Existing memory training methods require the use of data signal lines to transmit training data. Therefore, applications cannot access memory during memory training, which affects memory access performance. Summary of the Invention

[0005] In view of this, the present invention provides a memory controller, a memory access system, an electronic device, and a memory training method.

[0006] In a first aspect, the present invention provides a memory controller, comprising:

[0007] a first sampling module, configured to continuously sample a first reference signal sent by the memory chip and determine whether sampling has failed based on the sampled data while the memory controller is reading data from the memory chip, wherein a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller;

[0008] a first phase offset determining module, configured to determine, based on a phase compensation value configured when sampling of the first reference signal fails, a first phase offset between a middle position of a normal sampling interval of the first reference signal and a jump position of a first strobe signal, where the first strobe signal is a strobe signal sent by the memory chip to the memory controller;

[0009] The first phase compensation module is configured to perform phase compensation on the first data signal according to the first phase offset, so that a middle position of the first data signal is aligned with a jump position of the first selection signal.

[0010] Optionally, a first phase shift module is further included, configured to configure different phase compensation values ​​for the first reference signal when the memory controller reads data from the memory chip.

[0011] Optionally, the first phase shifting module is configured to configure different first compensation values ​​for the first reference signal so that the first reference signal shifts to different phases in a first direction until sampling of the first reference signal fails, and is configured to configure different second compensation values ​​for the first reference signal so that the first reference signal shifts to different phases in a second direction until sampling of the first reference signal fails, wherein the first direction and the second direction are two opposite directions;

[0012] The first phase offset determination module is used to determine the first phase offset between the middle position of the normal sampling interval of the first reference signal and the jump position of the first selection signal based on the first compensation value and the second compensation value configured when the sampling of the first reference signal fails.

[0013] Optionally, the first phase shift module is used to increase the first compensation value of the first reference signal according to a set step size each time the first selection signal jumps, so that the first reference signal is shifted right in sequence according to the set step size until the first reference signal sampling fails, and to reduce the second compensation value of the first reference signal according to a set step size each time the first selection signal jumps, so that the first reference signal is shifted left in sequence according to the set step size until the first reference signal sampling fails.

[0014] In a second aspect, the present invention provides a memory controller, comprising:

[0015] a first driver module, configured to send a second reference signal to the memory chip during a process in which the memory controller writes data to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling fails based on the sampled data, wherein a period of the second reference signal is the same as a period of the second data signal, an initial phase of the second reference signal is aligned with an initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent by the memory controller to the memory chip;

[0016] a second phase offset determining module, configured to determine, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a jump position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip;

[0017] The second phase compensation module is configured to perform phase compensation on the second data signal according to the second phase offset, so that a middle position of the second data signal is aligned with a jump position of the second selection signal.

[0018] Optionally, a second phase shift module is further included, configured to configure different phase compensation values ​​for the second reference signal when the memory controller writes data to the memory chip.

[0019] Optionally, the second phase shifting module is configured to configure different third compensation values ​​for the second reference signal so that the second reference signal is shifted to different phases in a first direction until sampling of the second reference signal fails, and is configured to configure different fourth compensation values ​​for the second reference signal so that the second reference signal is shifted to different phases in a second direction until sampling of the second reference signal fails, wherein the first direction and the second direction are two opposite directions;

[0020] The second phase offset determination module is used to determine the second phase offset between the middle position of the normal sampling interval of the second reference signal and the jump position of the second selection signal based on the third compensation value and the fourth compensation value configured when the sampling of the second reference signal fails.

[0021] Optionally, the second phase shift module is used to increase the third compensation value of the second reference signal according to a set step size each time the second selection signal jumps, so that the second reference signal is shifted right in sequence according to the set step size until the sampling of the second reference signal fails, and to reduce the fourth compensation value of the second reference signal according to the set step size each time the second selection signal jumps, so that the second reference signal is shifted left in sequence according to the set step size until the sampling of the second reference signal fails.

[0022] In a third aspect, the present invention provides a memory access system, comprising the memory controller and memory chip provided in the first aspect, and a signal line for transmitting a signal between the memory controller and the memory chip, wherein the signal line comprises:

[0023] a data signal line, configured to transmit the first data signal;

[0024] a strobe signal line for transmitting the first strobe signal, and

[0025] The reference signal line is used to transmit the first reference signal.

[0026] In a fourth aspect, the present invention provides a memory access system, comprising the memory controller and memory chip provided in the second aspect, and a signal line for transmitting a signal between the memory controller and the memory chip, wherein the signal line comprises:

[0027] a data signal line, configured to transmit the second data signal;

[0028] a strobe signal line for transmitting the second strobe signal, and

[0029] The reference signal line is used to transmit the second reference signal.

[0030] In a fifth aspect, the present invention provides an electronic device, comprising the memory access system provided in the third aspect or the fourth aspect.

[0031] In a sixth aspect, the present invention provides a memory training method, applied to a memory controller, the memory training method comprising:

[0032] During a process in which the memory controller reads data from the memory chip, the memory controller continuously samples a first reference signal sent by the memory chip and determines whether sampling fails based on the sampled data, wherein a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller;

[0033] determining, based on a phase compensation value configured when sampling of the first reference signal fails, a first phase offset between a middle position of a normal sampling interval of the first reference signal and a transition position of a first strobe signal, where the first strobe signal is a strobe signal sent by a memory chip to a memory controller;

[0034] Phase compensation is performed on the first data signal according to the first phase offset, so that a middle position of the first data signal is aligned with a jump position of the first selection signal.

[0035] In a seventh aspect, the present invention provides a memory training method applied to a memory controller, the memory training method comprising:

[0036] During a process in which the memory controller writes data to the memory chip, the memory controller sends a second reference signal to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling fails based on the sampled data, wherein a period of the second reference signal is the same as a period of the second data signal, an initial phase of the second reference signal is aligned with an initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent by the memory controller to the memory chip;

[0037] determining, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a transition position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip;

[0038] Phase compensation is performed on the second data signal according to the second phase offset, so that a middle position of the second data signal is aligned with a jump position of the second selection signal.

[0039] The memory controller provided by the present invention uses corresponding reference signals to perform memory training during the process of the memory controller reading data from the memory chip and during the process of the memory controller writing data to the memory chip. Compared with the existing technology, the memory training is performed using reference signals, and the memory training and memory access do not interfere with each other. The memory training can be continuously performed while the memory chip is working, making the memory chip work more stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic structural diagram of a memory controller according to an embodiment of the present invention;

[0041] Figure 2 A schematic structural diagram of a memory controller according to an embodiment of the present invention;

[0042] Figure 3Schematic diagram of an ideal sampling state of a data signal according to an embodiment of the present invention;

[0043] Figure 4 A schematic diagram illustrating a phase shift between a reference signal and a data signal relative to a strobe signal according to an embodiment of the present invention;

[0044] Figure 5 A schematic structural diagram of a memory controller according to an embodiment of the present invention;

[0045] Figure 6 A schematic structural diagram of a memory controller according to an embodiment of the present invention;

[0046] Figure 7 A schematic structural diagram of a memory access system according to an embodiment of the present invention;

[0047] Figure 8 A schematic structural diagram of a memory access system according to an embodiment of the present invention;

[0048] Figure 9 FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0052] An embodiment of the present invention provides a memory controller, such as Figure 1As shown, the memory controller includes:

[0053] a first sampling module 101, configured to continuously sample a first reference signal sent by the memory chip and determine whether sampling has failed based on the sampled data while the memory controller is reading data from the memory chip, wherein the period of the first reference signal is the same as the period of the first data signal, the initial phase of the first reference signal is aligned with the initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller;

[0054] A first phase offset determining module 102 is configured to determine a first phase offset between a middle position of a normal sampling interval of the first reference signal and a transition position of a first strobe signal based on a phase compensation value configured when sampling of the first reference signal fails, where the first strobe signal is a strobe signal sent by the memory chip to the memory controller;

[0055] The first phase compensation module 103 is configured to perform phase compensation on the first data signal according to the first phase offset, so that the middle position of the first data signal is aligned with the jump position of the first selection signal.

[0056] Specifically, when the memory controller reads data from the memory chip, the memory chip is the transmitter and the memory controller is the receiver. The memory chip sends a first data signal DQ and a first select signal DQS to the memory controller. It should be noted that in this application, the select signal DQS is the data select pulse signal DQS, and the two have the same meaning.

[0057] During this process, the memory chip also sends a first reference signal to the memory controller. The first sampling module 101 continuously samples the first reference signal according to the first selection signal and determines whether the sampling has failed based on the sampled data. Specifically, the first sampling module 101 collects the instantaneous level of the first reference signal as data when the first selection signal transitions.

[0058] If two consecutive identical data appear in the sampled data of the first reference signal, such as two consecutive 0s or two consecutive 1s, the first reference signal sampling fails. The phase compensation value at this time is a critical state for normal sampling of the first reference signal. The first sampling module 101 records the phase compensation value of the current first reference signal configuration.

[0059] After a sampling failure, the first sampling module 101 can notify the first phase offset determination module 102, for example by issuing a specific sampling feedback signal to notify the first phase offset determination module 102 of the sampling failure. At this point, the first phase offset determination module 102 needs to obtain the phase compensation value configured when the sampling of the first reference signal failed, and, based on the phase compensation value configured when the sampling of the first reference signal failed, determine the first phase offset between the middle position of the first reference signal's normal sampling interval and the transition position of the first selection signal. After determining the first phase offset, the first phase compensation module 103 performs phase compensation on the first data signal based on the first phase offset, aligning the middle position of the first data signal with the transition position of the first selection signal.

[0060] As an implementation method, Figure 2 As shown, the memory controller includes a first phase shift module 100 for configuring different phase compensation values ​​for a first reference signal during the process of the memory controller reading data from a memory chip. The first phase shift module 100 can be used to dynamically configure the phase compensation value of the first reference signal.

[0061] Furthermore, in one embodiment, the first phase shifting module 100 is configured to configure different first compensation values ​​for the first reference signal so that the first reference signal is shifted in a first direction with different phases until sampling of the first reference signal fails, and configured to configure different second compensation values ​​for the first reference signal so that the first reference signal is shifted in a second direction with different phases until sampling of the first reference signal fails, wherein the first direction and the second direction are two opposite directions;

[0062] The first phase offset determining module 102 is configured to determine a first phase offset between a middle position of a normal sampling interval of the first reference signal and a jump position of the first selection signal based on a first compensation value and a second compensation value configured when sampling of the first reference signal fails.

[0063] Furthermore, in one embodiment, the first phase shift module 100 is configured to increase the first compensation value of the first reference signal according to a set step size each time the first selection signal jumps, so that the first reference signal is sequentially shifted right according to the set step size until the first reference signal sampling fails, and to reduce the second compensation value of the first reference signal according to the set step size each time the first selection signal jumps, so that the first reference signal is sequentially shifted left according to the set step size until the first reference signal sampling fails.

[0064] It should be noted that during the phase shifting process, the increment or decrement step size (also referred to as granularity) of the first reference signal can be configured by the memory controller as needed. The sampling of the reference signal does not affect the sampling of the data signal.

[0065] Assuming that the first compensation value configured when the first reference signal sampling fails is A, and the second compensation value configured when the sampling fails is B, the expression of the first phase offset is: (A+B) / 2–A.

[0066] It is also understandable that after compensating the first data signal according to the first phase offset, the first reference signal is also synchronously compensated. In this way, the first data signal and the first reference signal are always phase-aligned, and memory training can be continuously implemented during subsequent memory accesses.

[0067] The following is a specific example to illustrate the memory training process of the memory controller.

[0068] Figure 3 This is a schematic diagram of the ideal sampling state of the data signal DQ. Figure 3 As shown, clk is the memory chip clock, DQS is the data strobe pulse signal, DQ+0 is the data signal of the initial phase, ref+0 is the reference signal of the initial phase, the reference signal ref and the data signal are both periodically alternating high and low level signals with the same period and initial phase alignment. Figure 3 In the example, the middle position of the data signal DQ is aligned with the transition position of the selection signal DQS, which is an ideal sampling state and does not require compensation for the reference signal ref and the data signal.

[0069] Figure 4 This is a schematic diagram of a situation where the data signal is phase-shifted relative to the selection signal. In this case, when the selection signal DQS jumps, the sampling position of the data signal DQ is not in the middle of the data signal DQ (the black area of ​​the data signal in the figure represents the target area of ​​interest). Therefore, the goal of memory training is to compensate for the data signal DQ. The ultimate goal is to make the jump position of the selection signal DQS correspond to the middle position of the compensated data signal DQ.

[0070] The memory training process is briefly described as follows:

[0071] The initial phase of the reference signal ref is aligned with the initial phase of the data signal DQ;

[0072] The memory controller uses several clocks to shift the ref phase right by 0.3 (+0.3), and then sampling fails (for example, a clock shift of 0.1 requires three clocks for sampling failure).

[0073] The memory controller uses several clocks to shift the ref phase left by 0.7 (-0.7) and then sampling fails (similarly, if one clock shifts 0.1, it takes 7 clocks to fail sampling);

[0074] According to the expression (0.3+0.7) / 2-0.3=0.2, it can be concluded that the initial phase of ref has a phase offset of 0.2 to the right relative to the optimal sampling point. The initial phase of the data signal DQ is aligned with the initial phase of ref, so the initial phase of the data signal DQ has a phase offset of 0.2 to the right relative to the optimal sampling point.

[0075] Therefore, ideal sampling can be achieved by simply shifting the data signal DQ to the left by 0.2 phase based on the initial phase. Figure 4 The left-shifted DQ signal is not shown in FIG.

[0076] In the above discussion, 0.3 represents 0.3 clock cycles, 0.7 represents 0.7 clock cycles, and 0.2 represents 0.2 clock cycles.

[0077] The memory controller provided in an embodiment of the present invention performs memory training while the memory controller reads data from a memory chip. It continuously samples a first reference signal and, based on a phase compensation value configured when sampling of the first reference signal fails, determines a first phase offset between the middle position of a normal sampling interval of the first reference signal and the transition position of a first selection signal. Phase compensation is then performed on the first data signal based on the first phase offset to align the middle position of the first data signal with the transition position of the first selection signal. Compared to the prior art, memory training using the first reference signal allows for independent interference between memory training and memory access. This allows for continuous memory training while the memory chip is operating, resulting in more stable operation of the memory chip.

[0078] On the other hand, an embodiment of the present invention provides a memory controller, such as Figure 5 As shown, the memory controller includes:

[0079] A first driver module 500 is configured to send a second reference signal to the memory chip during a process in which the memory controller writes data to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling has failed based on the sampled data, wherein the period of the second reference signal is the same as the period of the second data signal, the initial phase of the second reference signal is aligned with the initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value. The second data signal is a data signal sent by the memory controller to the memory chip;

[0080] a second phase offset determining module 502, configured to determine, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a transition position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip;

[0081] The second phase compensation module 503 is configured to perform phase compensation on the second data signal according to the second phase offset, so that the middle position of the second data signal is aligned with the jump position of the second selection signal.

[0082] Specifically, when the memory controller writes data to the memory chip, the memory controller acts as the transmitter and the memory chip acts as the receiver. The memory controller sends a second data signal and a second selection signal to the memory chip. During this process, the memory controller also sends a second reference signal to the memory chip. The memory chip is equipped with a corresponding sampling module that continuously samples the second reference signal based on the second selection signal and determines whether sampling has failed based on the sampled data. Specifically, the memory chip collects the instantaneous level of the second reference signal as data when the second selection signal transitions.

[0083] When two consecutive identical data appear in the sampled data of the second reference signal, such as two consecutive 0s or two consecutive 1s, the second reference signal sampling fails. The memory chip records the phase compensation value of the current second reference signal configuration.

[0084] After the memory chip fails to sample, it can notify the second phase offset determination module 502 by, for example, issuing a specific sampling feedback signal to notify the second phase offset determination module 502 of the sampling failure. At this point, the second phase offset determination module 502 needs to obtain the phase compensation value configured when the second reference signal sampling failed, and, based on the phase compensation value configured when the second reference signal sampling failed, determine the second phase offset between the middle position of the second reference signal's normal sampling interval and the transition position of the second selection signal. After determining the second phase offset, the second phase compensation module 503 performs phase compensation on the second data signal based on the second phase offset, aligning the middle position of the second data signal with the transition position of the second selection signal.

[0085] As an implementation method, Figure 6 As shown, the memory controller includes a second phase shift module 501 for configuring different phase compensation values ​​for the second reference signal during the process of the memory controller writing data to the memory chip. The second phase shift module 501 can be used to make the second reference signal have a dynamically configured phase compensation value.

[0086] Furthermore, in one embodiment, the second phase shifting module 501 is configured to configure different third compensation values ​​for the second reference signal so that the second reference signal is shifted in a first direction with different phases until sampling of the second reference signal fails, and configured to configure different fourth compensation values ​​for the second reference signal so that the second reference signal is shifted in a second direction with different phases until sampling of the second reference signal fails, wherein the first direction and the second direction are two opposite directions;

[0087] The second phase offset determining module 502 is configured to determine a second phase offset between the middle position of the normal sampling interval of the second reference signal and the jump position of the second selection signal based on the third compensation value and the fourth compensation value configured when the second reference signal sampling fails.

[0088] Furthermore, in one embodiment, the second phase shift module 501 is configured to increase the third compensation value of the second reference signal according to a set step size each time the second selection signal jumps, so that the second reference signal is sequentially shifted right according to the set step size until the second reference signal sampling fails, and to reduce the fourth compensation value of the second reference signal according to the set step size each time the second selection signal jumps, so that the second reference signal is sequentially shifted left according to the set step size until the second reference signal sampling fails.

[0089] It should be noted that during the phase shifting process, the increment or decrement step size (also called granularity) of the second reference signal can be configured by the memory controller as needed. The sampling of the reference signal does not affect the sampling of the data signal.

[0090] Assuming that the third compensation value configured when the second reference signal sampling fails is A and the fourth compensation value configured when the sampling fails is B, the expression of the second phase offset is: (A+B) / 2–A.

[0091] It is also understandable that after compensating the second data signal according to the second phase offset, the second reference signal is also synchronously compensated. In this way, the second data signal and the second reference signal are always phase-aligned, and memory training can be continuously implemented during subsequent memory accesses.

[0092] For an exemplary description of the memory training process of the memory controller provided by an embodiment of the present invention, reference may be made to the description of the aforementioned embodiment, which will not be elaborated here.

[0093] The memory controller provided in an embodiment of the present invention performs memory training while the memory controller is writing data to a memory chip. A second reference signal is sent to the memory chip, which continuously samples the second reference signal. Based on a phase compensation value configured when the second reference signal sampling fails, the memory chip determines a second phase offset between the middle position of the second reference signal's normal sampling interval and the transition position of the second selection signal. Phase compensation is then performed on the second data signal based on the second phase offset to align the middle position of the second data signal with the transition position of the second selection signal. Compared to the prior art, memory training using a second reference signal allows for non-interference between memory training and memory access. Memory training can be performed continuously while the memory chip is operating, making the memory chip's operation more stable.

[0094] On the other hand, an embodiment of the present invention provides a memory access system, such as Figure 7 As shown, the memory access system includes a memory controller and a memory chip and a signal line for transmitting signals between the memory controller and the memory chip, wherein the memory controller is used to perform memory training in the process of reading data from the memory chip, and has the following features: Figure 1 or Figure 2 In the structure shown, the signal line includes:

[0095] A data signal line, configured to transmit a first data signal (eg, a DQ signal);

[0096] a strobe signal line for transmitting a first strobe signal (eg, a DOS signal), and

[0097] The reference signal line is used to transmit a first reference signal (eg, a ref signal).

[0098] On the other hand, an embodiment of the present invention provides a memory access system, such as Figure 8 As shown, the memory access system includes a memory controller and a memory chip and a signal line for transmitting signals between the memory controller and the memory chip, wherein the memory controller is used to perform memory training in the process of writing data to the memory chip, and has the following features: Figure 5 or Figure 6 In the structure shown, the signal line includes:

[0099] a data signal line, configured to transmit a second data signal (eg, a DQ signal);

[0100] a strobe signal line for transmitting a second strobe signal (eg, a DOS signal), and

[0101] The reference signal line is used to transmit a second reference signal (eg, a ref signal).

[0102] It is understandable that in actual work, a memory controller must work in both directions, acting as both a receiver and a transmitter, so it will also integrate Figure 1 or Figure 2 The structure shown, and Figure 5 or Figure 6 In addition, in one embodiment, from the perspective of circuit design, the first phase shifting module and the second phase shifting module with similar functions can be the same circuit. Similarly, the first phase deviation determining module and the second phase deviation determining module can be the same circuit, and the first phase compensation module and the second phase compensation module can be the same circuit.

[0103] Compared to existing technologies, the memory access system provided by the present invention adds a reference signal line between the memory controller and the memory chip to transmit a reference signal. The memory controller uses the reference signal to implement memory training. Memory training and memory access do not interfere with each other, allowing continuous memory training while the memory chip is operating, ensuring more stable operation.

[0104] On the other hand, an embodiment of the present invention provides an electronic device, such as Figure 9 As shown, the memory access system includes a processor and the above embodiment. The processor can send a command to the memory controller, and the memory controller uses the first reference signal or the second reference signal to perform memory training.

[0105] On the other hand, an embodiment of the present invention provides a memory training method applied to a memory controller, comprising the following steps:

[0106] During a process in which the memory controller reads data from the memory chip, the memory controller continuously samples a first reference signal sent by the memory chip and determines whether sampling fails based on the sampled data, wherein a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller;

[0107] determining, based on a phase compensation value configured when sampling of the first reference signal fails, a first phase offset between a middle position of a normal sampling interval of the first reference signal and a transition position of a first strobe signal, where the first strobe signal is a strobe signal sent by the memory chip to the memory controller;

[0108] Phase compensation is performed on the first data signal according to the first phase offset, so that the middle position of the first data signal is aligned with the jump position of the first selection signal.

[0109] The implementation process of the memory training method has been exemplified in the previous embodiment and will not be expanded here.

[0110] The memory training method provided in an embodiment of the present invention performs memory training while a memory controller reads data from a memory chip. The method continuously samples a first reference signal and, based on a phase compensation value configured when sampling of the first reference signal fails, determines a first phase offset between the middle position of the first reference signal's normal sampling interval and the transition position of a first selection signal. Phase compensation is then performed on the first data signal based on the first phase offset to align the middle position of the first data signal with the transition position of the first selection signal. Compared to existing technologies, memory training using the first reference signal allows for independent interference between memory training and memory access. This allows for continuous memory training while the memory chip is operating, resulting in more stable operation of the memory chip.

[0111] On the other hand, an embodiment of the present invention provides a memory training method applied to a memory controller, comprising the following steps:

[0112] During a process in which the memory controller writes data to the memory chip, a second reference signal is sent to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling fails based on the sampled data, wherein a period of the second reference signal is the same as a period of the second data signal, an initial phase of the second reference signal is aligned with an initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent by the memory controller to the memory chip;

[0113] determining, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a transition position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip;

[0114] Phase compensation is performed on the second data signal according to the second phase offset, so that the middle position of the second data signal is aligned with the jump position of the second selection signal.

[0115] The memory training method provided by an embodiment of the present invention performs memory training while a memory controller is writing data to a memory chip. A second reference signal is sent to the memory chip, which continuously samples the second reference signal. Based on a phase compensation value configured when the second reference signal sampling fails, a second phase offset is determined between the middle position of the second reference signal's normal sampling interval and the transition position of the second selection signal. Phase compensation is then performed on the second data signal based on the second phase offset to align the middle position of the second data signal with the transition position of the second selection signal. Compared to the prior art, memory training using a second reference signal does not interfere with memory training and memory access. Memory training can be performed continuously while the memory chip is operating, making the memory chip's operation more stable.

[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A memory controller, characterized in that: The memory controller includes: a first sampling module, configured to continuously sample a first reference signal sent by the memory chip and determine whether sampling has failed based on the sampled data while the memory controller is reading data from the memory chip, wherein a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller; a first phase offset determining module, configured to determine, based on a phase compensation value configured when sampling of the first reference signal fails, a first phase offset between a middle position of a normal sampling interval of the first reference signal and a jump position of a first strobe signal, where the first strobe signal is a strobe signal sent by the memory chip to the memory controller; The first phase compensation module is configured to perform phase compensation on the first data signal according to the first phase offset, so that a middle position of the first data signal is aligned with a jump position of the first selection signal.

2. The memory controller according to claim 1, wherein: It also includes a first phase shift module, which is used to configure different phase compensation values ​​for the first reference signal when the memory controller reads data from the memory chip.

3. The memory controller according to claim 2, wherein: The first phase shifting module is configured to configure different first compensation values ​​for the first reference signal so that the first reference signal shifts different phases in a first direction until sampling of the first reference signal fails, and is configured to configure different second compensation values ​​for the first reference signal so that the first reference signal shifts different phases in a second direction until sampling of the first reference signal fails, wherein the first direction and the second direction are two opposite directions; The first phase offset determination module is used to determine the first phase offset between the middle position of the normal sampling interval of the first reference signal and the jump position of the first selection signal based on the first compensation value and the second compensation value configured when the sampling of the first reference signal fails.

4. The memory controller according to claim 3, wherein: The first phase shift module is configured to increase the first compensation value of the first reference signal according to a set step size each time the first selection signal jumps, so that the first reference signal is sequentially shifted right according to the set step size until the first reference signal sampling fails, and to reduce the second compensation value of the first reference signal according to a set step size each time the first selection signal jumps, so that the first reference signal is sequentially shifted left according to the set step size until the first reference signal sampling fails.

5. A memory controller, characterized in that: The memory controller includes: a first driver module, configured to send a second reference signal to the memory chip during a process in which the memory controller writes data to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling fails based on the sampled data, wherein a period of the second reference signal is the same as a period of the second data signal, an initial phase of the second reference signal is aligned with an initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent by the memory controller to the memory chip; a second phase offset determining module, configured to determine, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a jump position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip; The second phase compensation module is configured to perform phase compensation on the second data signal according to the second phase offset, so that a middle position of the second data signal is aligned with a jump position of the second selection signal.

6. The memory controller according to claim 5, wherein: It also includes a second phase shift module, which is used to configure different phase compensation values ​​for the second reference signal when the memory controller writes data to the memory chip.

7. The memory controller according to claim 6, wherein: The second phase shifting module is configured to configure different third compensation values ​​for the second reference signal so that the second reference signal shifts different phases in a first direction until sampling of the second reference signal fails, and is configured to configure different fourth compensation values ​​for the second reference signal so that the second reference signal shifts different phases in a second direction until sampling of the second reference signal fails, wherein the first direction and the second direction are two opposite directions; The second phase offset determination module is used to determine the second phase offset between the middle position of the normal sampling interval of the second reference signal and the jump position of the second selection signal based on the third compensation value and the fourth compensation value configured when the sampling of the second reference signal fails.

8. The memory controller according to claim 7, wherein: The second phase shift module is configured to increase the third compensation value of the second reference signal according to a set step size each time the second selection signal jumps, so that the second reference signal is sequentially shifted right according to the set step size until the second reference signal sampling fails, and to reduce the fourth compensation value of the second reference signal according to the set step size each time the second selection signal jumps, so that the second reference signal is sequentially shifted left according to the set step size until the second reference signal sampling fails.

9. A memory access system, characterized in that: The memory access system comprises the memory controller and the memory chip according to any one of claims 1 to 4, and a signal line for transmitting a signal between the memory controller and the memory chip, wherein the signal line comprises: a data signal line, configured to transmit the first data signal; a strobe signal line for transmitting the first strobe signal, and The reference signal line is used to transmit the first reference signal.

10. A memory access system, characterized in that: The memory access system comprises the memory controller and the memory chip according to any one of claims 5 to 8, and a signal line for transmitting a signal between the memory controller and the memory chip, wherein the signal line comprises: a data signal line, configured to transmit the second data signal; a strobe signal line for transmitting the second strobe signal, and The reference signal line is used to transmit the second reference signal.

11. An electronic device, characterized in that: The electronic device comprises the memory access system according to claim 9 or 10.

12. A memory training method, characterized in that: Applied to a memory controller, the memory training method includes: During a process in which the memory controller reads data from the memory chip, the memory controller continuously samples a first reference signal sent by the memory chip and determines whether sampling fails based on the sampled data, wherein a period of the first reference signal is the same as a period of the first data signal, an initial phase of the first reference signal is aligned with an initial phase of the first data signal, and the first reference signal has a dynamically configured phase compensation value, and the first data signal is a data signal sent by the memory chip to the memory controller; determining, based on a phase compensation value configured when sampling of the first reference signal fails, a first phase offset between a middle position of a normal sampling interval of the first reference signal and a transition position of a first strobe signal, where the first strobe signal is a strobe signal sent by a memory chip to a memory controller; Phase compensation is performed on the first data signal according to the first phase offset, so that a middle position of the first data signal is aligned with a jump position of the first selection signal.

13. A memory training method, characterized in that: Applied to a memory controller, the memory training method includes: During a process in which the memory controller writes data to the memory chip, the memory controller sends a second reference signal to the memory chip, so that the memory chip continuously samples the second reference signal and determines whether sampling fails based on the sampled data, wherein a period of the second reference signal is the same as a period of the second data signal, an initial phase of the second reference signal is aligned with an initial phase of the second data signal, and the second reference signal has a dynamically configured phase compensation value, and the second data signal is a data signal sent by the memory controller to the memory chip; determining, based on a phase compensation value configured when sampling of the second reference signal fails, a second phase offset between a middle position of a normal sampling interval of the second reference signal and a transition position of a second strobe signal, where the second strobe signal is a strobe signal sent by the memory controller to the memory chip; Phase compensation is performed on the second data signal according to the second phase offset, so that a middle position of the second data signal is aligned with a jump position of the second selection signal.

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