Systems and methods for setting displayport configuration data (DPCD) registers

Abstract

The application provides a system and method for setting a display port configuration data (DPCD) register, the system comprising: a host computer, a field programmable gate array (FPGA) and a display panel, wherein an input port of the FPGA is connected with a serial interface of the host computer through a serial data bus, and an output port of the FPGA is connected with the display panel through an auxiliary channel; wherein the host computer is configured to send serial data through the serial data bus; wherein the serial data is a statement based on an auxiliary channel protocol; the FPGA is configured to process the received serial data to obtain a corresponding command statement, and send the command statement through the auxiliary channel; and the display panel is configured to receive the command statement and transmit the command statement into the DPCD register, so as to set the DPCD register. Thus, the system sets the DPCD register through the auxiliary channel based on the FPGA platform.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a system and method for setting the Display Port Configuration Data (DPCD) register. Background Technology

[0002] With the rapid development of economy and technology, display panel types are emerging in an endless stream to meet various application requirements. Currently, the most common display panels are based on dp (Display Port) and edp (Embedded Display Port) outputs. In addition to high data transmission rates, these display panels also have very few channels and an embedded clock frequency to reduce radio frequency interference. When debugging certain functions of these display panels, simply using hardware circuit design, such as pull-up to a voltage source or pull-down to ground, cannot meet user requirements. In this case, the user requirements can be met by setting the DPCD (Display Port Configuration Data) register in the TCON (Timing Controller) on the display panel. This avoids hardware operations on the display panel, which could damage it, and allows for quick, simple, and effective debugging of the display panel through software operations.

[0003] During the debugging of the display panel, it is often necessary to configure related settings. Some of these settings can only be achieved through the DPCD register, and currently there are very few tools that can directly configure the DPCD register. Therefore, how to configure the DPCD register is a problem that urgently needs to be solved. Summary of the Invention

[0004] The present invention aims to solve, to a certain extent, the technical problems in the related technologies.

[0005] Therefore, the first objective of this invention is to provide a system for setting the Display Port Configuration Data (DPCD) register, which is based on an FPGA platform and implements the setting of the DPCD register through an auxiliary channel.

[0006] The second objective of this invention is to provide a method for setting the Display Port Configuration Data DPCD Register.

[0007] To achieve the above objectives, a first aspect of the present invention provides a system for setting a Display Port Configuration Data (DPCD) register, comprising: a host computer, a Field Programmable Gate Array (FPGA), and a display panel. The input port of the FPGA is connected to the serial interface of the host computer via a serial data bus, and the output port of the FPGA is connected to the display panel via an auxiliary channel. The host computer is used to send serial data via the serial data bus; the serial data is a statement based on the auxiliary channel protocol. The FPGA processes the received serial data to obtain corresponding command statements and sends the command statements via the auxiliary channel. The display panel receives the command statements and transmits them to the DPCD register to set the DPCD register.

[0008] A system for setting the Display Port Configuration Data (DPCD) register according to an embodiment of the present invention comprises a host computer, a Field Programmable Gate Array (FPGA), and a display panel. The FPGA's input port is connected to the host computer's serial interface via a serial data bus, and the FPGA's output port is connected to the display panel via an auxiliary channel. The host computer sends serial data via the serial data bus, the serial data being statements based on the auxiliary channel protocol. The FPGA processes the received serial data to obtain corresponding command statements and sends these command statements via the auxiliary channel. The display panel receives the command statements and transmits them to the DPCD register to set the DPCD register. Thus, this system, based on an FPGA platform, achieves DPCD register setting via an auxiliary channel.

[0009] In addition, the system for setting the display port configuration data DPCD register according to the first aspect embodiment of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, the FPGA includes:

[0011] A receiving unit is configured to receive the serial data sent by the host computer and perform serial-to-parallel conversion on the serial data to generate multiple sets of parallel data with a set number of bits and a flag bit of the parallel data; wherein, the flag bit is used to indicate that the parallel data with the set number of bits is valid data.

[0012] An encoding unit is connected to the receiving unit and is used to encode the valid data; wherein, the encoding is to convert the valid data into the command statement transmitted through the auxiliary channel;

[0013] A storage unit is connected to the encoding unit. The storage unit is used to store the command statement and send the command statement to the display panel.

[0014] According to one embodiment of the present invention, the FPGA further includes:

[0015] A phase-locked loop (PLL) unit is connected to the receiving unit, the encoding unit, and the storage unit, respectively. The PLL unit is used to perform frequency multiplication and division processing on the external clock, providing a receiving clock signal to the receiving unit, an encoding clock signal to the encoding unit, and a write clock signal and a read clock signal to the storage unit, respectively.

[0016] Specifically, the receiving unit is used to receive the serial data based on the receiving clock signal;

[0017] The encoding unit is specifically used to encode the valid data based on the encoding clock signal;

[0018] The storage unit is specifically used to store the command statement based on the write clock signal and to read the stored command statement based on the read clock signal.

[0019] According to one embodiment of the present invention, the command statement includes:

[0020] Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

[0021] According to one embodiment of the present invention, the receiving unit is specifically used to receive the serial data based on the receiving clock signal and a set baud rate; wherein the set baud rate is the same as the baud rate at which the host computer sends the serial data.

[0022] According to one embodiment of the present invention, the storage unit is specifically configured to start reading the command statements when the number of command statements for ending the write operation and stopping the write operation is determined to be equal to a first preset number, and to stop the read operation when the number of command statements read is equal to the number of command statements written.

[0023] According to one embodiment of the present invention, the FPGA further includes: a differential output buffer OBUFDS, wherein the differential output buffer OBUFDS is disposed between the memory cell and the output port of the FPGA; wherein,

[0024] The differential output buffer OBUFDS is used to convert the command statement into a differential signal and then send it to the display panel through the auxiliary channel.

[0025] To achieve the above objectives, a second aspect of the present invention proposes a method for setting a Display Port Configuration Data (DPCD) register based on the first aspect of the present invention. The method for setting the DPCD register is implemented using the system proposed in the first aspect of the present invention, and includes the following steps: a host computer sends serial data via a serial data bus; wherein the serial data is a statement based on an auxiliary channel protocol; the FPGA processes the received serial data to obtain a corresponding command statement, and sends the command statement through the auxiliary channel; the display panel receives the command statement and transmits the command statement to the DPCD register to achieve the setting of the DPCD register.

[0026] According to an embodiment of the present invention, a method for setting the Display Port Configuration Data (DPCD) register involves a host computer sending serial data via a serial data bus. This serial data is a statement based on an auxiliary channel protocol. The FPGA processes the received serial data to obtain the corresponding command statement and sends it through the auxiliary channel. Upon receiving the command statement, the display panel transmits it to the DPCD register, thereby setting the DPCD register. Thus, this method enables the setting of the DPCD register via an auxiliary channel on an FPGA platform.

[0027] In addition, the method for setting the display port configuration data DPCD register according to the second aspect embodiment of the present invention may also have the following additional technical features:

[0028] According to one embodiment of the present invention, when the FPGA processes the received serial data to obtain the corresponding command statement, it includes:

[0029] The system receives the serial data sent by the host computer and performs serial-to-parallel conversion on the serial data to generate multiple sets of parallel data with a set number of bits and a flag bit for the parallel data; wherein, the flag bit is used to indicate that the parallel data with the set number of bits is valid data.

[0030] The valid data is encoded; wherein, the encoding is to convert the valid data into the command statement transmitted through the auxiliary channel;

[0031] The command statement is stored and then sent to the display panel.

[0032] According to one embodiment of the present invention, receiving the serial data sent by the host computer includes:

[0033] Based on the received clock signal, the serial data is received at a set baud rate; wherein the set baud rate is the same as the baud rate at which the host computer sends the serial data.

[0034] According to one embodiment of the present invention, the command statement includes:

[0035] Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

[0036] According to one embodiment of the present invention, sending the command statement to the display panel includes:

[0037] When the number of command statements indicating the end of the write operation and the stop of the write operation is equal to a first set number, the command statements are read out.

[0038] The read operation stops when it is determined that the number of command statements read is equal to the number of command statements written.

[0039] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0040] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0041] Figure 1 This is a schematic diagram of a system for setting the Display Port Configuration Data DPCD register according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of a system for setting the Display Port Configuration Data DPCD register according to an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the system working principle for setting the DPCD register for display port configuration data according to an embodiment of the present invention;

[0044] Figure 4 The flowchart is a method for setting the Display Port Configuration Data DPCD Register according to an embodiment of the present invention. Detailed Implementation

[0045] The embodiments of the present invention disclosed below are described in detail. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0046] The system and method for setting the DPCD register for display port configuration data provided by the present invention will now be described in detail with reference to the accompanying drawings.

[0047] Figure 1 This is a schematic diagram of a system for setting the Display Port Configuration Data DPCD register according to an embodiment of the present invention.

[0048] like Figure 1 As shown, the system for setting the display port configuration data DPCD register according to an embodiment of the present invention includes: a host computer (PC), a field-programmable gate array (FPGA), and a display panel (Panel).

[0049] The FPGA's input port is connected to the host PC's serial interface via a serial data bus, and the FPGA's output port is connected to the display panel via an auxiliary channel (AUX). The host PC sends serial data via the serial data bus, which is a statement based on the AUX protocol. The FPGA processes the received serial data to obtain the corresponding command statement and sends the command statement via the AUX. The display panel receives the command statement and transmits it to the DPCD register to configure the DPCD register.

[0050] It should be noted that the display panel in the embodiments of the present invention can be any one of LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display panel, and LED (Light Emitting Diode) display panel.

[0051] In this embodiment, serial port software is installed on a host PC, such as a desktop or laptop, and a serial data bus is used to connect the host PC to the FPGA. The serial port software on the host PC then sends serial data based on the AUX protocol to the FPGA. It should be noted that the relevant settings on the serial port software mentioned in this embodiment (such as baud rate, data bit width, and the presence or absence of a parity bit) are related to the code of the receiving unit 10 in the FPGA used to receive serial data.

[0052] The FPGA receives serial data sent by the host PC, processes the received serial data to obtain the corresponding command statement, and sends the command statement to the display panel through the auxiliary channel AUX.

[0053] The display panel receives command statements output by the FPGA and transmits them to the DPCD register in the TCON. Thus, based on the FPGA platform, the function of setting the DPCD register based on the FPGA is realized through the auxiliary channel AUX.

[0054] Figure 2 This is a schematic diagram of a system for setting the Display Port Configuration Data DPCD register according to an embodiment of the present invention.

[0055] like Figure 2 As shown, the FPGA of this embodiment includes a receiving unit 10, an encoding unit 20, and a storage unit 30. The receiving unit 10 receives serial data sent by a host computer (PC) and performs serial-to-parallel conversion to generate multiple sets of parallel data with specified bit positions and a flag bit for the parallel data; the flag bit indicates that the parallel data with specified bit positions is valid data. The encoding unit 20 is connected to the receiving unit 10 and is used to encode the valid data; the encoding converts the valid data into command statements transmitted via the auxiliary channel (AUX). The storage unit 30 is connected to the encoding unit 20 and is used to store the command statements and send them to the display panel.

[0056] like Figure 2 As shown, the FPGA also includes a phase-locked loop (PLL) unit. The PLL unit 40 is connected to the receiving unit 10, the encoding unit 20, and the storage unit 30. The PLL unit 40 performs frequency multiplication and division processing on the external clock (provided by a crystal oscillator), providing the receiving unit 10 with a receive clock signal CLK1, the encoding unit 20 with an encoding clock signal CLK2, and the storage unit 30 with a write clock signal WCLK and a read clock signal RCLK. Specifically, the receiving unit 10 receives serial data based on the receive clock signal CLK1; the encoding unit 20 encodes valid data based on the encoding clock signal CLK2; and the storage unit 30 stores command statements based on the write clock signal WCLK and reads the stored command statements based on the read clock signal RCLK.

[0057] In an embodiment of the present invention, the receiving unit 10 can be a UART (Universal Asynchronous Receiver Transmitter). The receiving unit 10 receives and processes the serial data sent by the serial port software of the host PC. For example, the receiving unit can receive the serial port data (i.e., bit information) sent by the serial port software based on the receiving clock signal CLK1 and set the baud rate (the set baud rate is the same as the baud rate at which the host PC sends the serial data). The receiving unit performs serial-to-parallel conversion on the bit information (serial-to-parallel conversion is to sample the serial data at a fixed sampling frequency) and generates multiple sets of parallel data and a flag bit for the parallel data. For example, multiple sets of 8-bit parallel data and 1-bit flag bits are generated. The 8-bit parallel data is related to the serial data sent by the host PC, and the 1-bit flag bit is separate, representing that the corresponding 8-bit parallel data is valid data.

[0058] The encoding unit 20 encodes multiple valid data received based on the encoding clock signal CLK2, such as Manchester encoding. This encoding converts multiple valid data into command statements transmitted through the auxiliary channel AUX, such as: Pre-charge, Start, End, Command Comm, Address Addr, Write byte length Len, Write data content Data, and Write operation stop. For example, if serial data, after serial-to-parallel conversion, produces 14 8-bit valid data, and both the write byte length (Len) and write data content (Data) require 3 8-bit valid data for conversion, then in sequence: the first and second 8-bit valid data are converted to Pre-charge; the third and fourth 8-bit valid data are converted to Start; the fifth 8-bit valid data is converted to End; the sixth 8-bit valid data is converted to Command (Comm); the seventh 8-bit valid data is converted to Address (Addr); the eighth, ninth, and tenth 8-bit valid data are converted to Write byte length (Len); the eleventh, twelfth, and thirteenth 8-bit valid data are converted to Write data content (Data); and the fourteenth 8-bit valid data is converted to Stop. It should be noted that in this embodiment, only the encoded data allows the FPGA connected to the auxiliary channel (AUX) to communicate normally with the display panel.

[0059] Storage unit 30 stores encoded data based on the write clock signal WCLK. When the number of end-of-write and stop-of-write command statements in storage unit 30 equals a first preset number (2), it begins reading command statements from storage unit 30. When the number of command statements read from storage unit 30 equals the number of command statements written to storage unit 30, it stops reading statements from storage unit 30; that is, the read operation ends after reading all 8 bits of valid data.

[0060] When the display panel receives a command statement output from the storage unit 30, it transmits the command statement to the DPCD register in the TCON, thereby realizing the function of setting the DPCD register based on the FPGA platform through the auxiliary channel AUX.

[0061] Figure 3 This is a schematic diagram of the system working principle for setting the Display Port Configuration Data DPCD register according to an embodiment of the present invention.

[0062] like Figure 3 As shown, the working principle of the system for setting the display port configuration data DPCD register in this embodiment of the invention is as follows:

[0063] The host PC sends the command statements to be written to the DPCD register to the FPGA at the set baud rate via serial port software.

[0064] The FPGA samples and receives serial data at a set baud rate, processing the received data to obtain multiple sets of 8-bit parallel data and a 1-bit flag. Then, internally, the FPGA performs Manchester encoding on the received 8-bit parallel data, converting it into write operation command statements transmitted via the auxiliary channel AUX. These command statements are, in sequence: Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

[0065] Of these eight commands, only the End and Stop commands do not require Manchester encoding (because the encoded data for End and Stop commands is 8'hF0). The other six commands require encoding. Then, the encoded data (including the End and Stop commands) is stored in storage unit 30, and the number of written commands is counted. When the count for the End and Stop commands reaches 2, it indicates that all commands for the AUX write operation have been written to storage unit 30. At this point, the data stored in storage unit 30 can be read and sent out bit by bit. When the number of bits sent matches the number of bits stored in storage unit 30, i.e., 14 8-bit valid data have been sent, it indicates that all commands for the AUX write operation have been sent.

[0066] When the display panel receives a command statement output from the storage unit 30, it transmits the command statement to the DPCD register in the TCON, thereby realizing the function of setting the DPCD register based on the FPGA platform through the auxiliary channel AUX.

[0067] Optionally, a differential output buffer OBUFDS is set between the storage unit 30 and the output port of the FPGA. The differential output buffer OBUFDS is used to convert the command statement into a differential signal and send it to the display panel through the auxiliary channel AUX.

[0068] In summary, the system for setting the Display Port Configuration Data (DPCD) register according to an embodiment of the present invention comprises a host computer, a Field Programmable Gate Array (FPGA), and a display panel. The FPGA's input port is connected to the host computer's serial interface via a serial data bus, and the FPGA's output port is connected to the display panel via an auxiliary channel. The host computer sends serial data via the serial data bus, the serial data being statements based on the auxiliary channel protocol. The FPGA processes the received serial data to obtain corresponding command statements and sends these command statements via the auxiliary channel. The display panel receives the command statements and transmits them to the DPCD register to set the DPCD register. Thus, this system, based on an FPGA platform, achieves the setting of the DPCD register via an auxiliary channel.

[0069] Figure 4 The flowchart is a method for setting the Display Port Configuration Data DPCD Register according to an embodiment of the present invention.

[0070] like Figure 4 As shown, the method for setting the Display Port Configuration Data (DPCD) register according to an embodiment of the present invention includes the following steps:

[0071] S401, the host computer sends serial data through the serial data bus; where the serial data is a statement based on the auxiliary channel protocol.

[0072] S402, the FPGA processes the received serial data to obtain the corresponding command statement, and sends the command statement through the auxiliary channel.

[0073] S403: The display panel receives command statements and transmits them to the DPCD register to set the DPCD register.

[0074] According to one embodiment of the present invention, when the FPGA processes the received serial data to obtain the corresponding command statement, it includes:

[0075] Receive serial data sent by the host computer and convert the serial data into parallel data to generate multiple sets of parallel data with set bit positions and flag bits for the parallel data; wherein, the flag bits are used to indicate that the parallel data with set bit positions is valid data;

[0076] Encode the valid data; whereby encoding is the process of converting the valid data into command statements that are transmitted through the auxiliary channel.

[0077] Store the command statement and send it to the display panel.

[0078] According to one embodiment of the present invention, receiving serial data sent by a host computer includes:

[0079] Serial data is received based on the received clock signal and a baud rate is set; wherein, the set baud rate is the same as the baud rate at which the host computer sends serial data.

[0080] According to one embodiment of the present invention, the command statement includes:

[0081] Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

[0082] According to one embodiment of the present invention, sending command statements to a display panel includes:

[0083] When the number of command statements used to determine the end of the write operation and the stop of the write operation is equal to the first set number, the command statements for reading will begin.

[0084] The read operation stops when the number of command statements read equals the number of command statements written.

[0085] It should be noted that for details not disclosed in the method for setting the display port configuration data DPCD register in the embodiments of the present invention, please refer to the details disclosed in the system for setting the display port configuration data DPCD register in the embodiments of the present invention, which will not be repeated here.

[0086] According to an embodiment of the present invention, a method for setting the Display Port Configuration Data (DPCD) register involves a host computer sending serial data via a serial data bus. This serial data is a statement based on an auxiliary channel protocol. The FPGA processes the received serial data to obtain the corresponding command statement and sends it through the auxiliary channel. Upon receiving the command statement, the display panel transmits it to the DPCD register, thereby setting the DPCD register. Thus, this method enables the setting of the DPCD register via an auxiliary channel on an FPGA platform.

[0087] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0089] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of the invention pertain.

[0090] The logic or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer system, a system including a processor, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0091] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0092] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0093] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a single module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0094] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A system for setting display port configuration data DPCD registers, characterized in that, include: The system comprises a host computer, a field-programmable gate array (FPGA), and a display panel. The input port of the FPGA is connected to the serial interface of the host computer via a serial data bus, and the output port of the FPGA is connected to the display panel via an auxiliary channel. The host computer is used to send serial data through the serial data bus; wherein the serial data is a statement based on the auxiliary channel protocol. The FPGA is used to process the received serial data to obtain the corresponding command statement, and to send the command statement through the auxiliary channel; The display panel is used to receive the command statement and transmit the command statement to the DPCD register to set the DPCD register.

2. The system according to claim 1, characterized in that, The FPGA includes: A receiving unit is configured to receive the serial data sent by the host computer and perform serial-to-parallel conversion on the serial data to generate multiple sets of parallel data with a set number of bits and a flag bit of the parallel data; wherein, the flag bit is used to indicate that the parallel data with the set number of bits is valid data. An encoding unit is connected to the receiving unit and is used to encode the valid data; wherein, the encoding is to convert the valid data into the command statement transmitted through the auxiliary channel; A storage unit is connected to the encoding unit. The storage unit is used to store the command statement and send the command statement to the display panel.

3. The system according to claim 2, characterized in that, The FPGA also includes: A phase-locked loop (PLL) unit is connected to the receiving unit, the encoding unit, and the storage unit, respectively. The PLL unit is used to perform frequency multiplication and division processing on the external clock, providing a receiving clock signal to the receiving unit, an encoding clock signal to the encoding unit, and a write clock signal and a read clock signal to the storage unit, respectively. Specifically, the receiving unit is used to receive the serial data based on the receiving clock signal; The encoding unit is specifically used to encode the valid data based on the encoding clock signal; The storage unit is specifically used to store the command statement based on the write clock signal and to read the stored command statement based on the read clock signal.

4. The system according to claim 2 or 3, characterized in that, The command statements include: Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

5. The system according to claim 3, characterized in that, in, The receiving unit is specifically used to receive the serial data based on the receiving clock signal and a set baud rate; wherein the set baud rate is the same as the baud rate at which the host computer sends the serial data.

6. The system according to claim 4, characterized in that, in, The storage unit is specifically used to start reading the command statements when the number of command statements for ending the write operation and stopping the write operation is equal to a first set number, and to stop the read operation when the number of command statements read is equal to the number of command statements written.

7. The system according to claim 2 or 3, characterized in that, The FPGA further includes: a differential output buffer (OBUFDS), wherein the differential output buffer (OBUFDS) is disposed between the memory cell and the output port of the FPGA; wherein, The differential output buffer OBUFDS is used to convert the command statement into a differential signal and then send it to the display panel through the auxiliary channel.

8. A method for setting a Display Port Configuration Data (DPCD) register, implemented using any one of claims 1-7, characterized in that, Includes the following steps: The host computer sends serial data via a serial data bus; wherein the serial data is a statement based on the auxiliary channel protocol. The FPGA processes the received serial data to obtain the corresponding command statement, and sends the command statement through the auxiliary channel; The display panel receives the command statement and transmits it to the DPCD register to set the DPCD register.

9. The method according to claim 8, characterized in that, When the FPGA processes the received serial data to obtain the corresponding command statement, it includes: The system receives the serial data sent by the host computer and performs serial-to-parallel conversion on the serial data to generate multiple sets of parallel data with a set number of bits and a flag bit for the parallel data; wherein, the flag bit is used to indicate that the parallel data with the set number of bits is valid data. The valid data is encoded; wherein, the encoding is to convert the valid data into the command statement transmitted through the auxiliary channel; The command statement is stored and then sent to the display panel.

10. The method according to claim 9, characterized in that, Receiving the serial data sent by the host computer includes: The serial data is received based on a received clock signal at a set baud rate; wherein the set baud rate is the same as the baud rate at which the host computer sends the serial data.

11. The method according to claim 9, characterized in that, The command statements include: Pre-charge, Start, End, Command Comm, Address Addr, Write Byte Length Len, Write Data Content Data, and Write Operation Stop.

12. The method according to claim 11, characterized in that, Sending the command statement to the display panel includes: When the number of command statements indicating the end of the write operation and the stop of the write operation is equal to a first set number, the command statements are read out. The read operation stops when it is determined that the number of command statements read is equal to the number of command statements written.

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