Electroluminescent display device

Abstract

The present disclosure relates to an electroluminescent display apparatus and a display defect processing method of an electroluminescent display apparatus. In one embodiment, an electroluminescent display apparatus includes a pixel connected to a detection line, a panel driving circuit configured to cut off driving of a driving element included in the pixel in a detection interval, a reference voltage generating circuit configured to provide a detection reference voltage to the detection line before the detection interval, to generate a first comparator reference voltage higher than the detection reference voltage in the detection interval, and to generate a second comparator reference voltage lower than the detection reference voltage in the detection interval, a comparator configured to compare the first comparator reference voltage with a voltage of the detection line at a first timing of the detection interval to generate a first comparison output, and to compare the second comparator reference voltage with the voltage of the detection line at a second timing of the detection interval to generate a second comparison output, and a logic circuit configured to determine whether a defect occurs in the pixel based on the first comparison output and the second comparison output obtained in the detection interval.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefits of Korean Patent Application No. 10-2021-0127998, filed on September 28, 2021, and Korean Patent Application No. 10-2022-0114952, filed on September 13, 2022, which are incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to electroluminescent display devices and methods for handling display defects. Background Technology

[0004] Electroluminescent display devices are classified into inorganic light-emitting display devices and electroluminescent display devices based on the material of the light-emitting layer. Each sub-pixel of an electroluminescent display device includes a self-emissive light-emitting device, and the brightness is adjusted by controlling the amount of light emitted from the light-emitting device using data voltage based on the gray level of the image data.

[0005] As subpixels degrade over time, hot spot defects may occur due to short circuits. Defective subpixels identified as hot spots reduce visibility for the user, thereby degrading display quality. Summary of the Invention

[0006] In order to overcome the above-mentioned problems of the prior art, the present disclosure provides an electroluminescent display device that detects and compensates for hot spot defects caused by sub-pixel short circuits to improve display quality.

[0007] Furthermore, this disclosure can provide an electroluminescent display device that minimizes the circuitry required for detecting and compensating for hot spot defects caused by subpixel short circuits, thereby reducing manufacturing costs and increasing product lifespan and reliability.

[0008] To achieve these and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a pixel connected to a detection line; a panel driving circuit configured to cut off driving of driving elements included in the pixel during a detection interval; a reference voltage generation circuit configured to provide a detection reference voltage to the detection line before the detection interval, generate a first comparator reference voltage higher than the detection reference voltage during the detection interval, and generate a second comparator reference voltage lower than the detection reference voltage during the detection interval; a comparator configured to compare the first comparator reference voltage with the voltage of the detection line at a first timing of the detection interval to generate a first comparison output, and to compare the second comparator reference voltage with the voltage of the detection line at a second timing of the detection interval to generate a second comparison output; and logic circuitry configured to determine whether the pixel has a defect based on the first and second comparison outputs obtained during the detection interval.

[0009] In another aspect of this disclosure, a method for handling display defects in an electroluminescent display device including pixels connected to a detection line is disclosed. The method includes: providing a scan signal having a conduction level and a detection data voltage having a cutoff level to the pixels during a detection interval to deactivate each driving element included in the pixels; sequentially generating a first reference voltage and a second reference voltage; providing the first reference voltage to the detection line at a first timing point of the detection interval; and providing the second reference voltage to the detection line at a second timing point of the detection interval, wherein the second reference voltage is lower than the first reference voltage and the second timing point is later than the first timing point; comparing the first comparator reference voltage with the voltage of the detection line at the first timing point to generate a first comparison output; and comparing the second comparator reference voltage with the voltage of the detection line at the second timing point to generate a second comparison output; and determining whether the pixel has a defect based on the first comparison output and the second comparison output.

[0010] In another aspect of this disclosure, an electroluminescent display device includes: a pixel; a panel driving circuit connected to the pixel and configured to provide the pixel with a scan signal having an on level and a detection data voltage having an off level during a detection interval; a comparator including a first input terminal receiving a reference voltage and a second input terminal connected to a detection line, and configured to generate a first comparison output and a second comparison output at a first timing and a second timing of the detection interval, respectively; and logic circuitry determining whether a defect has occurred in the pixel based on the first comparison output and the second comparison output; wherein the reference voltage is set to: a first comparator reference voltage higher than the detection reference voltage at the first timing and a second comparator reference voltage lower than the detection reference voltage at the second timing; and the detection reference voltage is a voltage provided to the detection line before the detection interval.

[0011] In another aspect of this disclosure, an electroluminescent display device includes: a pixel connected to a detection line; a panel driving circuit configured to cut off driving of driving elements included in the pixel during a detection interval; a reference voltage generation circuit configured to provide a detection reference voltage to the detection line during an initialization interval prior to the detection interval; a dynamic logic circuit including a first output node and a second output node connected between a first power level and a second power level below the first power level, the dynamic logic circuit being configured to generate a first logic output through the first output node and a second logic output through the second output node, and the first and second logic outputs being offset based on the voltage of the detection line offset from the detection reference voltage during the detection interval; and a logic circuit configured to determine whether a defect has occurred in the pixel based on the first and second logic outputs obtained during the detection interval. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate one or more embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0013] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0014] Figure 2 This is a diagram illustrating the pixel connection configuration according to an embodiment of the present disclosure;

[0015] Figure 3 This is a diagram illustrating various defect types in pixels according to embodiments of the present disclosure;

[0016] Figure 4 This is a diagram illustrating the connection configuration of the pixel and defect processing circuit according to an embodiment of the present disclosure;

[0017] Figure 5 This is a diagram showing the driving waveforms of a pixel and defect processing circuit according to an embodiment of the present disclosure;

[0018] Figure 6 This is a diagram showing the comparator output of a defect handling circuit based on defect type;

[0019] Figure 7 This is a schematic diagram illustrating a first embodiment in which a comparator for a defect handling circuit is mounted on a control printed circuit board.

[0020] Figure 8 It shows in detail the basis Figure 7 A diagram of the connection configuration of the first embodiment;

[0021] Figure 9 It shows in detail the basis Figure 7 A diagram of the drive waveforms of the connection configuration in the first embodiment;

[0022] Figure 10A and Figure 10B It shows the basis Figure 7 A diagram illustrating the defect handling method of the first embodiment;

[0023] Figure 11A This is a diagram illustrating an example of detecting the Nth horizontal display line, which includes a target pixel with defects;

[0024] Figure 11B and Figure 11C This is a diagram illustrating an example of detecting the Mth source driver integrated circuit connected to the target pixel in the Nth horizontal display line;

[0025] Figure 11D This is a diagram illustrating an example of detecting a reference voltage line connected to a target pixel in a reference voltage line connected to the Mth source driver integrated circuit;

[0026] Figure 12 This is a diagram schematically illustrating a second embodiment of a comparator with defect handling circuitry mounted on each source driver integrated circuit;

[0027] Figure 13 It shows in detail the basis Figure 12 A diagram of the connection configuration in the second embodiment;

[0028] Figure 14 It shows in detail the basis Figure 12 A diagram of the drive waveforms for the connection configuration of the second embodiment;

[0029] Figure 15 It shows the basis Figure 12 A diagram of the second embodiment of the defect handling method; and

[0030] Figure 16 This is a diagram illustrating the connection configuration between pixels and detection processing circuitry according to another embodiment of the present disclosure;

[0031] Figure 17 It is shown Figure 16 A diagram showing the detailed connection configuration between pixels and dynamic logic circuits included in the detection processing circuit;

[0032] Figure 18 It is shown Figure 17 A diagram of the pixel and the driving waveform of the detection processing circuit;

[0033] Figure 19 It is shown in Figure 18 A diagram of the pre-charge operation of the dynamic logic circuitry performed during the pre-charge interval;

[0034] Figure 20 It is shown in Figure 18 A diagram of the first detection operation of the dynamic logic circuit executed during the detection interval;

[0035] Figure 21 It is shown in Figure 18 A diagram of the second detection operation of the dynamic logic circuit executed during the detection interval;

[0036] Figure 22 It is shown in Figure 18 A diagram of the third detection operation of the dynamic logic circuit executed during the detection interval;

[0037] Figure 23 This is a diagram showing the output of the dynamic logic circuit for the defect handling circuit of the defect type;

[0038] Figure 24 This is a diagram illustrating the connection configuration between pixels and detection processing circuitry according to another embodiment of the present disclosure;

[0039] Figure 25 It is shown Figure 24 A diagram showing the detailed connection configuration between pixels and dynamic logic circuits included in the detection processing circuit;

[0040] Figure 26 It is shown Figure 25 A diagram of the pixel and the driving waveform of the detection processing circuit;

[0041] Figure 27 It is shown in Figure 26A diagram showing the outputs of the dynamic logic circuits executed during the first initialization interval and the first detection interval; and

[0042] Figure 28 It is shown in Figure 26 The diagram shows the output of the dynamic logic circuit executed during the second initialization interval and the second detection interval. Detailed Implementation

[0043] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, when adding reference numerals to elements in each drawing, care should be taken to use similar reference numerals that have already been used to denote similar elements in other drawings as much as possible. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions unnecessarily obscure the essential points of the present disclosure.

[0044] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure.

[0045] Reference Figure 1 An electroluminescent display device according to embodiments of the present disclosure may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a defect handling circuit 14. The data driver 12 and the gate driver 13 may be configured as a panel driving circuit.

[0046] In the screen displaying the input image in the display panel 10, data lines DL extending in the column direction (or vertical direction) may intersect gate lines GL extending in the row direction (or horizontal direction), and pixels PXL may be arranged in a matrix type in multiple intersection areas to configure a pixel array. Each data line DL may be commonly connected in the column direction to a pixel PXL adjacent to the data line DL, and each gate line GL may be commonly connected in the row direction to a pixel PXL adjacent to the gate line GL.

[0047] Each pixel PXL can include multiple subpixels. Multiple subpixels can be configured with a single pixel PXL to generate various color combinations. To simplify the pixel array, subpixels configured with the same pixel PXL can share the same detection line SIO.

[0048] As subpixels degrade over time, hot spot defects may occur due to short circuits. Detection lines SIO can be used to detect defects in the corresponding pixel PXL. In the pixel array, the detection lines SIO can be arranged in the column direction parallel to the data lines DL, but are not limited to this.

[0049] The timing controller 11 can receive timing signals from the host system, such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock DCLK, to generate timing control signals for controlling the operation timing of the control panel drive circuitry. The timing control signals may include the gate timing control signal GDC and the data timing control signal DDC.

[0050] The timing controller 11 can receive video data DATA from the host system and a defect compensation signal BPC from the defect processing circuit 14. The defect compensation signal BPC can be used to perform partial or overall dark spot processing on defective pixels PXL. A pixel PXL is determined to be defective when at least one sub-pixel of a pixel PXL is defective. Partial dark spot processing can replace only one piece of video data DATA to be applied to the defective sub-pixel with block grayscale data, while overall dark spot processing can replace all video data DATA to be applied to a defective pixel PXL with block grayscale data. The timing controller 11 can reflect black grayscale data in the video data DATA based on the defect compensation signal BPC and can provide the video data DATA reflecting the black grayscale data to the data driver 12.

[0051] The timing controller 11 can divide the display driver and the detection driver in time based on the timing control signals DDC and GDC. The display driver can be used to display an input image on the screen based on video data DATA that reflects black grayscale data. The detection driver can be used to detect defective pixels PXL and make the defective pixels PXL partially or entirely black.

[0052] Display driving can be performed during the vertical active interval in a frame where the data enable signal transitions from logic high to logic low, and sensing driving can be performed during the vertical blanking intervals in a frame, excluding the vertical active intervals. During the vertical blanking intervals, the data enable signal can remain at a logic low level. Furthermore, sensing driving can be performed during the power-on interval from when the system main power is applied until screen playback begins, or during the power-off interval from when screen playback ends until the system main power is released.

[0053] The data driver 12 can be connected to the sub-pixel via the data line DL. The data driver 12 can generate the data voltage required for display driving or detection driving of the sub-pixel based on the data timing control signal DDC, and can provide the data voltage to the data line DL. The data voltage used for display driving can be the result of digital-to-analog conversion of video data DATA, and for this purpose, the data driver 12 can include multiple digital-to-analog converters. The data voltage used for detection driving can be a detection data voltage with an on or off level.

[0054] The data driver 12 can be configured with multiple source driver integrated circuits (ICs). Each source driver IC may include a shift register, a latch, a digital-to-analog converter, and an output buffer. Each source driver IC may also include separate circuitry for generating the detection data voltage.

[0055] Gate driver 13 can be connected to a sub-pixel via gate line GL. Gate driver 13 can generate scan signals based on gate timing control signal GDC, and can provide scan signals to gate line GL separately based on data voltage supply timing. The horizontal display line to which the data voltage is to be supplied can be selected by the scan signals. Each scan signal can be generated in the form of a pulse that swings between a gate on level and a gate off level. A scan signal with a gate on level can be set to a voltage higher than the threshold voltage of the transistors included in the sub-pixel, and a scan signal with a gate off level can be set to a voltage lower than the threshold voltage of the transistors included in the sub-pixel. The transistors included in the sub-pixel can be turned on in response to a scan signal with a gate on level, and can be turned off in response to a scan signal with a gate off level.

[0056] Gate driver 13 may include a gate shift register, a level shifter for converting the output signal of the gate shift register, which has on-level and off-level swing widths, and multiple gate driver ICs, each including an output buffer. Alternatively, gate driver 13 may be directly mounted on the substrate of display panel 10 in an in-panel gate driver (GIP) type. In GIP type, the level shifter may be mounted on a control printed circuit board (PCB), and the gate shift register may be located in the bezel area that is a non-display area of ​​display panel 10. Gate shift register may include multiple scan output stages cascaded together. Scan output stages may be independently connected to gate line GL and may output scan signals to gate line GL.

[0057] The defect handling circuit 14 can be connected to the pixel PXL of the display panel 10 via the detection line SIO. The defect handling circuit 14 can provide a display reference voltage to the sub-pixel via the detection line SIO during display driving. The defect handling circuit 14 can provide both the display reference voltage and the detection reference voltage to the detection line SIO during detection driving, and can detect voltage changes in each detection line SIO caused by a short-circuit defect in the sub-pixel using a comparator or dynamic logic circuit.

[0058] Defect handling circuit 14 can be used Figures 4 to 15 The comparator shown is used to detect the detection line caused by a short-circuit defect. Figure 2The voltage change in each of the SIO components. To improve the accuracy and reliability of the detection, two comparator reference voltages with different voltage levels can be provided to the comparator. The two comparator reference voltages can include a first comparator reference voltage and a second comparator reference voltage.

[0059] Based on Figures 4 to 14 In the detection drive, when the driving element of each sub-pixel is cut off by the detection data voltage with a cutoff level, the voltage of the detection line SIO connected to the normal pixel PXL can be maintained at the detection reference voltage in the first timing and the second timing. Due to the current inflow or outflow caused by the short circuit defect, the voltage of the detection line SIO connected to the defective pixel PXL can be different from the detection reference voltage in the first timing and the second timing.

[0060] Figures 4 to 15 The defect processing circuit 14 can compare a first comparator reference voltage with the voltage of the detection line SIO in a first timing sequence during the detection drive to generate a first comparison output, and can compare a second comparator reference voltage with the voltage of the detection line SIO in a second timing sequence during the detection drive to generate a second comparison output (wherein the second timing sequence is later than the first timing sequence). The defect processing circuit 14 can determine whether a pixel PXL has a defect based on the first comparison output and the second comparison output, and can output a defect compensation signal BPC based on the defective pixel PXL.

[0061] Defect handling circuit 14 can be used Figures 16 to 28 The dynamic logic circuit shown is used to detect voltage changes in each detection line SIO caused by short-circuit defects in sub-pixels. To improve detection accuracy and reliability, the dynamic logic circuit can output a first logic output that varies based on the voltage of the detection line SIO via a first output node, and a second logic output that varies according to the voltage of the detection line SIO via a second output node. Because the dynamic logic circuit is implemented with a circuit size smaller than that of a comparator, it can be easily integrated into a source driver IC.

[0062] Based on Figures 16 to 28 In the detection circuit, when the driving element of each sub-pixel is cut off by using the detection data voltage with a cutoff level, the voltage of the detection line SIO connected to the normal pixel PXL can be maintained as the detection reference voltage. However, due to the current inflow or outflow caused by the short-circuit defect, the voltage of the detection line SIO connected to the defective pixel PXL may be different from the detection reference voltage.

[0063] Figures 16 to 28The defect processing circuit 14 can determine whether a defect occurs in pixel PXL based on the first logic output and / or the second logic output obtained by the dynamic logic circuit in the detection drive, and can output a defect compensation signal BPC corresponding to the defective pixel PXL.

[0064] Figure 2 This is a diagram illustrating the pixel connection configuration according to an embodiment of the present disclosure. Figure 3 This is a diagram illustrating various defect types in pixels according to embodiments of this disclosure.

[0065] Reference Figure 2 Pixel PXL may include four sub-pixels SP1 to SP4 sharing a detection line SIO. The four sub-pixels SP1 to SP4 may include a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel for configuring the same pixel. Each of the four sub-pixels SP1 to SP4 may include, for example, a light-emitting device EL, a driving element DT, switching elements ST1 and ST2, and a storage capacitor Cst, but is not limited thereto. The inventive concept is not limited to the detailed connection configuration of the sub-pixels.

[0066] The light-emitting device EL can emit light using the display drive current supplied from the driving element DT. The light-emitting device EL can emit light only during display driving and may not emit light during detection driving. The light-emitting device EL can be implemented using an organic light-emitting diode (OLED) including an organic light-emitting layer, or it can be implemented using an inorganic light-emitting diode including an inorganic light-emitting layer. The anode electrode of the light-emitting device EL can be connected to the second node N2, and the cathode electrode of the light-emitting device EL can be connected to the input terminal of the low-level source voltage EVSS.

[0067] In display driving, the driving element DT can generate a display driving current based on its first gate-source voltage (i.e., the voltage difference between the display data voltage and the display reference voltage) and can provide the display driving current to the light-emitting device EL. In detection driving, the driving element DT can be turned off using its second gate-source voltage (i.e., the voltage difference between the detection reference voltage PCL and the detection data voltage SVdata with a cutoff level), and at this time, current cannot flow in the driving element DT when it is turned off. Furthermore, in detection driving, the driving element DT can be turned on using its third gate-source voltage (i.e., the voltage difference between the detection reference voltage PCL and the detection data voltage SVdata with a conduction level). At this time, current can flow in the driving element DT when it is turned on. However, due to the low current, the light-emitting device EL may not emit light. The gate electrode of the driving element DT can be connected to the first node N1, the drain electrode of the driving element DT can be connected to the input terminal for the high-level source voltage EVDD, and the source electrode of the driving element DT can be connected to the second node N2.

[0068] Switching elements ST1 and ST2 can be turned on in both the display drive and the detection drive, thus allowing the gate electrode of the driving element DT to be connected to the data line DL and the source electrode of the driving element DT to be connected to the detection line SIO. Switching elements ST1 and ST2 can be turned on based on the same scan signal SCAN. Switching elements (e.g., a first switching element and a second switching element) ST1 and ST2 can remain continuously turned on in the detection drive.

[0069] A first switching element ST1 can be connected between the data line DL and the first node N1, and can be turned on based on the scan signal SCAN from the gate line GL. The first switching element ST1 can be turned on during programming for display driving, and also during detection driving. When the first switching element ST1 is turned on, a detection data voltage SVdata or a display data voltage can be applied to the first node N1. The gate electrode of the first switching element ST1 can be connected to the gate line GL, the source electrode of the first switching element ST1 can be connected to the data line DL, and the drain electrode of the first switching element ST1 can be connected to the first node N1.

[0070] The second switching element ST2 can be connected between the detection line SIO and the second node N2, and can be turned on based on the scan signal SCAN from the gate line GL. In display driving programming, the second switching element ST2 can be turned on and can apply the display reference voltage charged to the detection line SIO to the second node N2. In detection driving, the second switching element ST2 can be turned on and can apply the detection reference voltage PCL charged to the detection line SIO to the second node N2. The gate electrode of the second switching element ST2 can be connected to the gate line GL, the drain electrode of the second switching element ST2 can be connected to the second node N2, and the source electrode of the second switching element ST2 can be connected to the detection line SIO.

[0071] The storage capacitor Cst can be connected between the first node N1 and the second node N2, and can store the gate-source voltage of the driving element DT.

[0072] Such sub-pixels can include Figure 3 At least one of the various defect types shown. The defect types may include a sub-pixel short-circuit defect associated with the driving element DT, a sub-pixel short-circuit defect associated with the second switching element ST2, a sub-pixel short-circuit defect associated with the light-emitting device EL, and a progressive short-circuit defect associated with the detection line SIO. When a sub-pixel short-circuit defect occurs, the voltage of the detection line SIO may fail to maintain the detection reference voltage PCL and may deviate from the detection reference voltage PCL during detection drive.

[0073] Subpixel short circuits associated with the driving element DT may include gate-source short circuits (GS short circuits), gate-drain short circuits (GD short circuits), and drain-source short circuits (DS short circuits) of the driving element DT. Subpixel short circuits associated with the second switching element ST2 may include gate-source short circuits (GS short circuits), gate-drain short circuits (GD short circuits), and drain-source short circuits (DS short circuits) of the second switching element ST2. Subpixel short circuits associated with the light-emitting device EL may refer to short circuits between the anode and cathode of the light-emitting device EL. Subpixel short circuits associated with the detection line SIO may include short circuits between the detection line SIO and the high-level source voltage EVDD, and short circuits between the detection line SIO and the low-level source voltage EVSS.

[0074] Figure 4 This is a diagram illustrating the connection configuration of the pixel and defect processing circuit according to an embodiment of the present disclosure. Figure 5 This is a diagram showing the driving waveforms of a pixel and defect processing circuit according to an embodiment of the present disclosure. Figure 6 This is a graph showing the comparator output based on the defect type.

[0075] Reference Figure 4 An electroluminescent display device according to embodiments of this disclosure may include a panel driving circuit PDRV and a defect handling circuit for detecting and compensating for sub-pixel short circuits occurring in pixel PXL. The defect handling circuit can be configured using a simple setup including a reference voltage generation circuit PGMA, a comparator COMP, and a logic circuit BPCL, thus reducing the size of the circuit units and manufacturing costs. The defect handling circuit can partially or entirely blacken the pixel PXL where a sub-pixel short circuit occurs, thereby removing hot spot defects and increasing product lifespan and reliability.

[0076] Reference Figures 4 to 6 The panel driving circuit PDRV can provide a scan signal SCAN with a conduction level and a detection data voltage SVdata with a cutoff level to pixel PXL during the detection interval, so as to cut off the driving of each driving element included in pixel PXL. At this time, the detection reference voltage PCL can be charged to the detection line SIO connected to pixel PXL.

[0077] When a sub-pixel short-circuit defect occurs in pixel PXL, the voltage VSIO of the detection line SIO may not remain at the detection reference voltage PCL during the detection interval, and may increase or decrease from the detection reference voltage PCL.

[0078] The reference voltage generation circuit PGMA can generate a reference voltage Vref with three voltage levels applied to the comparator COMP. The three voltage levels can include a detection reference voltage PCL provided to the detection line SIO via the comparator COMP before the detection interval, a first comparator reference voltage TH-HIGH higher than the detection reference voltage PCL, and a second comparator reference voltage TH-LOW lower than the detection reference voltage PCL. The detection reference voltage PCL can be the voltage VSIO used to initialize the detection line SIO and the comparator COMP. The first comparator reference voltage TH-HIGH can be the comparator reference voltage used to detect defect 1 (overflow type), in which the voltage VSIO of the detection line SIO increases from the detection reference voltage PCL. The second comparator reference voltage TH-LOW can be the comparator reference voltage used to detect defect 2 (underflow type), in which the voltage VSIO of the detection line SIO decreases from the detection reference voltage PCL.

[0079] An overflow defect 1 may occur due to short circuits in the GD and DS of the driving element DT, short circuits in the GS, GD, and DS of the second switching element ST2, and a short circuit between the detection line SIO and the high-level source voltage EVDD. An underflow defect 2 may occur due to a short circuit in the GS of the driving element DT, a short circuit (AC short circuit) between the anode and cathode electrodes of the light-emitting device EL, and a short circuit between the detection line SIO and the low-level source voltage EVSS.

[0080] The comparator COMP can compare the first comparator reference voltage TH-HIGH with the voltage VSIO of the detection line SIO at the first timing Tx of the detection interval to generate a first comparator output VCO1, and can compare the second comparator reference voltage TH-LOW with the voltage VSIO of the detection line SIO at the second timing Ty after the first timing Tx of the detection interval to generate a second comparator output VCO2. The first comparator output VCO1 and the second comparator output VCO2 can be either "1" representing a high voltage or "0" representing a low voltage.

[0081] At the first timing Tx, when the voltage VSIO of the detection line SIO is lower than the first comparator reference voltage TH-HIGH, the comparator COMP can output a high voltage 1 as the first comparator output VCO1. Conversely, when the voltage VSIO of the detection line SIO is higher than or equal to the first comparator reference voltage TH-HIGH, the comparator COMP can output a low voltage 0 as the first comparator output VCO1. This is because the voltage VSIO of the detection line SIO is input to the second input terminal (-) of the comparator COMP.

[0082] At the second timing Ty, when the voltage VSIO of the detection line SIO is higher than the reference voltage TH-LOW of the second comparator, the comparator COMP can output a low voltage 0 as the second comparator output VCO2. When the voltage VSIO of the detection line SIO is lower than or equal to the reference voltage TH-LOW of the second comparator, the comparator COMP can output a high voltage 1 as the second comparator output VCO2.

[0083] The logic circuit BPCL can determine whether pixel PXL has a defect based on the first comparison output VCO1 and the second comparison output VCO2. Specifically, the BPCL can determine whether pixel PXL has a defect based on the logical combination of the first comparison output VCO1 and the second comparison output VCO2. The BPCL can only determine that pixel PXL is in a normal state when the logical combination of the first comparison output VCO1 and the second comparison output VCO2 is (1, 0), while it can determine that pixel PXL is in an abnormal state when the logical combination of the first comparison output VCO1 and the second comparison output VCO2 is not (1, 0). For example, when the logical combination of the first comparison output VCO1 and the second comparison output VCO2 is (1, 1), the BPCL can determine that pixel PXL includes an underflow defect 2, while when the logical combination of the first comparison output VCO1 and the second comparison output VCO2 is (0, 0), the BPCL can determine that pixel PXL includes an overflow defect 1.

[0084] The logic circuit BPCL can output a defect compensation signal BPC for the defective pixel PXL (see...). Figure 1 This allows defective pixels (PXL) to turn black.

[0085] Figure 7 This is a schematic diagram illustrating a first embodiment in which a comparator is mounted on a control PCB.

[0086] Reference Figure 7 The comparator COMP can be mounted on the control PCB (CPCB) along with the logic BPCL and the reference voltage generation circuit PGMA. In this case, because the number of comparator COMPs is less than the number of detection lines SIO, the size of the circuit unit can be greatly reduced and the manufacturing cost lowered. A comparator COMP can be connected to the multiplexer array AMUX in each source driver IC (SD-IC). Multiple multiplexer switches included in the multiplexer array AMUX can selectively connect the comparator COMP to multiple detection lines SIO. The on / off operation of each multiplexer switch can be controlled by the logic circuit BPCL. The multiplexer switches can be selectively turned on during the detection interval, and all multiplexer switches can be turned on during the initialization interval before the detection interval.

[0087] The comparator COMP may include: a first input terminal (+) through which a first comparator reference voltage TH-HIGH and a second comparator reference voltage TH-LOW are input; a second input terminal (-) through which the voltage VSIO of the detection line SIO is input; and an output terminal in which a comparator output VCO (i.e., a first comparator output VCO1 and a second comparator output VCO2) is generated.

[0088] The enable switch EN can also be connected between the second input (-) and output of the comparator COMP. The enable switch EN can be turned off during the detection interval and turned on during the initialization interval preceding the detection interval. During the initialization interval, when the enable switch EN and the multiplexer switch are on, the voltages VSIO of the comparator COMP and each detection line SIO can be initialized to the detection reference voltage PCL from the reference voltage generation circuit PGMA.

[0089] Figure 8 It shows in detail the basis Figure 7 A diagram showing the connection configuration of the first embodiment. Figure 9 It shows in detail the basis Figure 7 A diagram of the drive waveform of the connection configuration in the first embodiment.

[0090] Reference Figure 8 and Figure 9 The display panel PNL and the source PCB SPCB can be electrically connected to each other via a conductive film COF, and the source driver IC SD-IC can be integrated on the conductive film COF. In addition to the data driver 12 (see...), Figure 1 In addition to the multiplexer array AMUX, the switch controller SCT and receiver RX can also be mounted on the source driver IC SD-IC.

[0091] The source PCB (SPCB) and control PCB (CPCB) can be electrically connected to each other via flexible circuit cables (FFC), but are not limited thereto. The logic circuit (BPCL) can be connected to the timing controller 11 (see...). Figure 1 The timing controller 11 is integrated and can be mounted on the control PCC PCB. Figure 1 It may also include a transmitter TX for transmitting switch control signals generated by the logic circuit BPCL. The logic circuit BPCL can generate switch control signals differently for each source driver IC SD-IC, and in addition, it can generate switch control signals differently for multiplexer switches SW1 to SWk.

[0092] The transmitter (TX) and receiver (RX) can be connected to each other via internal interface circuitry. Switch control signals generated by the logic circuit BPCL can be added to data transmission packets and transmitted from the transmitter (TX) to the receiver (RX). The switch controller (SCT) converts the added switch control signals into parallel digital signals, which can then be transmitted to the multiplexer array (AMUX).

[0093] The AMUX multiplexer array may include multiple multiplexer switches SW1 to SWk and multiple encoders ENC connected to the gate electrodes of the multiplexer switches SW1 to SWk. The encoders ENC may be connected to a switch controller SCT and may receive switch control signals from the switch controller SCT to control the on / off operation of each of the multiplexer switches SW1 to SWk. The switch control signals may be implemented as multi-bit digital signals. For example, in a source driver IC SD-IC including 240 detection channels, the switch control signals may be implemented as 8-bit digital signals.

[0094] The comparator COMP, mounted on the control PCB CPCB, can be connected to the corresponding detection line SIO via an on / off multiplexer switch. Additionally, the comparator COMP can be connected to the reference voltage generation circuit PGMA. Based on control by the logic circuit BPCL, the reference voltage generation circuit PGMA generates a detection reference voltage PCL to be charged to the detection line SIO, and a first comparator reference voltage TH-HIGH and a second comparator reference voltage TH-LOW for the comparison operation of the comparator COMP. A level shifter L / S can also be connected between the output of the comparator COMP and the logic circuit BPCL. The level shifter L / S can reduce the voltage swing width of the comparator output VCO based on transistor-to-transistor (TTL) levels, allowing the comparator output VCO to be processed by the logic circuit BPCL.

[0095] The enable switch EN, connected between the second input (-) and the output of comparator COMP, can be turned on during initialization interval A, and thus the voltage VSIO of each of the detection line SIO and the comparator output VCO can be initialized to the detection reference voltage PCL.

[0096] In detection interval B following initialization interval A, the driving element of pixel PXL connected to each of the detection lines SIO can be turned off in response to the scan signal SCAN with an on level and the detection data voltage SVdata with an off level VOFF. In detection interval B, the voltage VSIO of the detection line SIO connected to the normal pixel PXL can be maintained at the detection reference voltage PCL, while the voltage VSIO of the detection line SIO connected to the defective pixel PXL can be increased or decreased from the detection reference voltage PCL. In detection interval B, comparator COMP can sequentially compare the voltage VSIO of the corresponding detection line SIO with two reference voltages Vref (i.e., the first comparator reference voltage TH-HIGH and the second comparator reference voltage TH-LOW) to generate the comparator output VCO. The comparator COMP can compare the voltage VSIO of the corresponding detection line SIO with the first comparator reference voltage TH-HIGH at the first timing T1 of the detection interval B to generate a first comparator output VCO1, and then compare the voltage VSIO of the corresponding detection line SIO with the second comparator reference voltage TH-LOW at the second timing T2 of the detection interval B to generate a second comparator output VCO2. As described above. Figure 6 The logic combination of the comparator output VCO and the first comparison output VCO1 and the second comparison output VCO2 in the logic circuit BPCL can determine whether the corresponding pixel has a defect and can perform dark spot processing operation based on the defect type.

[0097] Figure 10A and Figure 10B It shows the basis Figure 7 A diagram showing the defect handling method of the first embodiment. Figure 11A This is a diagram illustrating an example of detecting the Nth horizontal display line, which includes a target pixel with defects. Figure 11B and Figure 11C This is a diagram illustrating an example of detecting the Mth source driver integrated circuit connected to the target pixel in the Nth horizontal display line. Figure 11D This is a diagram illustrating an example of detecting the reference voltage line connected to the target pixel in the reference voltage line connected to the reference voltage line connected to the Mth source driver integrated circuit.

[0098] Reference Figure 10A and Figure 11AAccording to the first embodiment, the display defect processing method can perform an initial detection on a horizontal display line (hereinafter referred to as the target horizontal display line) including defective pixels when all multiplexer switches are turned on. To this end, the display defect processing method can apply a scan signal with an on level and a detection data voltage SVdata with an off level VOFF to the pixels included in each horizontal display line to detect whether a defect has occurred in each horizontal display line. This initial detection operation can be sequentially performed by a horizontal display line unit and can be repeated until the target horizontal display line is detected (S101 to S104).

[0099] The pixels included in the target horizontal display line can be divided into groups and can be connected to multiple source driver ICs (SD-ICs). Therefore, as... Figure 10A , Figure 11B and Figure 11C According to the first embodiment, the display defect processing method can perform secondary detection on a pixel group (hereinafter referred to as the target pixel group) including defective pixels when the multiplexer switch is selectively turned on by a source driver IC unit. For this purpose, the display defect processing method can apply a scan signal with an on level and a detection data voltage SVdata with an off level VOFF to the pixels included in each pixel group to detect whether a defect has occurred in each pixel group. This secondary detection operation can be performed sequentially on a pixel group basis and can be repeated until the target pixel group is detected (S105 and S106).

[0100] Pixels included in the target pixel group can be individually connected to multiple detection lines (SIO). Therefore, as... Figure 10A and Figure 11D According to the first embodiment, the display defect processing method can perform three detections on a detection line (hereinafter referred to as the target detection line SIO) connected to a defective pixel while a multiplexer switch is selectively turned on via a detection line SIO unit. To this end, the display defect processing method can apply a scan signal with an on level and a detection data voltage SVdata with an off level VOFF to the pixel connected to each detection line SIO to detect whether a defect has occurred in each detection line SIO. Such three detection operations can be sequentially performed by a detection line SIO unit and can be repeated until the target detection line SIO is detected (S107 and S108).

[0101] Subsequently, as Figure 10A According to the display defect processing method of the first embodiment, it can be determined that the pixel coordinates connected to the target detection line SIO are defective (S109).

[0102] Subsequently, as Figure 10BWhen a defective pixel affects the brightness of another pixel, the display defect processing method according to the first embodiment can compensate the image data to be applied to other pixels, and thus can prevent brightness changes caused by the defective pixel (S110 and S111).

[0103] Subsequently, as Figure 10B When RGB driving can be performed on a defect type (e.g., a GS short-circuit defect in a driving element), the display defect processing method according to the first embodiment can perform four detections on the defective pixel from the RGBW sub-pixels whose pixel coordinates are determined to be defective. For this purpose, the display defect processing method can apply a detection data voltage SVdata with an on-state VON only to one of the RGBW sub-pixels whose pixel coordinates are determined to be defective, in a state where the multiplexer switch connected to the target detection line SIO is selectively turned on, and can apply a detection data voltage SVdata with an off-state VOFF to the other sub-pixels. The detection data voltage SVdata with an on-state VON and the detection data voltage SVdata with an off-state VOFF can be applied synchronously with a scan signal with an on-state. This four-detection operation can be repeated until a defective sub-pixel is detected (S112 and S113).

[0104] Subsequently, as Figure 10B When it is determined that the W subpixel is defective, the display defect processing method according to the first embodiment can turn the W subpixel black and implement RGB driving by using RGB subpixels (S115). The display defect processing method can increase the image data to be applied to the RGB subpixels by more than the input value in order to perform RGB driving. This can be used to compensate for the brightness loss that occurs when the W subpixel included in the same pixel turns black.

[0105] In addition, such as Figure 10B When it is determined that one of the RGB sub-pixels is defective, the display defect handling method according to the first embodiment can turn all RGBW sub-pixels black (S116).

[0106] Figure 12 This is a diagram schematically illustrating a second embodiment of a comparator mounted on various source driver integrated circuits.

[0107] Reference Figure 12 The logic circuit BPCL and the reference voltage generation circuit PGMA can be mounted on the control PCB CPCB, and multiple comparators COMP can be configured and mounted on each of the source driver ICs SD-IC. In this case, the number of comparators COMP can be the same as the number of detection lines SIO. In the second embodiment, with Figure 7Unlike the first implementation, the multiplexer array can be omitted and the comparator COMP of the source driver IC SD-IC can perform detection operations simultaneously, thus reducing the detection time.

[0108] The comparator COMP may include: a first input terminal (+) through which a first comparator reference voltage TH-HIGH and a second comparator reference voltage TH-LOW are input; a second input terminal (-) through which the voltage VSIO of the detection line SIO is input; and an output terminal in which a comparator output VCO (i.e., a first comparator output VCO1 and a second comparator output VCO2) is generated.

[0109] The initialization switch RPRE can also be connected between the first input (+) and the second input (-) of the comparator COMP. The initialization switch RPRE can be turned off during the detection interval and turned on during the initialization interval preceding the detection interval. When the initialization switch RPRE is turned on simultaneously during the initialization interval, the voltage VSIO of each of the comparator COMP and the detection line SIO can be initialized to the detection reference voltage PCL from the reference voltage generation circuit PGMA.

[0110] Each of the source driver ICs SD-IC may also include a serialization circuit SLZ, which is commonly connected to the output of the comparator COMP. The serialization circuit SLZ serializes the first compare output VCO1 and the second compare output VCO2 from each input of the comparator COMP, and then provides the serially transmitted data to the logic circuit BPCL.

[0111] Figure 13 It shows in detail the basis Figure 12 The diagram shows the connection configuration of the second embodiment. Figure 14 It shows in detail the basis Figure 12 A diagram of the drive waveform for the connection configuration in the second embodiment.

[0112] Reference Figure 13 and Figure 14 The display panel PNL and the source PCB SPCB can be electrically connected to each other via a conductive film COF, and the source driver IC SD-IC can be integrated on the conductive film COF. In addition to the data driver 12 (see...), Figure 1 In addition to the serialization circuit SLZ and the transmitter Tx, the serialization circuit SLZ and the transmitter Tx can also be mounted on the source driver IC SD-IC. The transmitter Tx can output the serialized data processed by the serialization circuit SLZ through the internal interface circuit.

[0113] The source PCB (SPCB) and control PCB (CPCB) can be electrically connected to each other via flexible circuit cables (FFC), but are not limited thereto. The logic circuit (BPCL) can be connected to the timing controller 11 (see...). Figure 1 The timing controller 11 is integrated and can be mounted on the control PCC PCB. Figure 1 It may also include a receiver Rx connected to the transmitter TX via an internal interface circuit. The receiver Rx can receive serially transmitted data through the internal interface circuit and can provide the serially transmitted data to the logic circuit BPCL.

[0114] The comparator COMP, mounted on the source driver IC SD-IC, can be connected to different detection lines SIO. Additionally, the comparator COMP can be connected to the reference voltage generation circuit PGMA. Based on control by the logic circuit BPCL, the reference voltage generation circuit PGMA can generate a reference voltage Vref. The reference voltage Vref may include the detection reference voltage PCL to be charged into the detection line SIO, and a first comparator reference voltage TH-HIGH and a second comparator reference voltage TH-LOW for the comparison operation of the comparator COMP. A voltage buffer BUF can also be connected between the output of the comparator COMP and the logic circuit BPCL. The voltage buffer BUF can buffer the reference voltage Vref and can provide the buffered reference voltage Vref to the comparator COMP.

[0115] The initialization switch RPRE connected between the first input (+) and the second input (-) of comparator COMP can be turned on during the initialization interval A', and thus, the voltage VSIO of each of the detection line SIO and the comparator output VCO can be initialized to the detection reference voltage PCL.

[0116] In the detection interval B' following the initialization interval A', the driving element of pixel PXL connected to each of the detection lines SIO can be turned off in response to the scan signal SCAN with a conduction level and the detection data voltage SVdata with a cutoff level VOFF. In detection interval B', the voltage VSIO of the detection line SIO connected to the normal pixel PXL can be maintained at the detection reference voltage PCL, while the voltage VSIO of the detection line SIO connected to the defective pixel PXL can be increased or decreased from the detection reference voltage PCL. In detection interval B', the comparator COMP can sequentially compare the voltage VSIO of the corresponding detection line SIO with two reference voltages Vref (i.e., the first comparator reference voltage TH-HIGH and the second comparator reference voltage TH-LOW) to generate the comparator output VCO. The comparator COMP can compare the voltage VSIO of the corresponding detection line SIO with the first comparator reference voltage TH-HIGH at the first timing T1' of the detection interval B' to generate a first comparator output VCO1, and then compare the voltage VSIO of the corresponding detection line SIO with the second comparator reference voltage TH-LOW at the second timing T2' of the detection interval B' to generate a second comparator output VCO2. As described above. Figure 6 The logic combination of the comparator output VCO and the first comparison output VCO1 and the second comparison output VCO2 in the logic circuit BPCL can determine whether the corresponding pixel has a defect and can perform dark spot processing operation based on the defect type.

[0117] Figure 15 It shows the basis Figure 12 A diagram of the second embodiment of the defect handling method.

[0118] Reference Figure 15 The display defect processing method according to the second embodiment can detect horizontal display lines (hereinafter referred to as target horizontal display lines) including defective pixels by using all comparators. To this end, the display defect processing method can apply a scan signal with an on level and a detection data voltage SVdata with an off level VOFF to the pixels included in each horizontal display line to detect whether a defect has occurred in each horizontal display line. Such detection operations can be performed sequentially by a horizontal display line unit and can be repeated until the target horizontal display line is detected (S201 to S204).

[0119] When a target horizontal display line is detected, it is possible to detect whether any defects exist in the individual pixels configured to support that line. Therefore, as... Figure 15 According to the display defect processing method of the second embodiment, the coordinates of the defective pixel can be calculated (S205).

[0120] Subsequently, as Figure 15 When a defective pixel affects the brightness of another pixel, the display defect processing method according to the second embodiment can compensate the image data to be applied to other pixels, and thus can prevent brightness changes caused by the defective pixel (S206 and S207).

[0121] Subsequently, as Figure 15 When RGB driving can be performed on a defect type (e.g., a GS short-circuit defect in a driving element), the display defect processing method according to the second embodiment can detect defective pixels from among the RGBW sub-pixels whose defective pixel coordinates are determined. To this end, the display defect processing method can apply a detection data voltage SVdata with an on-state level VON only to one of the RGBW sub-pixels whose pixel coordinates are determined to be defective, and can apply a detection data voltage SVdata with a off-state level VOFF to the other sub-pixels. The detection data voltage SVdata with an on-state level VON and the detection data voltage SVdata with a off-state level VOFF can be applied synchronously with a scan signal having an on-state level. This sub-pixel detection operation can be repeated until a defective sub-pixel is detected (S208 and S209).

[0122] Subsequently, as Figure 15 When the W subpixel is determined to be defective, the display defect processing method according to the second embodiment can turn the W subpixel black and implement RGB driving by using RGB subpixels (S211). The display defect processing method can increase the image data to be applied to the RGB subpixels by more than the input value in order to perform RGB driving. This can be used to compensate for the brightness loss that occurs when the W subpixel included in the same pixel turns black.

[0123] In addition, such as Figure 15 When it is determined that one of the RGB sub-pixels is defective, the display defect handling method according to the second embodiment can turn all RGBW sub-pixels black (S212).

[0124] Figure 16 This is a diagram illustrating the connection configuration between pixel PXL and detection processing circuit 14 according to another embodiment of the present disclosure.

[0125] refer to Figure 16 The defect handling circuit 14 can perform its detection operation when the driving element is turned off. The defect handling circuit 14 may include a reference voltage generation circuit PGMA, a dynamic logic circuit DRC, a serialization circuit SLZ, and a logic circuit BPCL.

[0126] The reference voltage generation circuit PGMA and the logic circuit BPCL can be mounted on the control PCB, while the dynamic logic circuit DRC and the serialization circuit SLZ can be embedded in the source driver IC. Because quiescent current does not flow in the dynamic logic circuit DRC, power consumption can be low. Because the dynamic logic circuit DRC is configured as a simple logic gate, its circuit size can be small. The dynamic logic circuit DRC can be implemented with a small size, thus easily embedded in the source driver IC.

[0127] The reference voltage generation circuit PGMA can apply the detection reference voltage PCL to the detection line SIO during the initialization interval before the detection interval. When a short-circuit defect occurs in a sub-pixel of pixel PXL, the voltage VSIO of the detection line SIO may not be maintained at the detection reference voltage PCL during the detection interval, and can be increased or decreased from the detection reference voltage PCL.

[0128] The dynamic logic circuit DRC may include a first output node and a second output node connected between a high-level power (i.e., a first-level power) and a low-level power (i.e., a second-level power lower than the first-level power). The dynamic logic circuit DR can generate a first logic output through the first output node and a second logic output through the second output node. During the detection interval, the first logic output and the second logic output may vary based on the voltage of the detection line SIO offset from the detection reference voltage PCL.

[0129] The serialization circuit SLZ can serialize the first and second logic outputs from the dynamic logic circuit DRC, and then provide serially transmitted data to the logic circuit BPCL.

[0130] The BPCL logic circuit can determine whether a defect exists in a pixel based on a first logic output and a second logic output obtained during the detection interval. Alternatively, the BPCL logic circuit can determine whether a defect exists in a pixel based on a logical combination of the first and second logic outputs obtained during the detection interval. For example... Figure 23 As shown, the logical combination of the first logic output and the second logic output can be one of (0,0), (1,0) and (1,1).

[0131] The BPCL logic circuit can determine that pixel PXL is normal based on the logic combination (1,0). The BPCL logic circuit can determine that pixel PXL has an overflow-type defect 1 based on the logic combination (0,0). The BPCL logic circuit can determine that pixel PXL has an underflow-type defect 2 based on the logic combination (1,1). Overflow-type defect 1 and underflow-type defect 2 can be referred to above. Figure 6 As stated above.

[0132] The logic circuit BPCL can output a defect compensation signal based on the defective pixel PXL. Figure 1 Therefore, based on the defect compensation signal, black spot processing can be performed on the defective pixel PQL.

[0133] The logic circuit BPCL can generate the first switch control signal DET1 and the second switch control signal DET2 required for the operation of the dynamic logic circuit DRC. The logic circuit BPCL can be embedded in a timing controller.

[0134] Figure 17 It is shown Figure 16 A diagram showing the detailed connection configuration between the pixel PXL and the dynamic logic circuit DRC included in the detection processing circuit 14. Figure 18 It is shown Figure 17 The diagram shows the driving waveforms of the pixel PXI and the detection processing circuit.

[0135] refer to Figure 17 and Figure 18 The dynamic logic circuit DRC may include a first transistor TR1 to a third transistor TR3 for generating a first logic output DO through a first output node NX1, and a fourth transistor TR4 to a sixth transistor TR6 for generating a second logic output DU through a second output node NX2.

[0136] The first transistor TR1 to the third transistor TR3 can be connected in series between a high-level power supply VDH (i.e., the first-level power supply) and a low-level power supply VDL (i.e., a second-level power supply lower than the first-level power supply). The first transistor TR1 can be connected between the high-level power supply VDH and the first output node NX1, and can be turned on based on the first switch control signal DET1. The second transistor TR2 can be connected between the first output node NX1 and the first connection node Na1, and can be turned on based on the voltage VSIO of the detection line SIO. The third transistor TR3 can be connected between the first connection node Na1 and the low-level power supply VDL, and can be turned on based on the first switch control signal DET1. The first transistor TR1 can be a P-type transistor, and each of the second transistor TR2 and the third transistor TR3 can be an N-type transistor.

[0137] Transistors TR4 through TR6 can be connected in series between the high-level power supply VDH and the low-level power supply VDL. Transistor TR4 can be connected between the high-level power supply VDH and the second connection node Na2, and can be turned on based on the second switch control signal DET2. Transistor TR5 can be connected between the second output node NX2 and the second node Na2, and can be turned on based on the voltage VSIO of the detection line SIO. Transistor TR6 can be connected between the second output node NX2 and the low-level power supply VDL, and can be turned on based on the second switch control signal DET2. Each of transistors TR4 and TR5 can be a P-type transistor, and transistor TR6 can be an N-type transistor.

[0138] The first switch control signal DET1 and the second switch control signal DET2 can have opposite phases.

[0139] The initialization switch RPRE can be connected between the detection line SIO and the reference voltage generation circuit PGMA. The initialization switch RPRE can be turned on in initialization interval A1 and turned off in pre-charge interval A2 and detection interval A3. When the initialization switch RPRE is turned on in initialization interval A2, the voltage VSIO of the detection line SIO can be initialized to the detection reference voltage PCL.

[0140] The panel driving circuit can provide a scan signal SCAN with a conduction level and a detection data voltage SVdata with a cutoff level to the pixel PXL during the initialization interval A1, the pre-charge interval A2 and the detection interval A3, so as to cut off the driving elements included in the pixel PXL.

[0141] Figure 19 It is shown in Figure 18 A diagram of the precharge operation of the dynamic logic circuit performed during the precharge interval. Figure 20 It is shown in Figure 18 The diagram shows the first detection operation of the dynamic logic circuit performed during the detection interval. Figure 23 This is a diagram showing the output of the dynamic logic circuit for the defect handling circuit of the defect type.

[0142] refer to Figure 18 and Figure 19 During the pre-charge interval A2, the voltage VSIO of the detection line can be higher than the threshold voltage POL of the P-type transistor and lower than the threshold voltage NOL of the N-type transistor. As a result, during the pre-charge interval A2, the second transistor TR2 and the fifth transistor TR5 can be turned off.

[0143] refer to Figure 18 and Figure 19In the pre-charge interval A2, the first switch control signal DET1 can be maintained at a low voltage level LL, below the threshold voltage POL of the P-type transistor, and the second switch control signal DET2 can be maintained at a high voltage level HL, above the threshold voltage NOL of the N-type transistor. As a result, in the pre-charge interval A2, the first transistor TR1 and the sixth transistor TR6 can be turned on, and the third transistor TR3 and the fourth transistor TR4 can be turned off.

[0144] refer to Figure 18 and Figure 19 During the pre-charge interval A2, since the first transistor TR1 and the sixth transistor TR1 are switched on, the high output (i.e., the first output) based on the high-level power VDH can be pre-charged into the first output node NX1, and the low output (i.e., the second output lower than the first output) based on the low-level power VDL can be pre-charged into the second output node NX2. For convenience, the high output can be represented as '1' and the low output can be represented as '0'.

[0145] refer to Figures 20 to 22 In detection interval A3, the first switch control signal DET1 can be maintained at a high voltage level HL, which is higher than the threshold voltage of the N-type transistor, and the second switch control signal DET2 can be maintained at a low voltage level LL, which is lower than the threshold voltage of the P-type transistor. As a result, in detection interval A3, the third transistor TR3 and the fourth transistor TR4 can remain in the on state, while the first transistor TR1 and the sixth transistor TR6 can remain in the off state.

[0146] In detection interval A3, the second transistor TR2 and the fifth transistor TR5 can be based on the voltage VSIO of the detection line, such as... Figure 20 and Figure 21 As shown, it can be selectively switched on, or it can be as follows: Figure 22 All of the above are turned off.

[0147] See details Figure 18 , 20 In case 23, when pixel PXL has an overflow defect 1, the voltage VSIO of the detection line can be higher than the threshold voltage NOL of the N-type transistor. In this case, the second transistor TR2 can be turned on and the fifth transistor TR5 can be turned off. As a result, the first output node NX1 can be connected to the low-level power supply VDL through the second transistor TR2 and the third transistor TR3, and the first logic output DO can be shifted from the pre-charged high output '1' to the low output '0'. On the other hand, because the second output node NX2 is floating, the second logic output DU can be maintained as the pre-charged low output '0'.

[0148] refer to Figure 18 , 21In case 23, when pixel PXL has an underflow defect 2, the voltage VSIO of the detection line may be lower than the threshold voltage POL of the P-type transistor. In this case, the second transistor TR2 can be turned off and the fifth transistor TR5 can be turned on. Therefore, the second output node NX2 can be connected to the high-level power VDH through the fourth transistor TR4 and the fifth transistor TR5, and the second logic output DU may be shifted from the low output '0' after precharge to the high output '1'. On the other hand, because the first output node NX1 is floating, the first logic output DO can remain at the high output '1' after precharge.

[0149] refer to Figure 18 , 22 In step 23, when pixel PXL is normal, the voltage VSIO of the detection line can be higher than the threshold voltage POL of the P-type transistor in detection interval A3, and lower than the threshold voltage NOL of the N-type transistor. In this case, the second transistor TR2 and the fifth transistor TR5 can both be turned off. Because the first output node NX1 is floating, the first logic output DO can remain as a pre-charged high output '1'. Similarly, because the second output node NX2 is floating, the second logic output DU can remain as a pre-charged low output '0'.

[0150] Figure 24 This is a diagram illustrating the connection configuration between the pixel and the detection processing circuit 14 according to another embodiment of the present disclosure.

[0151] refer to Figure 24 The defect handling circuit 14 can perform its detection operation when the driving element is turned off. The defect handling circuit 14 may include a reference voltage generation circuit PGMA, a dynamic logic circuit DRC, a serialization circuit SLZ, and a logic circuit BPCL.

[0152] The reference voltage generation circuit PGMA and the logic circuit BPCL can be mounted on the control PCB, while the dynamic logic circuit DRC and the serialization circuit SLZ can be embedded in the source driver IC SD-IC. Because quiescent current does not flow in the dynamic logic circuit DRC, power consumption can be low. Because the dynamic logic circuit DRC is configured as a simple logic gate, its circuit size can be small. The dynamic logic circuit DRC can be implemented with a small size, thus easily embedded in the source driver IC.

[0153] The reference voltage generation circuit PGMA can apply a first detection reference voltage VL to the detection line SIO via a first initialization switch INTA during a first initialization interval before the first detection interval. The reference voltage generation circuit PGMA can also apply a second detection reference voltage VH, higher than the first detection reference voltage VL, to the detection line SIO via a second initialization switch INTB during a second initialization interval before the second detection interval. When a short-circuit defect occurs in pixel PXL, the voltage of the detection line SIO may not remain at the first detection reference voltage VL during the first detection interval and may increase from the first detection reference signal VL. When a short-circuit defect occurs in pixel PXL, the voltage of the detection line SIO may not remain at the second detection reference voltage VH during the second detection interval and may decrease from the second detection reference voltage VH.

[0154] The Dynamic Logic Circuit (DRC) may include a first output node and a second output node connected between a high-level power supply and a low-level power supply. The DRC can generate a first logic output through the first output node and a second logic output through the second output node. During a first detection interval, the first logic output may vary based on the voltage of the detection line SIO. During a second detection interval, the second logic output may vary based on the voltage of the detection line SIO.

[0155] The serialization circuit SLZ can serialize the first and second logic outputs from the dynamic logic circuit DRC, and then provide serially transmitted data to the logic circuit BPCL.

[0156] The BPCL logic circuit can determine whether a defect exists in a pixel based on a first logic output obtained in a first detection interval and a second logic output obtained in a second detection interval. The BPCL logic circuit can also determine whether a defect exists in a pixel based on the change in the first logic output obtained in a first initialization interval and a first detection interval. Furthermore, the BPCL logic circuit can determine whether a defect exists in a pixel based on the change in the second logic output obtained in a second initialization interval and a second detection interval.

[0157] When the first logic output in the first initialization interval differs from the second logic output in the first detection interval, the logic circuit BPCL can determine that pixel PXL has an overflow-type defect 1. When the second logic output in the second initialization interval differs from the second logic output in the second detection interval, the logic circuit BPCL can determine that pixel PXL has an underflow-type defect 2. On the other hand, when the first logic output in the first initialization interval is the same as the second logic output in the first detection interval, and the second logic output in the second initialization interval is the same as the second logic input in the second detection interval, the logic circuit BPCL can determine that pixel PXL is normal. The overflow-type defect 1 and the underflow-type defect 2 can be referred to above. Figure 6 As stated above.

[0158] The logic circuit BPCL can output a defect compensation signal based on the defective pixel PXL. Figure 1 Therefore, based on the defect compensation signal, the defective pixel PXL can be processed for dark spots.

[0159] The BPCL logic circuit can generate the first switch control signal DET1 and the second switch control signal DET2 required for the operation of the dynamic logic circuit DRC. The BPCL logic circuit can be embedded in a timing controller.

[0160] Figure 25 It is shown Figure 24 A diagram showing the detailed connection configuration between the pixels and dynamic logic circuits included in the detection and processing circuit. Figure 26 It shows Figure 25 The diagram shows the pixel and the driving waveform of the detection processing circuit. Figure 27 It is shown in Figure 26 A diagram showing the output of the dynamic logic circuit executed during the first initialization interval and the first detection interval. Figure 28 It is shown in Figure 26 The diagram shows the output of the dynamic logic circuit executed during the second initialization interval and the second detection interval.

[0161] refer to Figures 25 to 28 The dynamic logic circuit DRC may include a first transistor TR1 and a second transistor TR2 for generating a first logic output DO through a first output node NX1, and a third transistor TR3 and a fourth transistor TR4 for generating a second logic output DU through a second output node NX2.

[0162] The first and second transistors TR1 and TR2 can be connected in series between the high-level power supply VDH and the low-level power supply VDL. The first transistor TR1 can be connected between the high-level power supply VDH and the first output node NX1, and can be turned on based on the first switch control signal DET1. The second transistor TR2 can be connected between the first output node NX1 and the low-level power supply VDL, and can be turned on based on the voltage VSIO of the detection line. The first transistor TR1 can be a P-type transistor, and the second transistor TR2 can be an N-type transistor.

[0163] The third transistor TR3 and the fourth transistor TR4 can be connected in series between the high-level power supply VDH and the low-level power supply VDL. The third transistor TR3 can be connected between the high-level power supply VDH and the second output node NX2, and can be turned on based on the voltage VSIO of the detection line. The fourth transistor TR4 can be connected between the second output node NX2 and the low-level power supply VDL, and can be turned on based on the second switch control signal DET2. The third transistor TR3 can be a P-type transistor, and the fourth transistor TR4 can be an N-type transistor.

[0164] The panel driving circuit can provide a scan signal SCAN with a conduction level and a detection data voltage SVdata with a cutoff level to the pixel PXL in the first initialization interval B11, the first detection interval B12, the second initialization interval B21 and the second detection interval B21, so as to cut off the driving elements included in the pixel PXL.

[0165] The first initialization switch INTA can be turned on in the first initialization interval B11 and turned off in another interval. The second initialization switch INTB can be turned on in the second initialization interval B21. In the first initialization interval B11, the first detection reference voltage VL provided to the detection line SIO can be higher than the low-level power VDL and lower than the voltage W2 used to fully turn on the N-type transistor (i.e., the second transistor TR2). In the second initialization interval B21, the second detection reference voltage VH provided to the detection line SIO can be higher than the low-level power VDL. Furthermore, the second detection reference voltage VH can be lower than the high-level power VDH and higher than the voltage W1 used to fully turn on the P-type transistor (i.e., the third transistor TR3).

[0166] The first switch control signal DET1 can be maintained at a low voltage level LL in the first initialization interval B11 and at a high voltage level HL in other intervals. The low voltage level LL of the first switch control signal DET1 can be the voltage for fully turning on the P-type transistor (i.e., the first transistor TR1), and the high voltage level HL of the first switch control signal DET1 can be the voltage for fully turning off the P-type transistor. Therefore, the first transistor TR1 can remain in the on state based on the first switch control signal DET1 with a low voltage level LL in the first initialization interval B11, and can remain in the off state based on the first switch signal DET1 with a high voltage level HL in the first detection interval B12.

[0167] The second switch control signal DET2 can be maintained at a high voltage level HL in the second initialization interval B21 and at a low voltage level LL in other intervals. The high voltage level HL of the second switch control signal DET2 can be the voltage for fully turning on the N-type transistor (i.e., the fourth transistor TR4), and the low voltage level LL of the second switch signal DET1 can be the voltage for fully turning off the N-type transistor. Therefore, the fourth transistor TR4 can remain in the on state in the second initialization interval B21 based on the second switch control signal DET2 with a high voltage level HL, and can remain in the off state in the second detection interval B22 based on the second switching control signal DET1 with a low voltage level LL.

[0168] In the first initialization interval B11, in response to the first switch control signal DET1, the dynamic logic circuit DRC can charge the high output '1' to the first output node NX1 based on the high-level power VDH. In the second initialization interval B21, the dynamic logic circuit DRC can charge the low output '0' to the second output node NX2 based on the low-level power VDL.

[0169] When the voltage VSIO of the detection line in the first detection interval B12 is higher than the threshold voltage W2 or NOL of the N-type transistor, the second transistor TR2 can be turned on, the first output node NX1 can be connected to the low-level power VDL, and the first logic output RO can be offset from the high output '1' of the first initialization interval B11 to the low output '0' based on the low-level power VDL. Because the first logic output RO is offset to the low output '0' in the first detection interval B12, the logic circuit BPCL (see...) Figure 24 It can be determined that pixel PXL has an overflow-type defect 1.

[0170] On the other hand, when the voltage VSIO of the detection line in the first detection interval B12 is lower than the threshold voltage W2 or NOL of the N-type transistor, the second transistor TR2 can be turned off. Therefore, the first output node NX1 can be floated, and the first logic output RO can remain a high output '1' in the first initialization interval B11. Because the first logic output RO remains a high output "1" in the first detection interval B12, the logic circuit BPCL (see...) Figure 24 It can be confirmed that pixel PXL is normal.

[0171] When the voltage VSIO of the detection line in the second detection interval B22 is lower than the threshold voltage W1 or POL of the P-type transistor, the third transistor TR3 can be turned on, the second output node NX2 can be connected to the high-level power VDH, and the second logic output RU can be offset from the low output '0' of the second initialization interval B21 to the high output '1' based on the high-level power VDH. Because the second logic output RU is offset to the high output '1' in the second detection interval B22, the logic circuit BPCL (see...) Figure 24 It can be determined that pixel PXL has an underflow type defect 2.

[0172] On the other hand, when the voltage VSIO of the detection line is higher than the threshold voltage W1 or POL of the P-type transistor in the second detection interval B22, the third transistor TR3 may be turned off. Therefore, the second output node NX2 can be floated, and the second logic output RU can remain at the low output '0' of the second initialization interval B21. Because the second logic input RU remains at a low output '0' in the second detection interval B22, the logic circuit BPCL (see...) Figure 24 It can be confirmed that pixel PXL is normal.

[0173] This implementation method can achieve the following effects.

[0174] In this embodiment, two comparison outputs based on each pixel can be generated using a comparator included in the source driver IC or control PCB. In this embodiment, the presence or absence of a defect in the corresponding pixel can be determined based on the logical combination of the two comparison outputs.

[0175] According to this embodiment, two logic outputs based on each pixel can be generated using dynamic logic circuitry included in the source driver IC. In this embodiment, whether a defect exists in a corresponding pixel can be determined based on the logical combination of the two logic outputs or each of the two logic outputs individually.

[0176] Therefore, in this embodiment, display quality can be improved by detecting and compensating for hot spot defects caused by sub-pixel short circuits.

[0177] Furthermore, in this embodiment, the circuit unit used to detect and compensate for hot spot defects caused by sub-pixel short circuits can be minimized, thereby reducing manufacturing costs and increasing product lifespan and reliability.

[0178] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0179] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. An electroluminescent display device, comprising: Pixel, the pixel being connected to the detection line; A panel driving circuit, the panel driving circuit being configured to cut off driving of driving elements included in the pixel during a detection interval; A reference voltage generation circuit is configured to provide a detection reference voltage to the detection line before the detection interval, generate a first comparator reference voltage higher than the detection reference voltage during the detection interval, and generate a second comparator reference voltage lower than the detection reference voltage during the detection interval. A comparator configured to compare a first comparator reference voltage with the voltage of the detection line at a first timing of the detection interval to generate a first comparison output, and to compare a second comparator reference voltage with the voltage of the detection line at a second timing of the detection interval to generate a second comparison output; as well as A logic circuit configured to determine whether the pixel has a defect based on a first comparison output and a second comparison output obtained in the detection interval.

2. The electroluminescent display device according to claim 1, wherein, The logic circuit is further configured to determine whether the pixel has the defect based on a logical combination of the first comparison output and the second comparison output obtained in the detection interval.

3. The electroluminescent display device according to claim 1, wherein, The comparator, the logic circuit, and the reference voltage generation circuit are mounted on a control printed circuit board, and The number of comparators is less than the number of detection lines.

4. The electroluminescent display device according to claim 3, wherein, The comparator includes: a first input terminal through which a first comparator reference voltage and a second comparator reference voltage are input; a second input terminal through which the voltage of the detection line is input; and an output terminal through which a first comparison output and a second comparison output are generated. The electroluminescent display device further includes an enable switch connected between the second input terminal and the output terminal of the comparator. The logic circuit is further configured to turn off the enable switch during the detection interval and turn it on during an initialization interval prior to the detection interval. The reference voltage generation circuit is further configured to provide the detection reference voltage to the detection line via the comparator during the initialization interval.

5. The electroluminescent display device according to claim 3, further comprising: A plurality of source driver integrated circuits having multiplexer switches and a portion of the panel driver circuit mounted on the plurality of source driver integrated circuits. The comparator is connected to multiple detection lines via the multiplexer switch; and The logic circuit detects whether a pixel is defective based on the on or off state of the multiplexer switch through a horizontal display line unit comprising multiple pixels, then detects whether a pixel is defective through a source driver integrated circuit unit, and subsequently detects whether a pixel is defective through a detection line unit.

6. The electroluminescent display device according to claim 1 further includes a plurality of source driver integrated circuits, wherein, A portion of the panel driving circuit is mounted on the plurality of source driving integrated circuits. The comparators are configured as a plurality, and the plurality of comparators are mounted on each of the plurality of source driver integrated circuits. The logic circuit and the reference voltage generation circuit are mounted on a control printed circuit board, and The number of comparators is equal to the number of detection lines.

7. The electroluminescent display device according to claim 6, wherein, The comparator includes: a first input terminal through which a first comparator reference voltage and a second comparator reference voltage are input; a second input terminal through which the voltage of the detection line is input; and an output terminal through which the first comparison output and the second comparison output are generated. The electroluminescent display device further includes an initialization switch, which is connected between the first input terminal and the second input terminal of the comparator. The logic circuit turns off the initialization switch during the detection interval and turns on the initialization switch during the initialization interval preceding the detection interval. The reference voltage generation circuit is further configured to provide the detection reference voltage to the detection line via the comparator during the initialization interval.

8. The electroluminescent display device according to claim 6, wherein, Each of the plurality of source driver integrated circuits further includes a serialization circuit, and The serialization circuit is configured to serialize the first comparison output and the second comparison output from each of the plurality of comparators to provide serially transmitted data to the logic circuit.

9. The electroluminescent display device according to claim 1, wherein, The pixel includes multiple sub-pixels sharing the detection line, and When it is determined that one of the plurality of sub-pixels is defective, the logic circuit is further configured to perform dark spot processing only on the defective sub-pixel or to perform dark spot processing on the entire pixel including the defective sub-pixel.

10. An electroluminescent display device, comprising: Pixel, the pixel being connected to the detection line; A panel driving circuit, connected to the pixel and configured to provide the pixel with a scan signal having a conduction level and a detection data voltage having a cutoff level during a detection interval; The comparator includes a first input terminal for receiving a reference voltage and a second input terminal connected to the detection line; as well as A logic circuit configured to determine whether the pixel has a defect based on a first comparison output and a second comparison output of the comparator at a first timing and a second timing of the detection interval, respectively. Wherein, the reference voltage is: at the first timing stage, set to a first comparator reference voltage higher than the detected reference voltage; and at the second timing stage, set to a second comparator reference voltage lower than the detected reference voltage; and The detection reference voltage is the same as the voltage supplied to the detection line before the detection interval.

11. An electroluminescent display device, comprising: Pixel, the pixel being connected to the detection line; A panel driving circuit, the panel driving circuit being configured to cut off driving of driving elements included in the pixel during a detection interval; A reference voltage generation circuit is configured to provide a detection reference voltage to the detection line during an initialization interval prior to the detection interval. A dynamic logic circuit includes a first output node and a second output node connected between a first-level power and a second-level power below the first-level power. The dynamic logic circuit is configured to generate a first logic output through the first output node and a second logic output through the second output node, wherein the first logic output and the second logic output are offset based on the voltage of the detection line offset from the detection reference voltage in the detection interval. as well as A logic circuit configured to determine whether a defect exists in a pixel based on a first logic output and a second logic output obtained during the detection interval.

12. The electroluminescent display device according to claim 11, wherein, The logic circuit is configured to determine whether the defect occurs in the pixel based on a logical combination of the first logic output and the second logic output obtained in the detection interval, and In the pre-charge interval between the initialization interval and the detection interval, the dynamic logic circuit pre-charges the high output to the first output node based on the first level power and pre-charges the low output to the second output node based on the second level power.

13. The electroluminescent display device according to claim 12, wherein, When the voltage of the detection line is higher than the threshold voltage of the N-type transistor during the detection interval, The first output node is connected to the second level power, and the first logic output is shifted from the pre-charged first output to the second output. The second output node is floated, and the second logic output is maintained as the precharged second output.

14. The electroluminescent display device according to claim 12, wherein, When the voltage of the detection line is lower than the threshold voltage of the P-type transistor during the detection interval The first output node is floated and the first logic output is maintained as the pre-charged first output. The second output node is connected to the first level power, and the second logic output is offset from the precharged second output to the first output.

15. The electroluminescent display device according to claim 12, wherein, When the voltage of the detection line is higher than the threshold voltage of the P-type transistor and lower than the threshold voltage of the N-type transistor during the detection interval, The first output node is floated and the first logic output is maintained as the pre-charged first output. The second output node is floated, and the second logic output is maintained as the precharged second output.

16. The electroluminescent display device according to claim 12, wherein, The dynamic logic circuit includes: The first transistor is connected between the first power level and the first output node and is turned on based on the first switch control signal; The second transistor is connected between the first output node and the first connection node and is turned on based on the voltage of the detection line; The third transistor is connected between the first connection node and the second level power, and is turned on based on the first switch control signal; The fourth transistor is connected between the first power level and the second connection node and is turned on based on the second switch control signal; A fifth transistor is connected between the second output node and the second connection node and is switched on based on the voltage of the detection line; and The sixth transistor, which is connected between the second output node and the second power level and is turned on based on the second switch control signal, Wherein, each of the first transistor, the fourth transistor, and the fifth transistor is a P-type transistor, and Each of the second transistor, the third transistor, and the sixth transistor is an N-type transistor.

17. The electroluminescent display device according to claim 16, wherein, The first switch control signal and the second switch control signal have opposite phases.

18. The electroluminescent display device according to claim 16, wherein, During the pre-charge interval, the first switch control signal is maintained at a first voltage level lower than the threshold voltage of the P-type transistor, and the second switch control signal is maintained at a second voltage level higher than the threshold voltage of the N-type transistor. During the detection interval, the first switch control signal maintains a loss of the second voltage level, and the second switch control signal maintains the first voltage level.

19. The electroluminescent display device according to claim 11, further comprising a plurality of source driver integrated circuits, wherein, A portion of the panel driving circuit is mounted thereon, and The dynamic logic circuit is mounted on each of the plurality of source driver integrated circuits.

20. An electroluminescent display device, comprising: Pixels, the pixels being connected to the detection lines; A panel driving circuit, the panel driving circuit being configured to cut off driving of driving elements included in the pixel during a first detection interval and a second detection interval; A reference voltage generation circuit is configured to provide a first detection reference voltage to the detection line during a first initialization interval before the first detection interval, and to provide a second detection reference voltage to the detection line during a second initialization interval before the second detection interval; A dynamic logic circuit, comprising a first output node and a second output node connected between a first power level and a second power level below the first power level, the dynamic logic circuit being configured to generate a first logic output through the first output node and a second logic output through the second output node, the first logic output being offset based on the voltage of the detection line during a first detection interval, and the second logic output being offset based on the voltage of the detection line during a second detection interval. as well as A logic circuit configured to determine whether a defect exists in the pixel based on one of a first logic output obtained in the first detection interval and a second logic output obtained in the second detection interval.

21. The electroluminescent display device according to claim 20, wherein, The second detection reference voltage is higher than the first detection reference voltage, the first detection reference voltage is higher than the second level power, and the second detection reference voltage is lower than the first level power.

22. The electroluminescent display device according to claim 20, wherein, During the first initialization interval, in response to the first switch control signal, the dynamic logic circuit charges the first output node with a first output based on the first level of power, and During the second initialization interval, in response to the second switch control signal, the dynamic logic circuit charges the second output node with a second output that is lower than the first output based on the second level power.

23. The electroluminescent display device according to claim 22, wherein, The dynamic logic circuit includes: The first transistor is connected between the first power level and the first output node and is turned on based on the first switch control signal; The second transistor is connected between the first output node and the second level power, and is turned on based on the voltage of the detection line; A third transistor is connected between the first power level and the second output node, and is switched on based on the voltage of the detection line; and The fourth transistor is connected between the second output node and the second power level, and is turned on based on the second switch control signal. Wherein, each of the first transistor and the third transistor is a P-type transistor, and Each of the second transistor and the fourth transistor is an N-type transistor.

24. The electroluminescent display device according to claim 23, wherein, The first transistor remains in an on state during the first initialization interval based on a first switch control signal having a first voltage level, and remains in an off state during the first detection interval based on a first switch control signal having a second voltage level higher than the first voltage level. The fourth transistor remains in an on state during the second initialization interval based on the second switch control signal having a third voltage level, and remains in an off state during the second detection interval based on the first switch control signal having a fourth voltage level lower than the third voltage level.

25. The electroluminescent display device according to claim 23, wherein, When the voltage of the detection line is higher than the threshold voltage of the N-type transistor during the first detection interval, the second transistor is turned on, and therefore, the first output node is connected to the second level power, and the first logic output is shifted from the charged first output to a second output lower than the first output based on the second level power. When the voltage of the detection line is lower than the threshold voltage of the N-type transistor during the first detection interval, the second transistor is turned off. Therefore, the first output node is floated and the first logic output is maintained as the first output after charging.

26. The electroluminescent display device according to claim 23, wherein, When the voltage of the detection line is lower than the threshold voltage of the P-type transistor during the second detection interval, the third transistor is turned on, and therefore, the second output node is connected to the first power level, and based on the first power level, the second logic output is shifted from the charged second output to the first output, and When the voltage of the detection line is higher than the threshold voltage of the P-type transistor during the second detection interval, the third transistor is turned off. Therefore, the second output node is floated, and the second logic output is maintained as the second output after charging.

27. The electroluminescent display device according to claim 20 further comprises a plurality of source driver integrated circuits, wherein, A portion of the panel driving circuit is mounted thereon, and The dynamic logic circuit is mounted on each of the plurality of source driver integrated circuits.

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