Memory device and operating method thereof

Abstract

The present disclosure provides a memory device and an operating method thereof. The operating method includes programming a plurality of first strings representing a plurality of string pairs of a finite state machine to an on-memory search array of a memory device, programming a plurality of second strings of the string pairs to a plurality of memory addresses of a working memory of the memory device, and programming a string representing an initial state of the finite state machine to a buffer of the memory device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory device, in particular, a memory device for implementing a finite state machine. BACKGROUND

[0002] A finite state machine is a computational model that can be used to model sequential logic circuits and computer programs. Finite state machines can be implemented by software or hardware.

[0003] Finite state machines can generate regular languages. Regular expression matching is often implemented with finite state machines and can be applied in building models for mathematics, artificial intelligence, and linguistics.

[0004] When implementing regular expression matching and finite state machines in hardware, not only the computational efficiency but also the space efficiency should be considered. Therefore, a hardware implementation with both computational efficiency and space efficiency is an important research topic.

[0005] SUMMARY

[0006] Embodiments of the present disclosure provide a memory device. The memory device includes a first driving circuit, a second driving circuit, an in-memory search array, a sensing circuit, a working memory, and a buffer. The in-memory search array is coupled to the word line driving circuit, and includes a plurality of memory cells. The memory cells are coupled to the first driving circuit through a plurality of first signal lines, and coupled to the second driving circuit through a plurality of third signal lines. The memory cells are configured to store a plurality of first strings of a plurality of string pairs generated according to a finite state machine. The sensing circuit is coupled to the in-memory search array. The sensing circuit includes a plurality of sensing cells. The sensing amplifiers are coupled to the memory cells through a plurality of second signal lines. The working memory is coupled to the sensing circuit. The working memory has a plurality of memory addresses. The memory addresses one-to-one correspond to the sensing cells, and are configured to store a plurality of second strings of the string pairs. The buffer is coupled to the working memory and the word line driving circuit. The buffer is configured to store a string representing an initial state of the finite state machine when the finite state machine is initialized.

[0007] Another embodiment of the present disclosure discloses a method of operating a memory device, comprising: programming a plurality of first strings of a plurality of string pairs representing a finite state machine to an in-memory search array of a memory device; programming a plurality of second strings of the string pairs to a plurality of memory addresses of a working memory of the memory device; and programming a string representing an initial state of the finite state machine to a buffer of the memory device.

[0008] For a better understanding of the above-described and other aspects of the present disclosure, example embodiments will be described in detail herein below, in conjunction with the following drawings: BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1A A memory device according to an embodiment of the present disclosure.

[0010] Figure 1B A memory device according to another embodiment of the present disclosure.

[0011] Figure 2 A block diagram of a finite state machine.

[0012] Figure 3 A flowchart of a method of operating a memory device according to an embodiment of the present disclosure.

[0013] Figure 4 A flowchart of a method of operating a memory device according to another embodiment of the present disclosure.

[0014] Figures 5A-5C An operation schematic of a memory-based finite state machine according to an embodiment of the present disclosure.

[0015] REFERENCE NUMERALS

[0016] 10a, 10b: memory device

[0017] 102: word line drive circuit

[0018] 103: bit line drive circuit

[0019] 104a, 104b: in-memory search array

[0020] 105: sensing circuit

[0021] 106: working memory

[0022] 107: buffer

[0023] 108: memory controller

[0024] C11-Cmn: storage unit

[0025] ML1-MLn: second signal line

[0026] SL1-SLn: third signal line

[0027] SRL1-1, SRL1-2-SRLm-1, SRLm-2: first signal line

[0028] SA1-SAn: sensing unit

[0029] q1-q4: state

[0030] a, b: input

[0031] S301-S305, S401-S407: step DETAILED DESCRIPTION

[0032] Please refer to Figure 1A , Figure 1A A memory device according to an embodiment of the present disclosure. The memory device 10a includes a first drive circuit 102, a second drive circuit 103, an in-memory search array 104a, a sensing circuit 105, a work memory 106, a buffer 107, and a memory controller 108.

[0033] The in-memory search array 104a includes a plurality of memory cells C11-Cmn, a plurality of groups of first signal lines SRL1-1, SRL1-2-SRLm-1, SRLm-2, a plurality of second signal lines ML1-MLn, and a plurality of third signal lines SL1-SLn. Each memory cell Cij is coupled to the first driver circuit 102 through a corresponding group of first signal lines SRLi-1, SRLi-2, where i is an integer not less than 1 and not more than m. A plurality of memory cells C1j-Cmj form a memory cell string. Each memory cell string is coupled to the sensing circuit 105 through a corresponding second signal line MLj and coupled to the second driver circuit 103 through a corresponding third signal line SLj, where j is an integer not less than 1 and not more than n. In this embodiment, the in-memory search array 104a is a NOR type non-volatile memory. Each memory cell Cij can include two transistors, where the gates of the two transistors are coupled to the first signal lines SRLi-1, SRLi-2, respectively. This architecture is referred to as a ternary content addressable memory. The transistors can be metal field effect transistors, ferroelectric transistors, or any suitable transistors. By programming the combination of threshold voltages of the two transistors of each memory cell, the memory cells C11-Cmn can be programmed to store 0 and 1, or further, to store 0, 1, and [don't care], where [don't care] means that either 0 or 1 can be matched when searching. For simplicity of explanation, "memory cells programmed with a particular second / third signal line" will be simplified as "memory cells programmed with a particular second / third signal line", and "data string stored in memory cells with a particular second / third signal line" will be simplified as "data string stored with a particular second / third signal line".

[0034] The sensing circuit 105 can include a plurality of sensing units SA1-SAn. In this embodiment, the sensing units SA1-SAn are one-to-one coupled to the second signal lines ML1-MLn. The sensing units are used to output a signal according to the magnitude of the current flowing through the second signal line to which the sensing unit is coupled, where the signal outputted by the sensing unit represents whether the data string of the second signal line to which the sensing unit is coupled matches the data string to be searched. In one embodiment, when the current flowing through the second signal line to which the sensing unit is coupled is greater than a predetermined threshold, it is determined that the data string of the third signal line matches the data string to be searched.

[0035] The working memory 106 is coupled to the sensing circuit 105. The working memory 106 can be a volatile memory or a non-volatile memory. The working memory 106 includes a plurality of memory addresses. In one embodiment, the memory addresses can correspond one-to-one to the sensing units of the sensing circuit. The buffer 107 is coupled to the working memory 106 and the first driver circuit 102.

[0036] The memory controller 108 is coupled to the word line first driving circuit 102, the word line second driving circuit 103, the sensing circuit 105, the work memory 106 and the buffer 107, and controls the behaviors of the word line first driving circuit 102, the word line second driving circuit 103, the sensing circuit 105, the work memory 106 and the buffer 107 through signals.

[0037] Referring to Figure 1B , Figure 1B A memory device according to another embodiment of the present disclosure. The memory device 10b has a similar architecture as the memory device 10a, except that the in-memory search array 104b used is different from the in-memory search array 104a. In this embodiment, the in-memory search array 104b is a NAND type non-volatile memory, each memory cell includes two transistors connected in series, and a plurality of memory cells are connected in series between a second signal line and a third signal line to form a memory cell string for storing a data string.

[0038] To illustrate how the memory devices 10a, 10b implement a finite state machine, an actual finite state machine will be taken as an example below.

[0039] Referring to Figure 2 , Figure 2 is a block diagram of a finite state machine. The finite state machine 2 includes four states q1-q4, wherein q1 is an initial state, and q4 is a terminal state (or an accepting state), and a, b are inputs. According to the regular expression of the finite state machine 2, the state transition relationships of the finite state machine 2 are shown in Table 1. Table 1 shows eight state transition relationships of the finite state machine 2, including: if the current state is q1 and the input is a, then the next state is q2, and if the current input is b, then the next state is q3; if the current state is q2 and the current input is a, then the next state is q4, and if the current input is b, then the next state is q1; if the current state is q3 and the current input is a, then the next state is q1, and if the current input is b, then the next state is q4; if the current state is q4 and the current input is a, then the next state is q4, and if the current input is b, then the next state is q4. It should be noted that since how the finite state machine is converted into a regular expression is well known to those skilled in the art, further description is omitted here.

[0040] Table 1

[0041]

[0042] Next, the states q1-q4 of the finite state machine 2 and the allowable inputs a, b are encoded. In one embodiment, q1 is encoded as 00, q2 is encoded as 01, q3 is encoded as 10, q4 is encoded as 11, a is encoded as 0001, and b is encoded as 0010. After encoding, Table 1 can be converted to Table 2.

[0043] Table 2

[0044]

[0045]

[0046] According to the encoded states, the encoded allowable inputs, and the state transition relationship, a plurality of string pairs can be generated, where each string pair corresponds to the state transition relationship one-to-one, and each string pair includes a first string and a second string. The first string includes the encoded current state and the encoded current input. The second string includes the encoded next state. For example, the string pair corresponding to the state transition relationship "current state q1 (00) input a (0001) next state q2 (01)" is [000001, 01], the string pair corresponding to the state transition relationship "current state q1 (00) input b (0010) next state q3 (10)" is [000010, 10], and the rest are similar. That is, in each string pair, in the first string, a first part of the code word represents the current state, and a second part of the code word represents the current input, and the second string represents the next state corresponding to the current state and the current input. Table 3 shows an example of the string pairs of the finite state machine 2.

[0047] Table 3

[0048] First string Second string 000001 01 000010 10 010001 11 010010 00 100001 00 100010 11 110001 11 110010 11

[0049] Please refer to Figure 3 , Figure 3 is a flowchart of an operation method of a memory device according to an embodiment of the present disclosure. After encoding is completed and the string pairs are obtained, the finite state machine can be established on the memory device 10a (or the memory device 10b) by the operation method shown in Figure 3 .

[0050] In step S301, the memory is programmed according to the first string of the string pair. Assuming m is 6 and n is 8 in the architecture of the memory device 10a, the memory controller 108 instructs the first driving circuit 102 and the second driving circuit 103 to apply appropriate programming bias (depending on the actual hardware specification) to program the first string of the string pair one-to-one to different third signal lines. For example, the first string 000001 of the string pair corresponding to "current state ql, current input a, then next state is q2" can be programmed to the memory cells Cll~C61 on the third signal line SLl, the first string 000010 of the string pair corresponding to "current state ql, current input b, then next state is q3" can be programmed to the memory cells C12~C62 on the third signal line SL2, and so on.

[0051] In step S303, the working memory 106 is programmed according to the second string of the string pair. Assuming the memory device 10a, the second string 01 of the string pair corresponding to "current state ql, current input a, then next state is q2" can be programmed to the memory address corresponding to the second signal line MLl (sensing unit SA1), the second string 10 of the string pair corresponding to "current state ql, current input b, then next state is q3" can be programmed to the memory address corresponding to the third signal line ML2 (sensing unit SA2), and so on.

[0052] In step S305, the string corresponding to the initial state of the finite state machine is stored to the buffer. Step S305 is used to initialize the finite state machine established by steps S301 and S305.

[0053] Please refer to Figure 4 , Figure 4 the flowchart of the operation method of the memory device according to another embodiment of the present disclosure. Figure 4 The flow of Figure 3 may be continued after the flow of Figure 4 . Through the flow of

[0054] In step S401, the memory controller receives an input string. The input string is encoded from an input to be input to the finite state machine. For example, if the input is a, the input string is 0001, and if the input is b, the input string is 0010. In step S403, the memory controller commands the first driving circuit 102 to apply a plurality of first search voltages to the in-memory search array 104a / 104b based on a clock signal and according to the input string. For example, assuming the input is a, in a first clock cycle of the clock signal, the memory controller 108 commands the first driving circuit 102 to apply a first search voltage corresponding to 0 to the first signal line group SRL3-1, SRL3-2, a first search voltage corresponding to 0 to the first signal line group SRL4-1, SRL4-2, a first search voltage corresponding to 0 to the first signal line group SRL5-1, SRL5-2, and a first search voltage corresponding to 1 to the first signal line group SRL6-1, SRL6-2, according to the string 0001 representing a.

[0055] In step S405, the first driving circuit 102 applies a plurality of second search voltages to the in-memory search array 104a / 104b based on the clock signal and according to the string stored in the buffer 107. Continuing the previous example, in the first clock cycle, the buffer 107 stores 00 representing the initial state ql, so the first driving circuit 102 applies a second search voltage corresponding to 0 to the first signal line group SRL1-1, SRL1-2, and a second search voltage corresponding to 0 to the first signal line group SRL2-1, SRL2-2.

[0056] In step S407, the sensing circuit 105 obtains a detection result by detecting multiple currents flowing out of the search arrays 104a / 104b in the memory, and triggers the working memory 106 to output a second string stored in the memory address corresponding to the detection result to the buffer 107 based on the detection result. In one embodiment, the detection result indicates which sensing unit of the sensing circuit 105 detected a current greater than a preset threshold. The detection result can determine which data string on the third signal line is matched. Continuing the above example, the search voltage applied by the first driving circuit 102 to the first signal lines SRL1 to SRL6 represents the data string to be searched as 000001. The data string on the third signal line SL1 matches 000001, so the current greater than the preset threshold can be detected by the sensing unit SA1 through the storage units C11 to C16. The data strings on the third signal lines SL2 to SL8 do not match 000001, so no current greater than the preset threshold can be detected by the sensing units SA2 to SA8. Based on this detection result, the sensing circuit 105 outputs a signal causing the working memory 106 to output the second string 01 stored at the memory address corresponding to the sensing unit SA1 to the buffer 107. The string 00 originally stored in the buffer 107 will be overwritten by the string 01 output by the working memory 106. This step is equivalent to changing the current state from q1 to q2.

[0057] In practical applications, the inputs to the finite state machine will be a sequence of inputs. That is, multiple inputs are input to the finite state machine in a specific order. For such an input sequence, steps S401 to S407 will be executed repeatedly. The following will be combined with... Figures 5A-5C Let's illustrate this with a practical example. In Figures 5A-5C In this context, the field "First String" represents the first string stored on multiple different second signal lines (e.g., ML1 to ML8), and the field "Second String" represents the second string stored in working memory 106 at the memory address corresponding to those multiple second signal lines. The current state represents the data string currently stored in buffer 107, and the current input represents the input to be processed in the input sequence. For example, suppose the input sequence is a, a, b, a, b. The corresponding input strings are 0001, 0001, 0010, 0001, 0010. (Reference) Figure 5AThe left part of the figure, at a first clock cycle of the clock signal, the buffer 107 stores the initial state 00 (q1), the first driving circuit 102 applies the search voltage corresponding to 000001 (the combination of the current state 00 and the current input 0001, hereinafter the same) to the first signal line group SRL1-1, SRL1-2 ~ SRL6-1, SRL6-2, the sensing circuit 105 detects that the current flowing from the second signal line ML1 (000001 matches) is greater than the preset threshold, and the working memory 106 outputs the second string 01 (q2) stored in the memory address corresponding to the third signal line SL1 to the buffer 107 to overwrite 00 (q1). Referring to Figure 5A The right part of the figure, at a second clock cycle of the clock signal, the buffer 107 stores the current state 01 (q2), the first driving circuit 102 applies the search voltage corresponding to 010001 (the combination of 01 and 0001) to the first signal line group SRL1-1, SRL1-2 ~ SRL6-1, SRL6-2, the sensing circuit 105 detects that the current flowing from the second signal line ML3 (010001 matches) is greater than the preset threshold, and the working memory 106 outputs the second string 11 (q4) stored in the memory address corresponding to the third signal line SL3 to the buffer 107 to overwrite 01 (q2). Referring to Figure 5B The left part of the figure, at a third clock cycle of the clock signal, the buffer 107 stores the current state 11 (q4), the first driving circuit 102 applies the search voltage corresponding to 110010 (the combination of 11 and 0010) to the first signal line group SRL1-1, SRL1-2 ~ SRL6-1, SRL6-2, the sensing circuit 105 detects that the current flowing from the second signal line ML8 (110010 matches) is greater than the preset threshold, and the working memory 106 outputs the second string 11 (q4) stored in the memory address corresponding to the third signal line SL8 to the buffer 107 to overwrite 11 (q4). Referring to Figure 5B The right part of the figure, at a fourth clock cycle of the clock signal, the buffer 107 stores the current state 11 (q2), the first driving circuit 102 applies the search voltage corresponding to 110001 (the combination of 11 and 0001) to the first signal line group SRL1-1, SRL1-2 ~ SRL6-1, SRL6-2, the sensing circuit 105 detects that the current flowing from the second signal line ML7 (110001 matches) is greater than the preset threshold, and the working memory 106 outputs the second string 11 (q4) stored in the memory address corresponding to the third signal line SL7 to the buffer 107 to overwrite 11 (q4). Referring to Figure 5CIn the fifth clock cycle of the clock signal, the buffer 107 stores the current state 11 (q4), the first driving circuit 102 applies the search voltage corresponding to 110010 (the combination of 11 and 0010) to the first signal line group SRLl-l, SRLl-2 ~ SRL6-l, SRL6-2, the sensing circuit 105 detects that the current flowing from the second signal line ML8 (110010 matches) is greater than the preset threshold value, and the working memory 106 outputs the second string 11 (q4) stored in the memory address corresponding to the third signal line SL8 to the buffer 107 to overwrite 11 (q4).

[0058] After the steps S401 ~ S407 are performed for each input of the input sequence, it can be determined whether the input sequence is accepted by the finite state machine according to the string stored in the buffer 107. When the string finally stored in the buffer 107 represents the same state as the termination state, it can be determined that the input sequence is accepted by the finite state machine. For example, the buffer 107 finally stores the string 11 representing q4, and the string 00 representing the termination state ql is not stored. Therefore, it can be determined that the input sequence a, a, b, a, b is not accepted by the finite state machine 2, as shown in the lower right corner. The above determination can be performed by the memory controller 108 or by a dedicated circuit (not shown). Figure 5C

[0059] It should be noted that in the above process, the second driving circuit 103 will be controlled by the memory controller 108 to output the appropriate bias at the correct time to enable the operation of the in-memory search to proceed smoothly. The "correct time" and "appropriate bias" depend on the actual specifications of the memory device.

[0060] In order to improve the space efficiency of the in-memory search array, the string pairs can be integrated. When integrating, the different characters of the first string between at least two of the string pairs with the same second string are replaced with [arbitrary]. For example, Table Three can be integrated as shown in Table Four.

[0061] Table Four

[0062] First string Second string 000001 01 000010 10 010010 00 100001 00 1X0010 11 X10001 11

[0063] In Table Four, X represents [arbitrary]. In order to be able to program the first string of the string pair shown in Table Four, for example, the in-memory search array needs to have a storage unit supporting the programming of [arbitrary].

[0064] ​In view of the above, although the present disclosure has been disclosed with examples as above, it is not intended to limit the present disclosure. Those skilled in the art to which the present disclosure belongs, various modifications and improvements can be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be defined by the scope of the appended claims.

Claims

1. A memory device, comprising: First driving circuit; A second driving circuit; An in-memory search array includes multiple memory cells, which are coupled to a first driving circuit via multiple first signal lines and to a second driving circuit via multiple third signal lines. These memory cells are used to store multiple first strings of multiple string pairs generated according to a finite state machine. A sensing circuit includes multiple sensing units, which are coupled to the memory units via multiple second signal lines; A working memory, coupled to the sensing circuit, has multiple memory addresses that correspond one-to-one with the sensing units and is used to store multiple second strings of these string pairs; as well as A buffer, coupled to the working memory and the first driving circuit, is used to store a string representing an initial state of the finite state machine during initialization. Each of the first strings includes a first part codeword and a second part codeword, wherein the first part codeword is used to represent a current state and the second part codeword is used to represent a current input.

2. The memory device of claim 1, wherein each of the second strings represents the next state of the finite state machine corresponding to a current state and a current input.

3. The memory device of claim 1, wherein the sensing circuit is configured to cause the working memory to output the second string stored at the memory address of the sensing unit corresponding to the detected current being greater than a preset threshold to the buffer based on a detection result obtained through the sensing units.

4. The memory device of claim 1, wherein the first driving circuit is configured to apply a plurality of first search voltages representing an input of the finite state machine based on a clock signal and to apply a plurality of second search voltages based on the string stored in the buffer to the first signal lines.

5. A method of operating a memory device, comprising: Programming is used to search an in-memory array of multiple first strings representing multiple strings of a finite state machine to a memory device; Program multiple second strings of these string pairs to multiple memory addresses of a working memory of the memory device; as well as Program a string representing an initial state of the finite state machine to a buffer in the memory device; Each of the first strings includes a first part codeword and a second part codeword, wherein the first part codeword is used to represent a current state and the second part codeword is used to represent a current input.

6. The operation method according to claim 5, wherein each of the second strings is used to represent the next state of the finite state machine corresponding to a current state and a current input.

7. The operating method according to claim 5 further includes: A first drive circuit of the memory device applies a plurality of first search voltages representing an input of the finite state machine and a plurality of second search voltages based on the string stored in the buffer to the search array in the memory based on a clock signal.

8. The operating method according to claim 7, further comprising: A sensing circuit of the memory device, based on a detection result obtained by detecting a search array within the memory through a plurality of sensing units of the sensing circuit, causes the working memory to output the second string stored at the memory address of the sensing unit corresponding to the detected current being greater than a preset threshold to the buffer.

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