Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming an initial active layer and a first mask layer on the substrate; patterning the first mask layer to form a plurality of first grooves and a plurality of second grooves in the first mask layer, wherein the size of the first grooves along a first direction is greater than the size of the second grooves along a second direction; removing the initial active layer exposed in the first grooves, and removing the initial active layer exposed in the second grooves to form a plurality of active pillars, wherein the bottoms of the active pillars located in the same second direction are connected together. In the application, the bottoms of the active pillars located in the same second direction are connected together, and the bottoms of the active pillars located in the same second direction are used as a bit line, so that the stability of the voltage on the active pillars located in the same second direction can be ensured, and the performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] A transistor can be understood as a current switch structure made of semiconductor material. For example, a gate (metal) can be arranged between a source (semiconductor) and a drain (semiconductor), and the gate can be used to control the on-off of current between the source and the drain. One type of transistor is a GAA transistor. GAA stands for Gate-All-Around, which is a ring-shaped gate technology. The GAA transistor can also be called a GAAFET.

[0003] However, the existing GAA transistor has the technical problem of unstable voltage. SUMMARY

[0004] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a preparation method thereof, which are used to improve the stability of voltage on each active pillar and improve the performance of the semiconductor structure.

[0005] To achieve the above object, the embodiments of the present application provide the following technical solutions:

[0006] The first aspect of the embodiments of the present application provides a preparation method of a semiconductor structure, which comprises:

[0007] providing a substrate;

[0008] forming an initial active layer and a first mask layer which are sequentially and layerwisely arranged on the substrate;

[0009] patterning the first mask layer to form a plurality of first grooves and a plurality of second grooves in the first mask layer, the plurality of first grooves are arranged at intervals along a first direction, and each of the first grooves extends along a second direction, the plurality of second grooves are arranged at intervals along the second direction, and each of the second grooves extends along the first direction, wherein the first direction intersects the second direction, and the size of the first groove along the first direction is greater than the size of the second groove along the second direction;

[0010] removing the initial active layer exposed in the first grooves, and removing part of the initial active layer exposed in the second grooves to form a plurality of active pillars arranged in an array, wherein the bottoms of a plurality of active pillars located in the same second direction are connected together.

[0011] In some embodiments, after the step of forming the initial active layer and the first mask layer which are sequentially and layerwisely arranged on the substrate, and before the step of patterning the first mask layer, the preparation method further comprises:

[0012] forming a second mask layer on the first mask layer;

[0013] patterning the second mask layer to form a plurality of first intermediate trenches and a plurality of second intermediate trenches on the second mask layer, the plurality of first intermediate trenches are spaced apart along a first direction and each of the first intermediate trenches extends along a second direction, the plurality of second intermediate trenches are spaced apart along the second direction and each of the second intermediate trenches extends along the first direction, a size of the first intermediate trenches along the first direction is greater than a size of the second intermediate trenches along the second direction.

[0014] In some embodiments, the second mask layer is patterned by one or more of SADP, SARP, SAQP, and SAOP.

[0015] In some embodiments, the step of patterning the first mask layer comprises:

[0016] removing the first mask layer exposed in the first intermediate trenches and the second intermediate trenches to form first recesses and second recesses in the first mask layer.

[0017] In some embodiments, the step of forming the first mask layer and the initial active layer stacked sequentially on the substrate comprises:

[0018] forming a first initial active layer, a second initial active layer, and a third initial active layer stacked sequentially on the substrate, the first initial active layer is disposed on the substrate, and an etching rate of the second initial active layer is greater than etching rates of the first initial active layer and the third initial active layer.

[0019] In some embodiments, the first initial active layer and the third initial active layer have the same type of doped ions, and a material of the second initial active layer comprises silicon germanium.

[0020] In some embodiments, the first initial active layer, the second initial active layer, and the third initial active layer are formed by epitaxial growth with external doping.

[0021] In some embodiments, the step of removing the initial active layer exposed in the first recesses and removing part of the initial active layer exposed in the second recesses to form a plurality of active pillars arranged in an array comprises:

[0022] In the first direction cross section, the first initial active layer, the second initial active layer and the third initial active layer exposed in the first groove are removed to form a first opening in the first initial active layer, a second opening in the second initial active layer and a third opening in the third initial active layer, wherein the size of the second opening is larger than the size of the first opening and the third opening along the first direction;

[0023] In the second direction cross section, the second initial active layer and the third initial active layer exposed in the second groove are removed to form a fourth opening in the third initial active layer and a fifth opening in the second initial active layer, wherein the size of the fifth opening is larger than the size of the fourth opening along the second direction; the first initial active layer retained constitutes a first active layer, the second initial active layer retained constitutes a second active layer and the third initial active layer retained constitutes a third active layer.

[0024] In some embodiments, after the step of removing the initial active layer exposed in the first groove and removing part of the initial active layer exposed in the second groove to form a plurality of active pillars arranged in an array, the preparation method further comprises:

[0025] forming a third oxide layer, which wraps the side and top surfaces of each of the active pillars, covers the top surface of the substrate between adjacent active pillars along the first direction, and covers the top surface of the first active layer between adjacent active pillars along the second direction.

[0026] In some embodiments, the third oxide layer is formed by a thermal oxidation process.

[0027] In some embodiments, after the step of forming a third oxide layer, the preparation method further comprises:

[0028] forming a third dielectric layer between each of the active pillars, which has a top surface flush with the top surface of the first active layer in the first direction cross section.

[0029] In some embodiments, after the step of forming a third dielectric layer between each of the active pillars, the preparation method further comprises:

[0030] forming a conductive layer between each of the active pillars, which has a top surface flush with the top surface of the second active layer;

[0031] In the second direction cross section, the conductive layer exposed in the fourth opening is removed to separate the conductive layer into a plurality of first conductive layers and a plurality of second conductive layers, which are independent of each other and extend along the first direction.

[0032] In some embodiments, the step of removing the conductive layer exposed in the fourth opening along the second direction section comprises:

[0033] forming a third mask layer above the conductive layer and the active pillars;

[0034] removing part of the third mask layer along the second direction section to form a plurality of spaced-apart etching openings in the third mask layer, each of the etching openings extending along the first direction, and each of the etching openings exposing the fourth opening in the third active layer;

[0035] removing part of the conductive layer in each of the fifth openings to separate the conductive layer into a first conductive layer and a second conductive layer which are independent of each other and extend along the first direction.

[0036] In some embodiments, after the step of removing part of the conductive layer in each of the fifth openings, the preparation method further comprises:

[0037] a trench is formed between the first conductive layer and the second conductive layer in the same fifth opening, the trench extending along the first direction, a separation layer is formed in the trench, the separation layer also extending out of the trench and filling the area between adjacent active pillars.

[0038] In some embodiments, the step of forming a third dielectric layer between each of the active pillars comprises:

[0039] forming a third initial dielectric layer between each of the active pillars, a top surface of the third initial dielectric layer being flush with a top surface of the active pillars;

[0040] removing part of the thickness of the third initial dielectric layer, the remaining third initial dielectric layer constituting a third dielectric layer, and the third dielectric layer being located between adjacent first active layers along the first direction.

[0041] A second aspect of the embodiments of the present application provides a semiconductor structure, comprising:

[0042] a substrate;

[0043] a plurality of active pillars disposed on the substrate, the active pillars being spaced apart along a first direction, the active pillars being spaced apart along a second direction, and a plurality of the active pillars located along the same second direction having their bottoms connected together, the first direction being perpendicular to the second direction.

[0044] In some embodiments, in the first direction cross section, the active pillar comprises a first active layer, a second active layer and a third active layer, wherein the cross-sectional area of the second active layer is smaller than the cross-sectional area of the first active layer and the third active layer.

[0045] In some embodiments, the semiconductor structure further comprises a plurality of first conductive layers and a plurality of second conductive layers extending along the first direction, the plurality of first conductive layers and the plurality of second conductive layers are arranged alternately along a second direction;

[0046] and the first conductive layer and the second conductive layer located on both sides of the same active pillar are connected together and connected to all the active pillars in the first direction where the active pillar is located.

[0047] In some embodiments, further comprising an isolation layer, the isolation layer is arranged in the region surrounded by the third active layer of each active pillar and the region surrounded by the first conductive layer and the second conductive layer between adjacent active pillars.

[0048] In the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, the bottoms of the plurality of active pillars along the same second direction are connected together, and the bottoms of the plurality of active pillars along the same second direction are used as a bit line, so that the stability of the voltage on the plurality of active pillars along the same second direction is ensured, and the performance of the semiconductor structure is improved.

[0049] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions and the beneficial effects brought by these technical features, the other technical problems solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, the other technical features included in the technical solutions and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0051] Figure 1 The process flow chart of the preparation method of the semiconductor structure provided by the embodiments of the present application;

[0052] Figure 2 The structure schematic diagram of the film layer in the first direction in the preparation method of the semiconductor structure provided by the embodiments of the present application;

[0053] Figure 3 A structure schematic diagram of forming a film layer in a second direction in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0054] Figure 4 A structure schematic diagram of forming a mask pattern in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0055] Figure 5 A structure schematic diagram of forming a first oxide layer in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0056] Figure 6 A structure schematic diagram of forming a first dielectric layer in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0057] Figure 7 A structure schematic diagram of forming a first intermediate groove in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0058] Figure 8 A structure schematic diagram of forming a second pattern transfer layer and a second photoresist layer in a first direction in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0059] Figure 9 A structure schematic diagram of forming a second pattern transfer layer and a second photoresist layer in a second direction in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0060] Figure 10 A structure schematic diagram of patterning a second pattern transfer layer in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0061] Figure 11 A structure schematic diagram of forming a filling layer in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0062] Figure 12 A structure schematic diagram of forming a second intermediate groove in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0063] Figure 13 A structure schematic diagram of forming a first recess in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0064] Figure 14 A structure schematic diagram of forming a second recess in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0065] Figure 15 A structure schematic diagram of forming an active pillar in a first direction in the preparation method of the semiconductor structure provided by the embodiment of the present application;

[0066] Figure 16 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0067] Figure 17 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0068] Figure 18 A structure schematic view of the semiconductor structure in the second direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0069] Figure 19 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0070] Figure 20 A structure schematic view of the semiconductor structure in the second direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0071] Figure 21 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0072] Figure 22 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0073] Figure 23 A structure schematic view of the semiconductor structure in the second direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0074] Figure 24 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0075] Figure 25 A structure schematic view of the semiconductor structure in the second direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0076] Figure 26 A structure schematic view of the semiconductor structure in the second direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0077] Figure 27 A structure schematic view of the semiconductor structure in the first direction in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in the following figure.

[0078] Figure 28A structure schematic diagram of the semiconductor structure in a second direction after forming the first conductive layer and the second conductive layer in the preparation method of the semiconductor structure provided in the embodiments of the present application;

[0079] Figure 29 A structure schematic diagram of the semiconductor structure in a first direction after forming the isolation layer in the preparation method of the semiconductor structure provided in the embodiments of the present application;

[0080] Figure 30 A structure schematic diagram of the semiconductor structure in a second direction after forming the isolation layer in the preparation method of the semiconductor structure provided in the embodiments of the present application.

[0081] Reference signs:

[0082] 10: substrate;

[0083] 20: initial active layer; 21: first initial active layer; 211: first active layer; 22: second initial active layer; 221: second active layer; 23: third initial active layer; 231: third active layer; 24: first opening; 25: second opening; 26: third opening; 27: fourth opening; 28: fifth opening;

[0084] 30: first mask layer; 31: amorphous carbon layer; 32: silicon oxynitride layer;

[0085] 40: second mask layer; 41: first intermediate groove; 42: second intermediate groove;

[0086] 50: first pattern transfer layer; 51: first opening area; 52: first protrusion; 53: first oxide layer; 54: first dielectric layer;

[0087] 60: first photoresist layer; 61: first etching groove;

[0088] 70: second pattern transfer layer; 71: second opening area; 72: second protrusion;

[0089] 80: second photoresist layer; 81: second etching groove;

[0090] 90: filling layer; 91: second oxide layer; 92: second dielectric layer;

[0091] 100: third oxide layer;

[0092] 110: third dielectric layer;

[0093] 120: conductive layer; 121: first conductive layer; 122: second conductive layer; 123: groove;

[0094] 130: first region;

[0095] 140: third mask layer; 141: first sub mask layer; 142: second sub mask layer; 143: third sub mask layer; 144: etching opening;

[0096] 150: isolation layer. DETAILED DESCRIPTION

[0097] As described in the background, the transistor of the semiconductor structure in the related art has the problem of unstable voltage. The applicant has found that the cause of the problem is that, in forming the semiconductor structure, a plurality of bit lines are first formed in a substrate, and then a plurality of active pillars are formed on the substrate, each bit line is used to connect the source region or the drain region of each active pillar in the same row, and then a plurality of word lines are formed, the plurality of word lines are used to connect the channel region of each active pillar in the same column. However, in the above semiconductor structure, the voltages of the source regions or the drain regions of the active pillars in the same row are different, and it is difficult to ensure the stability of the threshold voltage of the active pillars in the same row.

[0098] In order to solve the above technical problem, in the embodiment of the present application, the bottoms of a plurality of active pillars in the same second direction are connected together, and the bottoms of the plurality of active pillars in the same second direction are used as a bit line, so that the stability of the voltage of the plurality of active pillars in the same second direction can be ensured, and the performance of the semiconductor structure is improved.

[0099] In order to make the above-mentioned purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0100] Figure 1 The flowchart of the preparation method of the semiconductor structure provided in the embodiments of the present application is shown in Figure 1, Figures 2-10 The schematic diagram of each stage of the preparation method of the semiconductor structure is shown in Figure 2, and the following will be described with reference to Figures 2-30 The preparation method of the semiconductor structure will be described in detail.

[0101] The semiconductor structure in the embodiments of the present application is not limited, and the following will be described taking a dynamic random access memory (DRAM) as an example, but the embodiments of the present application are not limited thereto, and the semiconductor structure in the embodiments of the present application can also be other structures.

[0102] As Figure 1 shown, the preparation method of the semiconductor structure provided in the embodiments of the present application includes the following steps:

[0103] Step S100: providing a substrate.

[0104] As shown in Figure 2 the substrate 10 is used as a support component of a dynamic random access memory for supporting other components arranged thereon, wherein the substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound.

[0105] Step S200: forming an initial active layer and a first mask layer which are arranged in sequence on the substrate.

[0106] With reference to Figure 2 the initial active layer 20 is formed on the substrate 10, wherein the initial active layer includes a first initial active layer 21, a second initial active layer 22 and a third initial active layer 23 which are arranged in sequence, and the first initial active layer 21 is arranged on the substrate 10.

[0107] In the embodiment, the first initial active layer 21, the second initial active layer 22 and the third initial active layer 23 are all formed by epitaxial growth with external doping. For example, hydrogen carrying silicon tetrachloride or trichlorosilane, silane or dichlorosilane, etc. can be introduced into a reaction chamber provided with the substrate, and a high-temperature chemical reaction is performed in the reaction chamber to reduce or thermally decompose the silicon-containing reaction gas, so that the silicon atoms epitaxially grow on the substrate to form a silicon layer. At the same time, by means of doping ions in the reaction chamber, the doping ions can be doped into the epitaxial layer of silicon while the epitaxial layer of silicon is formed, thereby forming the first initial active layer 21, wherein the doping ions can include boron ions or phosphorus ions.

[0108] After the first initial active layer 21 is formed, the second initial active layer 22 can be formed on the first initial active layer 21 by means of epitaxial growth with side doping, wherein the material of the second initial active layer 22 includes silicon germanide.

[0109] The forming process of the third initial active layer 23 is the same as that of the first initial active layer 21, and the embodiment will not be described again. In addition, the type of the doping ions of the third initial active layer 23 is the same as that of the first initial active layer 21.

[0110] In the embodiment, the etching rate of the second initial active layer 22 is greater than that of the first initial active layer 21 and the third initial active layer 23, so that when the initial active layer 20 is etched to form an active pillar in the subsequent process, the shape of the active pillar can be a structure with small middle and large ends.

[0111] After the third initial active layer 23 is formed, a first mask layer 30 is formed on the third initial active layer 23 by a deposition process. The first mask layer 30 can be a single film layer or a stacked structure. For example, the first mask layer 30 can include an amorphous carbon layer 31 and a silicon oxynitride layer 32 which are sequentially stacked. The amorphous carbon layer 31 is disposed on the third initial active layer 23. In this embodiment, the first mask layer 30 is a stacked structure, which can improve the accuracy in the pattern transfer process, thereby improving the yield of the semiconductor structure.

[0112] In this embodiment, the deposition process can include one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0113] In step S300, the first mask layer is patterned to form a plurality of first grooves and a plurality of second grooves in the first mask layer. The plurality of first grooves are spaced apart along a first direction, and each first groove extends along a second direction. The plurality of second grooves are spaced apart along the second direction, and each second groove extends along the first direction. The first direction intersects the second direction, and the size of the first groove along the first direction is greater than the size of the second groove along the second direction.

[0114] For example, continuing to refer to Figure 2 The second mask layer 40 can be formed on the first mask layer 30 by a deposition process. The material of the second mask layer 40 can include an oxide, such as silicon oxide.

[0115] Then, the second mask layer 40 is patterned to form a plurality of first intermediate grooves 41 and a plurality of second intermediate grooves 42 in the second mask layer 40. The plurality of first intermediate grooves 41 are spaced apart along a first direction, and each first intermediate groove 41 extends along a second direction. The plurality of second intermediate grooves 42 are spaced apart along the second direction, and each second intermediate groove 42 extends along the first direction. The size of the first intermediate groove 41 along the first direction is greater than the size of the second intermediate groove 42 along the second direction.

[0116] In this embodiment, the first direction intersects the second direction. For example, the first direction can be perpendicular to the second direction. The first direction can be an X direction, and the second direction can be a Y direction. Figure 2 Figure 3 In this embodiment, the first direction intersects the second direction. For example, the first direction can be perpendicular to the second direction. The first direction can be an X direction, and the second direction can be a Y direction.

[0117] For example, when the second mask layer 40 is patterned, one or more of SADP, SARP, SAQP, and SAOP can be used.

[0118] For example, as shown in Figure 2 and Figure 3 ​As shown, a first pattern transfer layer 50 with a mask pattern is formed on the second mask layer 40. The first pattern transfer layer 50 can be a stacked structure, for example, the first pattern transfer layer 50 includes a spin-coated carbon layer and a silicon oxynitride layer.

[0119] When forming the mask pattern, a first photoresist layer 60 of a certain thickness can be formed on the first pattern transfer layer 50 using a coating process.

[0120] Subsequently, by means of exposure, development or etching, a plurality of first etching grooves 61 are formed in the first photoresist layer 60. The plurality of first etching grooves 61 are spaced apart along the first direction, and each first etching groove 61 extends along the second direction.

[0121] Then, as Figure 4 As shown, the first pattern transfer layer 50 exposed in the first etching tank 61 is removed by etching gas or etching liquid to form a plurality of first opening regions 51 in the first pattern transfer layer 50, and a first protrusion 52 for separating each first opening region 51. The plurality of first opening regions 51 are spaced apart along a first direction, and each first opening region 51 extends along a second direction.

[0122] Finally, the first photoresist layer 60 is removed using a cleaning solution.

[0123] After removing the first photoresist layer 60, as follows Figure 5 As shown, a first oxide layer 53 is formed on the inner wall of the first opening region 51 and on the top surface of the first protrusion 52.

[0124] like Figure 6 As shown, a first dielectric layer 54 is formed in the area enclosed by the first oxide layer 53. The first dielectric layer 54 fills the area enclosed by the first oxide layer 53 and covers the top surface of the first oxide layer 53.

[0125] like Figure 7 As shown, the second mask layer 40, which is covered by the first dielectric layer 54, the first oxide layer 53, the first oxide layer 53 located on the sidewall of the first protrusion 52, and the first protrusion 52 are removed to form a plurality of first intermediate grooves 41 in the second mask layer 40, wherein the dimension of the first intermediate groove 41 along the first direction is denoted as A1.

[0126] like Figure 8 and Figure 9 As shown, a second pattern transfer layer 70 is formed on the retained second mask layer 40 using a deposition process. Part of the second pattern transfer layer 70 fills the first intermediate trench 41. The second pattern transfer layer 70 can be a stacked structure. For example, the second pattern transfer layer 70 may include a spin-coated carbon layer, a silicon oxynitride layer, a spin-coated carbon layer, and a silicon oxynitride layer stacked in sequence.

[0127] With reference to the above Figure 9 A second photoresist layer 80 of a certain thickness can be formed on the second pattern transfer layer 70 by a coating process, and then a plurality of second etching grooves 81 can be formed in the second photoresist layer 80 by exposure, development or etching.

[0128] As shown in Figure 10 , the second pattern transfer layer 70 of the remaining thickness exposed in the second etching grooves 81 is removed by etching gas or etching liquid to form a plurality of second opening regions 71 in the second pattern transfer layer 70 and a second protrusion 72 for separating the second opening regions 71, the second opening regions 71 are arranged along the second direction and each extends along the first direction.

[0129] As shown in Figure 11 , a filling layer 90 is formed in the second opening regions 71, the filling layer 90 fills the second opening regions 71, wherein the filling layer 90 includes a second oxide layer 91 formed in the second opening regions 71 and a second dielectric layer 92 formed on the second oxide layer 91, the material of the second oxide layer 91 can include silicon oxide, and the material of the second dielectric layer 92 can include spin-on carbon layer.

[0130] As shown in Figure 12 , the second mask layer 40 is removed by using the remaining second pattern transfer layer and the filling layer 90 as a mask to form a plurality of second intermediate grooves 42 in the second mask layer 40, wherein the size of the second intermediate grooves 42 along the second direction is denoted as A2, and A1 is greater than A2.

[0131] As shown in Figure 13 and Figure 14 , the first mask layer 30 exposed in the first intermediate grooves 41 and the second intermediate grooves 42 is removed by etching gas or etching liquid to form a first groove 33 and a second groove 34 in the first mask layer 30, wherein in Figure 13 , the area below the dashed line is the first groove 33, and in Figure 14 , the area below the dashed line is the second groove 34.

[0132] In this embodiment, the size of the first intermediate grooves 41 along the first direction is greater than the size of the second intermediate grooves 42 along the second direction, that is, A2 is greater than A1, so that after the first mask layer 30 in the first intermediate grooves 41 and the second intermediate grooves 42 is removed, the size of the first groove 33 along the first direction is greater than the size of the second groove 34 along the second direction in the first mask layer 30, wherein the size of the first groove 33 along the first direction is denoted as A3, the size of the second groove 34 along the second direction is denoted as A4, and A3 is greater than A4.

[0133] Step S400: removing the initial active layer exposed in the first groove, and removing the initial active layer exposed in the second groove to form a plurality of active pillars arranged in an array, wherein the bottoms of the active pillars in the same second direction are connected together.

[0134] Exemplarily, as shown in FIG. 4, in the first direction cross section, the first initial active layer 21, the second initial active layer 22 and the third initial active layer 23 exposed in the first groove are removed to form a first opening 24 in the first initial active layer 21, a second opening 25 in the second initial active layer 22 and a third opening 26 in the third initial active layer 23, wherein the size of the second opening 25 is larger than the sizes of the first opening 24 and the third opening 26 along the first direction. Figure 15 It should be noted that, in the embodiment, from bottom to top, the area between the first dashed line and the substrate 10 is the first opening 24, the area between the first dashed line and the second dashed line is the second opening 25, and the area above the second dashed line is the third opening 26.

[0135] Figure 15 In the embodiment, since the etching rate of the second initial active layer 22 is greater than the etching rates of the first initial active layer 21 and the third initial active layer 23, under the same etching conditions, the etching amount of the second initial active layer 22 is greater, and thus the size of the second opening 25 is greater.

[0136] Exemplarily, as shown in FIG. 5, in the second direction cross section, the second initial active layer 22 and the third initial active layer 23 exposed in the second groove are removed to form a fourth opening 27 in the third initial active layer 23 and a fifth opening 28 in the second initial active layer 22, wherein the size of the fifth opening 28 is greater than the size of the fourth opening 27 along the second direction.

[0137] It should be noted that, in the embodiment, the first opening 24, the second opening 25, the third opening 26, the fourth opening 27 and the fifth opening 28 are mutually connected. Figure 16 In the embodiment, since the size of the second groove 34 is smaller than the size of the first groove 33, under the same etching conditions, the amount of the etching liquid or the etching gas entering the second groove 34 is smaller, and thus the thickness of the removed initial active layer 20 is also smaller, so that part of the first initial active layer 21 in the second direction cross section is reserved.

[0138] It should be noted that, in the embodiment, the first opening 24, the second opening 25, the third opening 26, the fourth opening 27 and the fifth opening 28 are mutually connected.

[0139] In the embodiment, since the size of the second groove 34 is smaller than the size of the first groove 33, under the same etching conditions, the amount of the etching liquid or the etching gas entering the second groove 34 is smaller, and thus the thickness of the removed initial active layer 20 is also smaller, so that part of the first initial active layer 21 in the second direction cross section is reserved.

[0140] ​The first initial active layer 21 reserved constitutes a first active layer 211, the second initial active layer 22 reserved constitutes a second active layer 221, and the third initial active layer 23 reserved constitutes a third active layer 231, and the first active layer 211, the second active layer 221, and the third active layer 231 constitute a plurality of active pillars 29 arranged in an array.

[0141] The first active layer 211 in each active pillar 29 can be used as a source region or one of the source regions, the second active layer 221 can be used as a channel region, and the third active layer 231 can be used as the other of the source region or the drain region; for example, if the first active layer 211 is used as the source region, the third active layer 231 is correspondingly used as the drain region.

[0142] In this embodiment, by making the size of the second groove smaller than the size of the first groove, when the initial active layer exposed in the second groove and the first groove is removed, the etching thickness is different, thereby connecting the source regions or the drain regions of the bottoms of a plurality of active pillars in the same second direction together and using the source regions or the drain regions of the bottoms of the plurality of active pillars in the same second direction as a bit line, and there is no need to separately form a bit line as in the related art, which can ensure the stability of the voltage on the plurality of active pillars in the same second direction, thereby improving the performance of the semiconductor structure.

[0143] In some embodiments, as shown in Figure 17 and Figure 18 After the step of removing the initial active layer exposed in the first groove and removing part of the initial active layer exposed in the second groove to form a plurality of active pillars arranged in an array, the method for manufacturing the semiconductor structure further comprises:

[0144] forming a third oxide layer 100 wrapped around the side surface and the top surface of each active pillar 29, covering the top surface of the substrate 10 between the active pillars 29 adjacent in the first direction, and covering the top surface of the first active layer 211 between the active pillars 29 adjacent in the second direction.

[0145] In this step, the third oxide layer 100 can be formed by a thermal oxidation process, by adjusting the temperature of the reaction chamber to cause the surfaces of the active pillars 29 and the surfaces of the first active layer 211 to be oxidized to form the third oxide layer 100, and the third oxide layer 100 can be used as a gate oxide layer. The third oxide layer 100 in this embodiment is formed by a thermal oxidation process, which can simplify the preparation process of the third oxide layer 100.

[0146] As shown in Figures 19 to 21As shown, after the third oxide layer 100 is formed, a third dielectric layer 110 is formed between each active pillar 29. In the first direction section, the top surface of the third dielectric layer 110 is flush with the top surface of the first active layer 211.

[0147] For example, in such Figure 19 and Figure 20 As shown, a third initial dielectric layer 111 is formed between each active post 29, and the top surface of the third initial dielectric layer 111 is flush with the top surface of the active post 29.

[0148] like Figure 21 As shown, a portion of the thickness of the third initial dielectric layer 111 is removed, and the third initial dielectric layer 111 located between the first active layers 211 is retained. The retained third initial dielectric layer 111 constitutes the third dielectric layer 110, and the third dielectric layer 110 is located between adjacent active pillars along the first direction, and the third dielectric layer 110 extends along the second direction. The top surface of the third dielectric layer 110 is flush with the bottom surface of the channel region of the active pillar 29, that is, the top surface of the third dielectric layer 110 is flush with the bottom surface of the second active layer.

[0149] In other words, in this embodiment, the third initial dielectric layer 111 located in the second opening, the third opening, the fourth opening and the fifth opening is removed, and the initial dielectric layer 111 located in the first opening is retained to form the third dielectric layer 110.

[0150] In some embodiments, after the step of forming a third dielectric layer between the active pillars, the method for fabricating the semiconductor structure further includes:

[0151] like Figure 22 and Figure 23 As shown, a conductive layer 120 is formed between each active pillar 29 using a deposition process. The top surface of the conductive layer 120 is flush with the top surface of the second active layer 221, so that the conductive layer 120 covers the channel region of each active pillar 29. The second active layer 221 of each active pillar 29 constitutes the channel region. The material of the conductive layer 120 may include tungsten metal.

[0152] like Figures 24 to 28 As shown, along the second direction section, the conductive layer 120 exposed in the fourth opening is removed to separate the conductive layer 120 into multiple first conductive layers 121 and multiple second conductive layers 122 that are independent of each other and all extend along the first direction.

[0153] Multiple first conductive layers 121 and multiple second conductive layers 122 are alternately arranged along the second direction, and the first conductive layers 121 and the second conductive layers 122 located on both sides of the same active post 29 are connected together and connected to all active posts 29 in the first direction where the active post 29 is located.

[0154] In Figure 28 For example, the second active pillar 29 from left to right, the first conductive layer 121 is arranged on the left side of the active pillar 29, the second conductive layer 122 is arranged on the right side of the active pillar 29, and the first conductive layer 121 and the second conductive layer 122 are connected together between two adjacent active pillars 29 along the first direction, and are connected with all the active pillars 29 along the first direction in which the second active pillar 29 is located.

[0155] For example, as shown in Figure 24 and Figure 25 A third mask layer 140 is formed above each active pillar 29 and the conductive layer 120. In other words, each active pillar 29 and the conductive layer 120 form a first area 130, the third mask layer 140 is formed in the first area 130, the third mask layer 140 extends out of the first area 130 and covers the top surface of each active pillar 29.

[0156] In this embodiment, the third mask layer 140 can be formed by a deposition process, wherein the third mask layer 140 can include a laminated structure, for example, the third mask layer 140 includes a first sub-mask layer 141, a second sub-mask layer 142 and a third sub-mask layer 143 arranged in sequence, and part of the first sub-mask layer 141 is located in the first area. In addition, the first sub-mask layer 141 can be a spin-on carbon layer, the second sub-mask layer 142 can be a silicon oxynitride layer, and the third sub-mask layer 143 can be a photoresist layer.

[0157] As shown in Figure 26 On the second direction section, part of the third mask layer 140 is removed to form a plurality of spaced etching openings 144 in the third mask layer 140, that is, the plurality of etching openings 144 are spaced along the second direction, and each etching opening 144 extends along the first direction and exposes the fourth opening 27 located in the third active layer 231.

[0158] After the fourth opening 27 is exposed, etching gas can be introduced into the fourth opening 27 to remove part of the conductive layer 120 located in each fifth opening, that is, the conductive layer 120 exposed in each fourth opening 27 is removed to separate the conductive layer 120 located in each fifth opening into the first conductive layer 121 and the second conductive layer 122 which are independent of each other and extend along the first direction.

[0159] Among them, the first conductive layer 121 and the second conductive layer 122 located in the same fifth opening form a trench 123 therebetween, and the trench 123 extends along the first direction.

[0160] For example, as shown in Figure 28As shown, in the second direction, the conductive layer reserved on the right side of the first active pillar is referred to as the first conductive layer 121, and the conductive layer reserved on the left side of the second active pillar is referred to as the second conductive layer 122. The first conductive layer 121 and the second conductive layer 122 between the first active pillar and the second active pillar enclose a trench 123.

[0161] In the embodiment, in the second direction cross section, the distance between the second active layers of adjacent active pillars is greater than the distance between the third active layers, so the width of the conductive layer between the adjacent second active layers is greater than the distance between the adjacent third active layers. When the conductive layer between the second active layers is etched in the gap between the adjacent third active layers, the conductive layer between the second active layers can be divided into two parts, and the conductive layer between the second active layers can be prevented from being etched completely, thereby improving the yield of the semiconductor structure.

[0162] As shown in Figure 29 and Figure 30 , after the step of removing part of the conductive layer in each fifth opening, the method for manufacturing the semiconductor structure further comprises: forming an isolation layer 150 in the trench 123, and the isolation layer 150 also extends out of the trench 123 and fills the region between the adjacent active pillars 29.

[0163] Exemplarily, the deposition process can be used to form the isolation layer 150 in the trench 123, and the isolation layer 150 can fill the region surrounded by the third active layer 231 of each active pillar 29. The isolation layer 150 is used to isolate the first conductive layer 121 and the second conductive layer 122 between the adjacent active pillars 29, and is used to isolate the third active layer 231 of each active pillar 29.

[0164] The material of the isolation layer 150 can include silicon oxide or silicon nitride.

[0165] The embodiment of the application further provides a semiconductor structure, as shown in Figure 28 and Figure 29 , the semiconductor structure comprises a substrate 10 and a plurality of active pillars 29.

[0166] The plurality of active pillars 29 are arranged on the substrate 10. The active pillars 29 are arranged at intervals in the first direction, and the active pillars 29 are arranged at intervals in the second direction. The bottoms of all the active pillars 29 in the same second direction are connected together, wherein the first direction is perpendicular to the second direction.

[0167] This embodiment connects the source or drain regions at the bottom of all active pillars along the same second direction and uses the source or drain regions at the bottom of all active pillars along the same second direction as a single bit line, eliminating the need to form separate bit lines as in related technologies. This ensures the stability of the voltage on several active pillars along the same second direction, thereby improving the performance of the semiconductor structure.

[0168] In some embodiments, in a first directional cross section, the active column 29 includes a first active layer 211, a second active layer 221 and a third active layer 231, with the first active layer 211 disposed on the substrate 10.

[0169] The cross-sectional area of ​​the second active layer 221 is smaller than that of the first active layer 211 and the third active layer 231, and the size of the second active layer 221 first decreases and then increases.

[0170] This embodiment reduces the cross-sectional area of ​​the second active layer 221, making the second active layer 221 concave in shape. This arrangement facilitates the formation of the first and second conductive layers and improves the yield of the semiconductor structure.

[0171] In some embodiments, the semiconductor structure further includes multiple first conductive layers 121 and multiple second conductive layers 122, both of which extend along a first direction, and the multiple first conductive layers 121 and multiple second conductive layers 122 are alternately arranged along a second direction, wherein the first conductive layers 121 and the multiple second conductive layers 122 are made of the same material, namely tungsten metal.

[0172] Furthermore, the first conductive layer 121 and the second conductive layer 122 located on both sides of the same active post 29 are connected together and connected to all active posts 29 in the first direction where the active post 29 is located.

[0173] by Figure 30 Taking the orientation shown as an example, along the second direction, from left to right, they are successively called the first active pillar, the second active pillar... the fifteenth active pillar. Taking the second active pillar as an example, the placement of the first conductive layer 121 and the second conductive layer 122 will be explained in detail.

[0174] The second conductive layer 122 is disposed on the left side of the second active post 29, and the first conductive layer 121 is disposed on the right side of the second active post 29. Both the first conductive layer 121 and the second conductive layer 122 extend in a direction perpendicular to the plane of the paper. The first conductive layer 121 and the second conductive layer 122, which are located on both sides of the second active post 29, wrap around the active post 29 and are connected together between two adjacent active posts 29 in the first direction, and together with all active posts 29 in the first direction where the second active post 29 is located.

[0175] In some embodiments, the semiconductor structure further comprises an isolation layer 150, which is arranged in the region surrounded by the third active layer 231 of each active pillar 29, and the region surrounded by the first conductive layer 121 and the second conductive layer 122 between adjacent active pillars 29, wherein the isolation layer 150 is used to realize the insulation arrangement between the first conductive layer and the second conductive layer, and the insulation arrangement between each active pillar; in addition, the material of the isolation layer 150 can include silicon oxide or silicon nitride.

[0176] In the description of the present specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other.

[0177] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application.

[0178] In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0179] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, comprising the steps of: providing a substrate; forming an initial active layer and a first mask layer on the substrate in sequence; patterning the first mask layer to form a plurality of first grooves and a plurality of second grooves in the first mask layer, the plurality of first grooves are arranged in a first direction and each of the first grooves extends in a second direction, the plurality of second grooves are arranged in the second direction and each of the second grooves extends in the first direction, the first direction intersects the second direction, and a size of the first grooves in the first direction is greater than a size of the second grooves in the second direction; removing the initial active layer exposed in the first grooves and removing part of the initial active layer exposed in the second grooves to form a plurality of active pillars arranged in an array, wherein bottoms of a plurality of the active pillars in the same second direction are connected together. 2.The method of claim 1, wherein after the step of forming the initial active layer and the first mask layer on the substrate in sequence and before the step of patterning the first mask layer, the method further comprises: forming a second mask layer on the first mask layer; patterning the second mask layer to form a plurality of first intermediate grooves and a plurality of second intermediate grooves in the second mask layer, the plurality of first intermediate grooves are arranged in a first direction and each of the first intermediate grooves extends in a second direction, the plurality of second intermediate grooves are arranged in the second direction and each of the second intermediate grooves extends in the first direction, and a size of the first intermediate grooves in the first direction is greater than a size of the second intermediate grooves in the second direction. 3.The method of claim 2, wherein the second mask layer is patterned by one or more of SADP, SARP, SAQP and SAOP. 4.The method of claim 2, wherein in the step of patterning the first mask layer, the method comprises: removing the first mask layer exposed in the first intermediate grooves and the second intermediate grooves to form the first grooves and the second grooves in the first mask layer. 5.The method of any one of claims 1-4, wherein in the step of forming the initial active layer and the first mask layer on the substrate in sequence, the method comprises: the initial active layer comprises a first initial active layer, a second initial active layer and a third initial active layer, the first initial active layer is arranged on the substrate, and an etching rate of the second initial active layer is greater than etching rates of the first initial active layer and the third initial active layer. 6.The method of claim 5, wherein a type of doping ions of the first initial active layer and the third initial active layer is the same, and a material of the second initial active layer comprises silicon germanium. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. The method of claim 5, wherein the first, second and third initial active layers are formed by epitaxial growth with side doping.

8. The method of claim 5, wherein the step of removing the initial active layer exposed in the first recess and removing part of the initial active layer exposed in the second recess to form a plurality of active pillars arranged in an array comprises: removing the first, second and third initial active layers exposed in the first recess to form a first opening in the first initial active layer, a second opening in the second initial active layer and a third opening in the third initial active layer in a first direction cross-section, wherein the size of the second opening is larger than the size of the first and third openings along the first direction; and removing the second and third initial active layers exposed in the second recess to form a fourth opening in the third initial active layer and a fifth opening in the second initial active layer in a second direction cross-section, wherein the size of the fifth opening is larger than the size of the fourth opening along the second direction, the first initial active layer remaining forms a first active layer, the second initial active layer remaining forms a second active layer and the third initial active layer remaining forms a third active layer.

9. The method of claim 8, wherein after the step of removing the initial active layer exposed in the first recess and removing part of the initial active layer exposed in the second recess to form a plurality of active pillars arranged in an array, the method further comprises: forming a third oxide layer wrapping around the side and top surfaces of each of the active pillars, covering the top surface of the substrate between adjacent active pillars along the first direction and covering the top surface of the first active layer between adjacent active pillars along the second direction.

10. The method of claim 9, wherein the third oxide layer is formed by a thermal oxidation process.

11. The method of claim 9, wherein after the step of forming a third oxide layer, the method further comprises: forming a third dielectric layer between each of the active pillars, the top surface of the third dielectric layer being flush with the top surface of the first active layer in the first direction cross-section.

12. The method of claim 11, wherein after the step of forming a third dielectric layer between each of the active pillars, the method further comprises: forming a conductive layer between each of the active pillars, the top surface of the conductive layer being flush with the top surface of the second active layer; and removing the conductive layer exposed in the fourth opening along the second direction cross-section to separate the conductive layer into a plurality of first conductive layers and a plurality of second conductive layers which are independent of each other and extend along the first direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 13. The method of claim 12, wherein: removing the conductive layer exposed in the fourth openings in the second direction comprises: forming a third mask layer over the conductive layer and the active pillars; removing part of the third mask layer in the second direction to form a plurality of spaced-apart etching openings in the third mask layer, each of the etching openings extending in the first direction, and each of the etching openings exposing the fourth openings in the third active layer; removing part of the conductive layer in each of the fifth openings to separate the conductive layer into a first conductive layer and a second conductive layer, each of the first and second conductive layers extending in the first direction and being independent of each other.

14. The method of claim 13, wherein: after the step of removing part of the conductive layer in each of the fifth openings, the method further comprises: forming a trench between the first conductive layer and the second conductive layer in the same fifth opening, the trench extending in the first direction, and forming an isolation layer in the trench, the isolation layer further extending out of the trench and filling the area between adjacent active pillars.

15. The method of claim 11, wherein: in the step of forming a third dielectric layer between the active pillars, comprises: forming a third initial dielectric layer between the active pillars, the third initial dielectric layer having a top surface flush with the top surface of the active pillars; removing part of the thickness of the third initial dielectric layer, the remaining third initial dielectric layer constituting a third dielectric layer, and the third dielectric layer being located between adjacent first active layers in the first direction.

16. A semiconductor structure prepared by the method of any one of claims 1-15, comprising: a substrate; a plurality of active pillars disposed on the substrate, the active pillars being spaced apart in a first direction, the active pillars being spaced apart in a second direction, and the bottom of all the active pillars in the same second direction being connected together, the first direction being perpendicular to the second direction.

17. The semiconductor structure of claim 16, wherein: the active pillars comprise a first active layer, a second active layer, and a third active layer, wherein the second active layer has a smaller cross-sectional area than the first active layer and the third active layer.

18. The semiconductor structure of claim 17, wherein: the semiconductor structure further comprises a plurality of first conductive layers and a plurality of second conductive layers extending in the first direction, the plurality of first conductive layers and the plurality of second conductive layers being alternately disposed in the second direction; the first conductive layer and the second conductive layer on both sides of the same active pillar are connected together and connected to all the active pillars in the first direction in which the active pillar is located.

19. The semiconductor structure of claim 18, wherein: ​ Further comprising an isolation layer disposed within an area enclosed by the third active layer of each of the active pillars and an area enclosed by the first conductive layer and the second conductive layer between adjacent active pillars.

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