Die bonding structure, stacking structure, and method for manufacturing the same

Abstract

A die bonding structure includes a first die and a second die. The first die includes a first sealing ring and a plurality of first metal contacts, wherein the side surfaces of the first metal contacts are aligned with the first side surface of the first sealing ring. The second die includes a second sealing ring and a plurality of second metal contacts, wherein the side surfaces of the second metal contacts are aligned with the side surfaces of the second sealing ring. The first metal contacts are directly bonded to the second metal contacts, and the first sealing ring is directly bonded to the second sealing ring. Because the die can be bonded laterally and side-to-side via the copper metal contacts, the bonding spacing can be well controlled by designing the layout of the die.

Description

Technical Field

[0001] The present invention relates to a grain bonding structure, a stacking structure, and a method for manufacturing the grain bonding structure. Background Art

[0002] With the rapid development of the semiconductor industry, the packing density of various electronic components (such as transistors, diodes, resistors, and capacitors) has continued to improve. This improvement in electronic component packing density is primarily achieved by continuously reducing the feature size of components, allowing more components to be placed within a given area. Therefore, how to further increase component packing density has become a critical issue. Summary of the Invention

[0003] According to one embodiment of the present invention, a die bonding structure is provided, comprising a first die and a second die. The first die comprises a first seal ring and a plurality of first metal contacts, wherein a first group of the first metal contacts has side surfaces aligned with a first side surface of the first seal ring. The second die comprises a second seal ring and a plurality of second metal contacts, wherein side surfaces of the second metal contacts are aligned with side surfaces of the second seal ring. The first group of first metal contacts are respectively directly bonded to the second metal contacts, and the first seal ring is directly bonded to the second seal ring.

[0004] In some embodiments, the first sealing ring and the second sealing ring comprise the same material.

[0005] In some embodiments, the first sealing ring and the second sealing ring include SiN or SiCN.

[0006] In some embodiments, the first die and the second die are laterally bonded.

[0007] In some embodiments, the first metal contact and the second metal contact comprise copper.

[0008] In some embodiments, the first die includes an integrated circuit device surrounded by a first seal ring.

[0009] In some embodiments, the second die includes an integrated circuit device surrounded by a second seal ring.

[0010] In some embodiments, the first die and the second die have different sizes.

[0011] In some embodiments, the first die and the second die have different layouts.

[0012] In some embodiments, the die bonding structure further includes a third die, the third die including a third seal ring and a plurality of third metal contacts, wherein side surfaces of the third metal contacts are aligned with side surfaces of the third seal ring, and the third seal ring is directly bonded to the first seal ring.

[0013] In some embodiments, side surfaces of a second group of the first metal contacts are aligned with the second side surface of the first sealing ring, and the first metal contacts of the second group are directly bonded to the third metal contacts.

[0014] According to another embodiment of the present invention, a stacked structure is provided, comprising a circuit board, a first die, and a second die disposed on the circuit board. The first die includes a first sealing ring and a plurality of first metal contacts. The second die includes a second sealing ring and a plurality of second metal contacts. The first sealing ring is directly bonded to the second sealing ring, and the first metal contacts are directly bonded to the second metal contacts. The bonding direction between the first die and the second die is perpendicular to a normal direction of the circuit board.

[0015] In some embodiments, the first die and the second die have different sizes.

[0016] In some embodiments, the first die and the second die have different layouts.

[0017] In some embodiments, the first sealing ring and the second sealing ring include SiN or SiCN.

[0018] In some embodiments, the first metal contact and the second metal contacts include copper.

[0019] According to one embodiment of the present invention, a method for manufacturing a die bonding structure is provided, comprising cutting a first wafer to obtain a first die, wherein after cutting the first wafer, a first sealing ring and a plurality of first metal contacts are exposed from a side surface of the first die; cutting a second wafer to obtain a second die, wherein after cutting the second wafer, a second sealing ring and a plurality of second metal contacts are exposed from a side surface of the second die; and bonding the first sealing ring to the second sealing ring and bonding the first metal contact to the second metal contact.

[0020] In some embodiments, the step of cutting the first wafer includes performing a laser cutting process, and the laser cutting process is performed on the side surface of the first sealing ring.

[0021] In some embodiments, the step of cutting the second wafer includes performing a laser cutting process, and the laser cutting process is performed on the side surface of the second sealing ring.

[0022] In some embodiments, the method for fabricating a die-bonding structure further includes pre-cutting the first wafer and the second wafer using a blade. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To make the objects, features, advantages and embodiments of the present invention more clearly understood, the detailed description of the accompanying drawings is as follows:

[0024] Figure 1 1 is a top view of some embodiments of a wafer in the present invention.

[0025] Figure 2 for Figure 1 Schematic top view of area A of the wafer.

[0026] Figure 3 For the Figure 2 Cross-sectional view of line segment 3-3 in FIG.

[0027] Figure 4 For the Figure 2 Cross-sectional view of line segment 4-4 in FIG.

[0028] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12A 、 Figure 13A They are cross-sectional schematic diagrams of different steps of some embodiments of the method for manufacturing a stacked structure of the present invention.

[0029] Figure 12B and Figure 13B They are Figure 12A and Figure 13A Schematic diagram from above.

[0030] Figure 14 for Figure 11 Schematic diagram of the cross-section of the cut metal contacts.

[0031] Figure 15 Schematic top views of some embodiments of the stacking structure of the present invention. DETAILED DESCRIPTION

[0032] The following drawings and detailed descriptions clearly illustrate the spirit of the present invention. After understanding the preferred embodiments of the present invention, those skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

[0033] When an element is referred to as being "on," it can generally mean that the element is directly on another element or that there are other elements between the two elements. Conversely, when an element is referred to as being "directly on" another element, it can mean that there are no other elements between the two elements. As used herein, the term "and / or" includes any combination of one or more of the listed associated items.

[0034] In this document, it is understood that the terms "first," "second," and "third," etc., are used to describe various elements, components, regions, layers, and / or blocks. However, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer, and / or block. Therefore, a first element, component, region, layer, and / or block in the following text may also be referred to as a second element, component, region, layer, and / or block without departing from the spirit of the present invention.

[0035] When an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or an additional element may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no additional elements present.

[0036] Reference Figure 1 A top view of some embodiments of a wafer according to the present invention is provided. A wafer 10 having a semiconductor substrate is provided. In some embodiments, wafer 10 comprises a silicon substrate. Alternatively, wafer 10 may comprise another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, gallium aluminum arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination thereof.

[0037] In some embodiments, a silicon substrate is used as a base material, and multiple processes are performed thereon to provide different layers to form various features of integrated circuit devices. For ease of description, the features of integrated circuit devices are simplified in this application.

[0038] The wafer 10 is then cut to form a plurality of dies 100. The wafer 10 is cut along the dicing streets 20. That is, after the wafer 10 is cut along the dicing streets 20, a plurality of dies 100 are obtained. In the same wafer 10, the layout of the dies 100 is substantially the same.

[0039] Please refer to Figures 2 to 4 ,in Figure 2 for Figure 1 A schematic top view of region A of the wafer, Figure 3 For the Figure 2 The cross-section of line segment 3-3 in Figure 4 For the Figure 2 The cross-sectional view taken along line 4-4 in FIG. The region corresponding to each die 100 (hereinafter referred to as die region 100') includes a silicon substrate 110 and a device layer 120 formed on the silicon substrate 110. The device layer 120 includes a plurality of integrated circuit components 122, which may include active components such as transistors, switches, etc., and / or passive components such as resistors, capacitors, inductors, and converters.

[0040] A plurality of isolation structures 112 are formed and embedded in the silicon substrate 110 to electrically isolate adjacent integrated circuit devices 122. In some embodiments, the device layer 120 includes more than one metal layer 124 and a plurality of interconnect elements 126, wherein the metal layers 124 are interconnected through the interconnect elements 126. The device layer 120 further includes a dielectric layer 128. The dielectric layer 128 is disposed on the silicon substrate 110 and surrounds the integrated circuit devices 122, the metal layers 124, and the interconnect elements 126.

[0041] In some embodiments, the metal layer 124 includes metal lines 124A, metal connection pads 124B, and metal contacts 124C, wherein the interconnect elements 126 may be vias or plugs. The metal layer 124 and the interconnect elements 126 may be made of a metal, such as copper. The metal layer 124 and the interconnect elements 126 may be manufactured using a series of Cu damascene processes. For ease of illustration, the number of integrated circuit components 122, metal layers 124, and interconnect elements 126 in the figure is simplified.

[0042] More specifically, the metal layer 124 includes a topmost metal layer 124T, wherein the top surface of the topmost metal layer 124T is exposed to the dielectric layer 128, and the thickness of the topmost metal layer 124T is greater than the thickness of the other metal layers 124. The topmost metal layer 124T includes metal lines 124A, metal connection pads 124B, and metal contacts 124C. The metal contacts 124C are configured to be adjacent to the saw streets 20. The size of each metal connection pad 124B is larger than the size of each metal contact 124C, and the sizes and shapes of these metal connection pads 124B can be different. A portion of the metal connection pads 124B is connected to the metal contacts 124C of the same layer through the metal lines 124A. Alternatively, the metal connection pads 124B can be electrically connected to the underlying metal layer 124 through the internal connection element 126, so that the metal connection pads 124B are electrically connected to the integrated circuit element 122. In this way, the integrated circuit element 122 can be connected to an external circuit or controlled by an external circuit through the metal layer 124 and the interconnection element 126 .

[0043] The die region 100' further includes a seal ring 130 disposed on the device layer 120. From a top view, the seal ring 130 can be rectangular and is disposed around the periphery of the die region 100', thereby enclosing the integrated circuit device 122. A cross-section of the seal ring 130 below the topmost metal layer 124T shows that the top surface of the seal ring 130 contacts the bottom surface of the topmost metal layer 124T, while the bottom surface of the seal ring 130 contacts the top surface of the silicon substrate 110. Cross-sections of the seal ring 130 at other locations show that the top surface of the seal ring 130 is exposed to the dielectric layer 128, while the bottom surface of the seal ring 130 contacts the top surface of the silicon substrate 110. In this way, the seal ring 130 protects the integrated circuit device 122 from damage during subsequent processing.

[0044] In some embodiments, the sealing ring 130 is not aligned with the metal contact 124C. For example, the metal contact 124C of each topmost metal layer 124T has a first outer surface S1 facing the scribe line 20, and the sealing ring 130 has a second outer surface S2 facing the scribe line 20, and the first outer surface S1 is not aligned with the second outer surface S2. More specifically, the first outer surface S1 of the metal contact 124C is closer to the scribe line 20 than the second outer surface S2 of the sealing ring 130. In other words, the metal contact 124C protrudes from the sealing ring 130. The material of the sealing ring 130 is different from the material of the dielectric layer 128. For example, the material of the sealing ring 130 can be a nitride, such as SiN or SiCN, and the material of the dielectric layer 128 can be an oxide, such as SiO2.

[0045] Please refer to Figures 5 to 13B ,in Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12A 、 Figure 13A These are schematic cross-sectional views of some embodiments of the method for manufacturing a stacked structure of the present invention at different steps. Figure 12B and Figure 13B They are Figure 12A and Figure 13A For ease of illustration, only the silicon substrate 110, the metal contact 124C, the dielectric layer 128, and the sealing ring 130 are depicted in the cross-sectional schematic diagram, and the drawings are not drawn to scale.

[0046] Reference Figure 5The scribe line 20 is defined between the die regions 100 ′. More specifically, the scribe line 20 includes a portion of the dielectric layer 128 and the silicon substrate 110 between the die regions 100 ′, and there is no physical interface between the scribe line 20 and the die regions 100 ′.

[0047] Reference Figure 6 A partial sawing process is performed to partially remove the dielectric layer 128 at the saw streets 20 . In some embodiments, the partial sawing process is performed by sawing with a blade 30 .

[0048] Reference Figure 7 , the partial cutting process stops at the silicon substrate 110. In other words, the dielectric layer 128 forms a groove 22 after the blade cuts, and the silicon substrate 110 is exposed in the groove 22. A portion of the silicon substrate 110 is also removed in this partial cutting process.

[0049] Reference Figure 8 A plurality of masks 140 are formed over the die region 100'. The masks 140 may be patterned photoresist, which can be fabricated by coating the photoresist material on a substrate and then etching the photoresist material. The masks 140 at least cover the area encompassing the seal ring 130 and the metal contacts 124C, while the scribe line 20 is not covered by the masks 140.

[0050] Reference Figure 9 , an etching process is performed to remove the portion of the dielectric layer 128 not covered by the mask 140. In some embodiments, the etching process can be a wet etching process and an etchant with a higher etching rate for silicon oxide than for silicon and silicon nitride is selected. In this way, the sealing ring 130 can serve as an etching stop layer, and the side surface of the sealing ring 130 will be exposed after the etching process. In some embodiments, the etching process can be a dry etching process. If it is a dry etching process, the portion of the dielectric layer 128 covered by the mask 140 will still remain and the silicon substrate 110 corresponding to the cutting street 20 may be thinned.

[0051] Reference Figure 10 , mask 140 (see Figure 9 ) is removed, and a laser cutting process is performed using a laser beam 40. The laser cutting process is to cut along the side surface of the sealing ring 130. More specifically, the laser cutting process aligns the path of the laser beam 40 with the outer surface of the sealing ring 130. The laser cutting process passes through the metal contact 124C, and a portion of the metal contact 124C is also cut off after the laser cutting process. After the laser cutting process is performed, a plurality of dies 100 can be obtained, such as Figure 11 shown.

[0052] The cross section of the metal contact 124C after laser cutting shows Figure 14 The metal contact 124C includes a fill metal 124C1 and a barrier layer 124C2 that serves to underlie the fill metal 124C1. The fill metal 124C1 is exposed after the laser cutting process, while the barrier layer 124C2 serves to underlie the bottom and side surfaces of the fill metal 124C1. In some embodiments, the fill metal 124C1 may be made of copper, and the barrier layer 124C2 may be made of titanium.

[0053] Back again Figure 11 The wafer is cut along the sidewalls of the seal ring 130. The seal ring 130 can be made of a nitride material such as SN or SiCN. Therefore, there is a clear interface between the seal ring 130 and the dielectric layer 128 (if any remains), or between the seal ring 130 and the silicon substrate 110. In this way, the cutting path of the laser cutting can be well controlled.

[0054] In some embodiments, each die 100 includes a device layer 120 surrounded by a seal ring 130, and at least one metal contact 124C has an exposed surface aligned with the seal ring 130. The sidewalls of the seal ring 130, the sidewalls of the metal contact 124C, and the sidewalls of the silicon substrate 110 are substantially coplanar. Because the die 100 is cut using a two-step sawing process, including blade sawing and laser sawing, the sawed surface of the die 100 produced using the two-step sawing process has better smoothness and flatness than a single sawing process.

[0055] Reference Figure 12A and Figure 12B , a first die 100A from a first wafer and a second die 100B from a second wafer are provided. The first die 100A and the second die 100B are respectively obtained through a series of processes as described above, wherein the main difference between the first die 100A and the second die 100B is that the first die 100A is cut from the first wafer, and the second die 100B is cut from the second wafer. The sizes of the first die 100A and the second die 100B can be the same or different. The layouts of the first die 100A and the second die 100B can be different. The material of the sealing ring 130 of the first die 100A and the material of the sealing ring 130 of the second die 100B can be the same, so that the thermal expansion coefficient between the first die 100A and the second die 100B can be better balanced.

[0056] On the side where the first die 100A and the second die 100B are to be bonded, the number of metal contacts 124C of the first die 100A and the number of metal contacts 124C of the second die 100B are the same, and the arrangement of the metal contacts 124C of the first die 100A and the second die 100B is symmetrical.

[0057] After the first die 100A and the second die 100B are placed so as to contact each other with their bonding sides, a hybrid bonding process is performed to connect the metal contacts 124C of each first die 100A to the corresponding metal contacts 124C of the second die 100B.

[0058] In some embodiments, the hybrid bonding process includes performing a thermal compression process to allow the metal contact 124C of each first die 100A to be directly connected to the metal contact 124C of the corresponding second die 100B by a metal direct bonding method such as copper to copper, and the sealing ring 130 of the first die 100A and the silicon substrate 110 as well as the sealing ring 130 of the second die 100B and the silicon substrate 110 are also directly connected during the thermal compression process. In this way, a die bonding structure 50 (e.g., Figure 13A After the thermal compression bonding process, an annealing process may be performed to enhance the bonding strength and prevent structural delamination.

[0059] Optionally, a pre-cleaning process may be performed between the laser cutting process and the hybrid bonding process. In some embodiments, an acidic cleaning solution may be applied to the surfaces of the first die 100A and the second die 100B to remove native oxides on the surfaces of the metal contacts 124C of the first die 100A and the metal contacts 124C of the second die 100B. Unintended particles or impurities on the surfaces of the first die 100A and the second die 100B may also be removed during this pre-cleaning process.

[0060] After the hybrid bonding process is completed, a thinning process may optionally be performed on the die bonding structure 50. For example, the bonded first die 100A and second die 100B may be flipped upside down, and then the silicon substrate 110 of the bonded first die 100A and second die 100B may be ground to reduce the thickness of the bonded first die 100A and second die 100B. The thinning process is preferably performed after the hybrid bonding process is completed to ensure that the bond strength is not affected by performing the thinning process first.

[0061] Reference Figure 13A and Figure 13B, performing a pick-and-place process to transfer the die bonded structure 50 to the circuit board 150. This results in a die-to-die stack 200, in which the first die 100A and the second die 100B are bonded side-to-side. A series of wire bonding and packaging processes can then be performed to complete the package structure.

[0062] In some embodiments, the die-bonding structure 50, comprising a bonded first die 100A and a bonded second die 100B, is stacked on a circuit board 150 in a first direction D1, where the first direction D1 is parallel to the first die 100A, the second die 100B, and the normal to the major surface of the circuit board 150. The first die 100A and the second die 100B are bonded in a second direction D2, where the second direction D2 is perpendicular to the first direction D1. The first die 100A and the second die 100B are laterally bonded via metal contacts 124C disposed on the side surfaces of the first die 100A and the second die 100B. The metal contacts 124C comprise copper.

[0063] Reference Figure 15 , which is a top view schematically illustrating another embodiment of a stacking structure according to the present invention. The die-on-die stacking structure 200' includes a circuit board 150', a first die 100A', a second die 100B', and a third die 100C'. The first die 100A', the second die 100B', and the third die 100C' are arranged side-by-side and laterally bonded via metal contacts 124C on the side surfaces of the first die 100A', the second die 100B', and the third die 100C'. For example, the second die 100B' is laterally bonded to the first side surface of the first die 100A' via a first group of metal contacts 124C on the side surface of the first die 100A' and metal contacts 124C on the side surface of the second die 100B'. The third die 100C' is laterally bonded to the second side surface of the first die 100A' via a second group of metal contacts 124C on the side surface of the first die 100A' and metal contacts 124C on the side surface of the third die 100C'. In some embodiments, at least two of the first die 100A', the second die 100B', and the third die 100C' have different sizes. In some embodiments, at least two of the first die 100A', the second die 100B', and the third die 100C' have different layouts.

[0064] According to the various embodiments of the present invention described above, dies can be joined laterally and side-to-side via copper metal contacts. The bonding spacing can be well controlled by designing the die layout. Furthermore, the dies are cut using a two-step dicing process involving blade dicing and laser dicing, resulting in smoother side surfaces that facilitate hybrid bonding.

[0065] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0066]

Explanation of symbols

[0067] 10: Wafer

[0068] 20: Cutting Road

[0069] 22: Groove

[0070] 30: Blade

[0071] 40: Laser beam

[0072] 50: Grain bonding structure

[0073] 100: Grain

[0074] 100': Grain area

[0075] 100A, 100A': first grain

[0076] 100B, 100B': Second die

[0077] 100C': the third grain

[0078] 110: Silicon substrate

[0079] 112: Isolation Structure

[0080] 120: Component layer

[0081] 122: Integrated circuit components

[0082] 124:Metal layer

[0083] 124A: Metal wire

[0084] 124B: Metal connection pad

[0085] 124C:Metal contacts

[0086] 124C1: Filler Metal

[0087] 124C2: Barrier layer

[0088] 124T: Top metal layer

[0089] 126:Internal connection element

[0090] 128: dielectric layer

[0091] 130: Sealing ring

[0092] 140:Mask

[0093] 150: Circuit board

[0094] 200,200': Die-to-die stacking structure

[0095] S1: first outer surface

[0096] S2: Second outer surface

[0097] D1: First direction

[0098] D2: Second direction.

Claims

1. A grain bonding structure, characterized in that: Include: A first die comprising a first sealing ring and a plurality of first metal contacts, wherein a plurality of side surfaces of a first group of the first metal contacts are aligned with a first side surface of the first sealing ring; as well as The second die includes a second sealing ring and a plurality of second metal contacts, wherein the plurality of side surfaces of the second metal contacts are aligned with the side surface of the second sealing ring, wherein the side surfaces of the first metal contacts of the first group are directly and laterally bonded to the side surfaces of the second metal contacts, and the first sealing ring is directly bonded to the second sealing ring. 2 . The die bonding structure according to claim 1 , wherein the first sealing ring and the second sealing ring comprise the same material. 3 . The die bonding structure according to claim 1 , wherein the first seal ring and the second seal ring comprise SiN or SiCN. The die bonding structure according to claim 1 , wherein the first die and the second die are bonded laterally. The die bonding structure according to claim 1 , wherein the first metal contacts and the second metal contacts comprise copper. 6 . The die bonding structure as claimed in claim 1 , wherein the first die comprises an integrated circuit device surrounded by the first seal ring. 7 . The die bonding structure of claim 1 , wherein the second die comprises an integrated circuit device surrounded by the second seal ring. The die bonding structure as claimed in claim 1 , wherein the first die and the second die have different sizes. 9 . The die bonding structure as claimed in claim 1 , wherein the first die and the second die have different layouts.

10. The die bonding structure according to claim 1, wherein Also includes: The third die includes a third sealing ring and a plurality of third metal contacts, wherein the side surfaces of the plurality of third metal contacts are aligned with the side surface of the third sealing ring, and the third sealing ring is directly bonded to the first sealing ring.

11. The die bonding structure according to claim 10, wherein a plurality of side surfaces of a second group of the first metal contacts are aligned with the second side surface of the first sealing ring, and the side surfaces of the second group of the first metal contacts are directly and laterally bonded to the side surfaces of the third metal contacts.

12. A stacking structure, characterized in that: Include: circuit boards; A first die is disposed on the circuit board and includes a first sealing ring and a plurality of first metal contacts; and The second die is disposed on the circuit board and includes a second sealing ring and a plurality of second metal contacts. wherein the first sealing ring is directly connected to the second sealing ring, and the first metal contacts are directly connected to the second metal contacts respectively, and The bonding direction between the first die and the second die is perpendicular to the normal direction of the circuit board. The stack structure according to claim 12 , wherein the first die and the second die have different sizes. The stack structure according to claim 12 , wherein the first die and the second die have different layouts. The stack structure according to claim 12 , wherein the first seal ring and the second seal ring comprise SiN or SiCN. The stack structure according to claim 12 , wherein the first metal contacts and the second metal contacts comprise copper.

17. A method for manufacturing a grain bonding structure, characterized in that: Include: cutting the first wafer to obtain first dies, wherein after cutting the first wafer, the first sealing ring and the plurality of first metal contacts are exposed from the side surface of the first dies; cutting the second wafer to obtain second dies, wherein after cutting the second wafer, the second sealing ring and the plurality of second metal contacts are exposed from the side surface of the second dies; as well as The first sealing ring and the second sealing ring are joined together, and the side surfaces of the first metal contacts and the side surfaces of the second metal contacts are laterally joined together. 18 . The method for fabricating a die bonding structure according to claim 17 , wherein the step of cutting the first wafer comprises performing a laser cutting process, and the laser cutting process is performed on a side surface of the first sealing ring. 19 . The method for fabricating a die bonding structure according to claim 17 , wherein the step of cutting the second wafer comprises performing a laser cutting process, and the laser cutting process is performed while aligning with a side surface of the second sealing ring.

20. The method for manufacturing a die bonding structure according to claim 17, wherein: The method further comprises pre-cutting the first wafer and the second wafer with a blade.

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