Wiring substrate

Abstract

The present application provides a wiring substrate with high reliability in connection with electronic components. The wiring substrate of the embodiment has: a first conductor layer (112) having a first conductor pad (P1) and a second conductor pad (P2); a second insulating layer (210) having a first opening (110a) exposing the first conductor pad (P1) and a second opening (110b) exposing the second conductor pad (P2); a metal pillar (MP) filling the first opening (110a); and a wiring structure (WS) disposed in the second opening. The upper surface of a first surface side connection pad (OP) of the wiring structure (WS) constitutes a component mounting surface having first, second, and third component mounting regions (EA1, EA2, EA3), and the first surface side connection pads are respectively disposed in the component mounting regions (EA1, EA2, EA3). The first surface side connection pads disposed in the component mounting regions (EA1, EA2) are electrically connected to the first surface side connection pads disposed in the component mounting region (EA3).

Description

TECHNICAL FIELD

[0001] The present application relates to a wiring substrate. BACKGROUND

[0002] In Patent Literature 1, a semiconductor package in which a plurality of semiconductor chips are mounted on another organic wiring substrate mounted on a wiring substrate is disclosed. The plurality of semiconductor chips are arranged so that their entirety is housed on the upper surface of the organic wiring substrate.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2020-191323

[0004] In the wiring substrate disclosed in Patent Literature 1, the organic wiring substrate has a size of the entire region including the region in which the plurality of semiconductor chips are mounted. It is considered that the organic wiring substrate is likely to be deformed because the size in the planar direction of the organic wiring substrate is relatively large, and that the connection between the organic wiring substrate and the semiconductor chips can be poor. SUMMARY

[0005] The wiring substrate of the present application has: a first insulating layer; a first conductor layer formed on the first insulating layer and having a plurality of first conductor pads and a plurality of second conductor pads; a second insulating layer formed on the first conductor layer and having a first opening exposing the first conductor pads and a second opening exposing the plurality of second conductor pads; a metal pillar formed on the first conductor pads and filling the first opening; and a wiring structure having a first surface having a plurality of first surface-side connection pads and a second surface having second surface-side connection pads on the side opposite to the first surface, the wiring structure being arranged in the second opening with the second surface-side connection pads connected to the second conductor pads. The upper surfaces of the plurality of first surface-side connection pads and the upper surface of the metal pillar constitute a component mounting surface having a first component mounting region, a second component mounting region adjacent to the first component mounting region, and a third component mounting region adjacent to the first component mounting region, the plurality of first surface-side connection pads being arranged in the first component mounting region, the second component mounting region, and the third component mounting region, respectively, first surface-side connection pads of the plurality of first surface-side connection pads arranged in the first component mounting region and the second component mounting region being electrically connected to each other, and first surface-side connection pads arranged in the first component mounting region and the third component mounting region being electrically connected to each other.

[0006] According to the embodiment of the present application, the component mounting surface of the wiring substrate is constituted by the wiring structure and the metal pillar. Therefore, it is possible to provide a wiring substrate in which the enlargement of the size in the planar direction of the wiring structure is relatively suppressed and the connection reliability of the wiring structure to electronic components is high. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a cross-sectional view showing one example of a wiring substrate of one embodiment of the present application.

[0008] Figure 2A is a cross-sectional view showing one example of a wiring substrate of one embodiment of the present application. Figure 1 is an enlarged view of a wiring structure in the example of the wiring substrate.

[0009] Figure 2B is an enlarged view of a wiring structure in another example of the wiring substrate of one embodiment of the present application.

[0010] Figure 3A is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0011] Figure 3B is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0012] Figure 3C is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0013] Figure 3D is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0014] Figure 3E is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0015] Figure 3F is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0016] Figure 4A is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0017] Figure 4B is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0018] Figure 4C is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0019] Figure 4D is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0020] Figure 4E is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0021] Figure 4F is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0022] Figure 4G This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0023] Figure 4H This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0024] Figure 4I This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0025] Label Explanation

[0026] 1: Wiring substrate; 10: First stacked layer; 20: Second stacked layer; 101, 11, 21: Insulating layers; 102, 12, 22: Conductor layers; 111: First insulating layer; 112: First conductor layer; 110: Second insulating layer; 210: Third insulating layer; 31: Resin insulating layer; 32, 320: Wiring layers; 100: Core substrate; 103: Through-hole conductor; 13, 23, 33: Via conductor; 110a, 110b, 210a: Openings; P1: First conductor pad; P2: Second conductor pad; OP: Connecting pad (first side connecting pad); IP: Connecting pad (second side connecting pad); WS: Wiring structure; MP: Metal pillar; UF: Insulating film for bottom filling; BP: Bump; IS: Component mounting surface; EA1, EA2, EA3: Component mounting areas; E1, E2, E3: Electronic components; GS1: First support substrate; GS2: Second support substrate; FW: Micro-wiring. Detailed Implementation

[0027] A wiring substrate according to one embodiment of the present invention will be described with reference to the accompanying drawings. Furthermore, the accompanying drawings herein do not represent exact ratios of the structural elements, but are depicted in a manner that facilitates understanding of the features of the present invention. Figure 1 In this paper, a cross-sectional view of wiring substrate 1 is shown as an example of the structure that a wiring substrate can have as an embodiment.

[0028] like Figure 1 As shown, the wiring substrate 1 has a core substrate 100 comprising an insulating layer (core insulating layer) 101 and conductor layers (core conductor layers) 102 formed on both sides of the core insulating layer 101. Insulating layers and conductor layers are alternately stacked on both sides of the core substrate 100. In the illustrated example, a first stacked portion 10, consisting of insulating layers 11, 111 and conductor layers 12, 112, is formed on one side F1 of the core substrate 100. Furthermore, a second stacked portion 20, consisting of insulating layer 21 and conductor layer 22, is formed on the other side F2 of the core substrate 100.

[0029] In addition, in the description of the wiring substrate of the present embodiment, the side away from the core insulating layer 101 is referred to as "upper", "upper side", "outer side", or "outside", and the side close to the core insulating layer 101 is referred to as "lower", "lower side", "inner side", or "inside". In addition, in each structural element, the surface on the side opposite to the core substrate 100 is also referred to as "upper surface", and the surface on the side of the core substrate 100 is also referred to as "lower surface". Therefore, in the description of each element constituting the wiring substrate 1, the side away from the core substrate 100 is also referred to as "upper side", "upper", "upper layer side", "outer side", or simply "upper" or "outside", and the side close to the core substrate 100 is also referred to as "lower side", "lower", "lower layer side", "inner side", or simply "lower" or "inside".

[0030] The outermost insulating layer 111 among the insulating layers constituting the first build-up layer 10 is also referred to as the first insulating layer 111. In addition, the outermost conductor layer 112 among the conductor layers constituting the first build-up layer 10 is also referred to as the first conductor layer 112. The second insulating layer 110 covering the first conductor layer 112 and the first insulating layer 111 exposed from the conductor pattern of the first conductor layer 112 is formed on the first build-up layer 10. The third insulating layer 210 is formed on the second build-up layer 20. The second insulating layer 110 and the third insulating layer 210 can be, for example, solder resist layers constituting the outermost insulating layers of the wiring substrate 1.

[0031] The openings 110a, 110b are formed in the second insulating layer 110. The openings 110a, 110b are through-holes that pass through the second insulating layer 110 in the thickness direction, the opening 110a is filled with a conductor, and the wiring structure WS is disposed in the opening 110b. The wiring structure WS contains relatively fine wires and can have circuit wires with a relatively high density. In addition, the opening 110a is also referred to as the first opening 110a, and the opening 110b is also referred to as the second opening 110b. The conductor filling the opening 110a constitutes the outermost surface of the wiring substrate 1 and forms a metal pillar MP that can be used for connection of the wiring substrate 1 to an external electronic component. The upper surface of the wiring structure WS disposed in the opening 110b constitutes the outermost surface of the wiring substrate 1 like the metal pillar MP and has a connection pad OP that can be used for connection of the wiring substrate 1 to an external electronic component. The opening 210a is formed in the third insulating layer 210, and the conductor pad 22p of the outermost conductor layer 22 in the second build-up layer 20 is exposed from the opening 210a.

[0032] The insulating layers 101, 11, 111, 21 that constitute the wiring substrate 1 can be formed using, for example, an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin. Each of the insulating layers 101, 11, 111, 21 can contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. The second insulating layer 110 and the third insulating layer 210, which are the solder resist layers, can be formed using, for example, a photosensitive epoxy resin or a polyimide resin.

[0033] The insulating layer 101 of the core substrate 100 is formed with a via conductor 103 that connects the conductor layer 102 constituting one face Fl in the core substrate 100 and the conductor layer 102 constituting the other face F2. The insulating layers 11, 111, 21 are each formed with a via conductor 13, 23 that connects the conductor layers sandwiching the insulating layer 11, 111, 21 to each other.

[0034] The conductor layers 102, 12, 112, 22, the via conductors 13, 23, the via conductor 103, and the metal post MP are formed using any metal such as copper or nickel, and can be constituted by, for example, a metal foil such as a copper foil and / or a metal film formed by plating or sputtering. The conductor layers 102, 12, 112, 22, the via conductors 13, 23, the via conductor 103, and the metal post MP are shown in a single-layer structure in Figure 1 , but can include a multi-layer structure having two or more metal layers. For example, the conductor layer 102 formed on the surface of the insulating layer 101 can have a three-layer structure including a metal foil (preferably a copper foil), an electroless plating film (preferably an electroless copper plating film), and an electrolytic plating film (preferably an electrolytic copper plating film). In addition, the conductor layers 12, 112, 22, the via conductors 13, 23, the via conductor 103, and the metal post MP can have, for example, a two-layer structure including an electroless plating film and an electrolytic plating film.

[0035] Each of the conductor layers 102, 12, 112, 22 of the wiring substrate 1 is patterned to have a prescribed conductor pattern. In particular, the first conductor layer 112 is formed to have a pattern of a plurality of first conductor pads P1 and a plurality of second conductor pads P2. The first conductor pads P1 of the first conductor layer 112 are connected to the metal post MP. That is, the first conductor pads P1 of the first conductor layer 112 can be electrically connected to an external electronic component that can be mounted on the wiring substrate 1 via the metal post MP. In addition, the plurality of second conductor pads P2 of the first conductor layer 112 are exposed within the opening 110b and connected to the connection pads IP of the wiring structure WS disposed within the opening 110b. In detail, as described with reference to Figure 2A and Figure 2BAs will be described later, the connection pad IP and the connection pad OP can be electrically connected via the conductor within the wiring structure WS. Therefore, the 2nd conductor pad P2 can be electrically connected with the external electronic component via the connection pads IP, OP.

[0036] The 1st conductor layer 112 in the wiring substrate 1 includes a plurality of 1st conductor pads P1 connected with the external electronic component via the metal pillar MP and a plurality of 2nd conductor pads P2 connected with the external electronic component via the wiring structure WS. The upper surface of the connection pad OP of the wiring structure WS and the upper surface of the metal pillar MP constitute one component mounting surface in the wiring substrate 1 that can connect the external electronic component. In other words, the distance from the upper surface of the 1st insulating layer 111 of the upper surface of the wiring structure WS (the upper surface of the connection pad OP) and the distance from the upper surface of the 1st insulating layer 111 of the upper surface of the metal pillar MP are substantially equal. Further, the component mounting surface is indicated by a broken line IS in the drawing. Figure 1

[0037] The component mounting surface constituted by the upper surface of the connection pad OP and the upper surface of the metal pillar MP has a plurality of component mounting regions, and in the illustrated example, has the component mounting regions EA1, EA2, EA3. The component mounting regions EA1, EA2, EA3 respectively correspond to regions where the electronic components E1, E2, E3 are to be mounted. The upper surface of the metal pillar MP and the upper surface of the connection pad OP can be electrically and mechanically connected with the external electronic component via a conductive joining material (not shown) such as solder between the connection pads of the external electronic component, for example.

[0038] In the illustrated example, the plurality of connection pads OP formed on the upper surface of the wiring structure WS are respectively located in the three component mounting regions EA1, EA2, EA3. That is, the wiring structure WS is disposed across the three component mounting regions EA1, EA2, EA3. In addition, a part of the component mounting surface constituted by the upper surface of the connection pad OP and the upper surface of the metal pillar MP in addition to the upper surface of the connection pad OP includes a region other than the region where the wiring structure WS is disposed. Specifically, in the illustrated example, a part of the component mounting region EA2 and a part of the component mounting region EA3 correspond to the upper surface of the metal pillar MP. Further, the component mounting region EA1 is also referred to as the 1st component mounting region EA1, the component mounting region EA2 is also referred to as the 2nd component mounting region EA2, and the component mounting region EA3 is also referred to as the 3rd component mounting region EA3.

[0039] ​That is, the component mounting area in the wiring substrate of the embodiment occupies not only the area where the wiring structure is disposed, but also the area where the metal pillar MP is formed. In other words, when an external electronic component is mounted on the wiring substrate of the embodiment, the electronic component can be connected to both the wiring structure WS and the metal pillar MP. In the illustrated example, the second insulating layer 110 has a second opening 110b such that a wiring structure WS is disposed in a portion of the area encompassing the three component mounting areas EA1, EA2, EA3 (i.e., the area that does not completely overlap with the three component mounting areas). In this way, the area where the wiring structure WS is disposed can be limited to a predetermined range within the range encompassing the three component mounting areas. Therefore, in the wiring substrate 1, a planar orientation is not required ( Figure 1 The wiring structure, which is relatively large in size in the left-right direction of the paper, can be configured with a smaller wiring structure WS that corresponds only to the main parts in the component mounting area. As a result, the flatness of the component mounting surface is improved, and therefore, the reliability of the connection between external electronic components and the wiring substrate is considered to be improved. In addition, from the viewpoint of suppressing the influence of its thermal expansion on other structural elements constituting the wiring substrate 1 (especially the metal pillar MP and the first conductor pad P1), the wiring structure WS can be configured in the opening with its sides and top surface completely exposed.

[0040] In addition, as will be referred to later Figure 2A and Figure 2B Due to the difficulty of detailed description, the wiring structure WS can include wiring capable of electrically connecting electronic components that can be connected to the wiring structure WS to each other. Specifically, of the 12 connecting pads OP of the illustrated wiring structure WS, the nine connecting pads OP in the planar direction of the wiring structure WS are located in the first component mounting area EA1, while the three connecting pads OP at each end are located in the second and third component mounting areas EA2 and EA3, respectively. These connecting pads OP located in the first component mounting area EA1 and the connecting pads OP located in the adjacent second and third component mounting areas EA2 and EA3 can be electrically connected via wiring within the wiring structure WS. In the use of the wiring substrate 1, multiple electronic components mounted are electrically connected to each other via the wiring structure WS, thereby increasing the degree of freedom in the circuit design of the multiple electronic components that can be mounted in the use of the wiring substrate 1.

[0041] Furthermore, the surface of the wiring substrate 1 opposite to the component mounting surface of the core substrate 100, consisting of the third insulating layer 210 and the conductor pad 22p exposed from the opening 210a, can be a connection surface for connecting to external elements when the wiring substrate 1 itself is mounted on an external wiring substrate (e.g., the motherboard of any electrical device). The conductor pad 22p can be connected to any substrate, electrical component, or mechanical component.

[0042] Electronic components E1, E2, and E3 that can be mounted on the wiring substrate 1 include, for example, active components such as semiconductor integrated circuit devices and transistors. In the illustrated example, electronic component E1 is, for example, an integrated circuit such as a logic chip with assembled logic circuits, or a processing device such as an MPU (Micro Processor Unit), while electronic components E2 and E3 can be, for example, memory elements such as HBM (High Bandwidth Memory). That is, the wiring substrate 1 can have the form of an MCM (Multi Chip Module) in its use.

[0043] Next, refer to Figure 2A and Figure 2B The structure of the wiring construct WS is described in detail. Figure 2A yes Figure 1 An enlarged view of region II enclosed by a dashed line. The wiring structure WS disposed within the opening 110b of the second insulating layer 110 has alternating layers of resin insulating layer 31 and wiring layers 32, 320. The wiring layers 32, 320, which are opposite each other and separated by a layer of resin insulating layer 31, are connected to each other by a via conductor 33.

[0044] The wiring structure WS has a first surface A and a second surface B opposite to the first surface A. In the illustrated example, the second surface B is formed by the surface (lower surface) of the resin insulating layer 31 and the surface (lower surface) of the wiring layer 32. The wiring layer 32 constituting the second surface B includes a connecting pad IP, which is connected to a second conductor pad P2 via a bump BP, which is a conductive bonding material (e.g., solder). The second conductor pad P2 has a protective film on its surface, for example, composed of three layers: Ni, Pd, and Au. The bump BP can be bonded to, for example, the Au layer constituting the outermost layer of the protective film. The first surface A is formed by the surface (upper surface) of the wiring layer 32 and the surface (upper surface) of the resin insulating layer 31 exposed from the pattern of the wiring layer 32. The wiring layer 32 constituting the first surface A has a connecting pad OP. A plating layer composed of two layers, for example, nickel and tin, can be formed on the surface of the connecting pad OP. Furthermore, the connecting pad OP on the first side A of the wiring structure WS is also referred to as the first side connecting pad OP, and the connecting pad IP on the second side B is also referred to as the second side connecting pad IP.

[0045] The resin insulating layer 31 can be formed of an insulating resin such as an epoxy resin or a phenol resin. The resin insulating layer 31 can include any one of a fluororesin, a liquid crystal polymer (LCP), a fluorinated ethylene resin (PTFE), a polyester resin (PE), and a modified polyimide resin (MPI). As the conductor constituting the wiring layers 32, 320 and the via conductors 33, copper, nickel, or the like can be exemplified, and copper is preferably used. In the illustrated example, the wiring layers 32, 320 and the via conductors 33 have a two-layer structure including a metal film layer (preferably, a non-electrolytic copper plating film layer) np and a plated film layer (preferably, an electrolytic copper plating film) ep.

[0046] Reference Signs List Figure 1 As described above, the nine central first-surface connecting pads OP among the twelve first-surface connecting pads OP are located within the component mounting region EA1, the three first-surface connecting pads OP on the left side of the paper are located in the component mounting region EA2, and the three first-surface connecting pads OP on the right side of the paper are located in the component mounting region EA3. That is, in use of the wiring board 1, the nine central first-surface connecting pads OP can be connected to the external electronic component E1, the three first-surface connecting pads OP on the left side of the paper can be connected to the external electronic component E2, and the three first-surface connecting pads OP on the right side of the paper can be connected to the external electronic component E3.

[0047] The first-surface connecting pads OP disposed in the first component mounting region EA1 are electrically connected to the first-surface connecting pads OP disposed in the second and third component mounting regions EA2, EA3 via the wiring BW. According to this structure, the wiring board 1 in use can electrically connect a plurality of external electronic components to each other via the wiring structure WS. Specifically, as illustrated, in the case where three electronic components E1, E2, E3 are mounted, the adjacent electronic components are electrically connected to each other via the wiring structure WS, respectively, and E2 and E1 and E1 and E3 can be electrically connected.

[0048] In addition, in the wiring structure WS in the wiring board 1, the second-surface connecting pads IP and the first-surface connecting pads OP can be electrically connected via the wiring layers 32, 320 and the via conductors 33 constituting the wiring structure WS. That is, the wiring structure WS can function to electrically connect the first conductor layer 112 (the second conductor pads P2) and the electronic components, and also can function to electrically connect at least three or more external electronic components to each other. Thus, the degree of freedom of arrangement of the electronic components in use of the wiring board 1 can be improved.

[0049] Further, the wiring structure WS can be provided between the second surface B and the upper surface of the first insulating layer 111 with the bottom-filling insulating film UF interposed therebetween in the configuration into the opening 110b. The bottom-filling insulating film UF can be a thermosetting NCF (Non Conductive Film) capable of containing an epoxy resin, a polyimide resin. By interposing the bottom-filling insulating film UF between the wiring structure WS and the first insulating layer 111, the connection reliability of the wiring structure WS to the conductor pad P2 with respect to physical stress (thermal stress, physical external force) can be improved.

[0050] In Figure 2A In the example shown, the wiring structure WS can have a wiring layer having a buried wiring form. Specifically, the wiring layer 320 has a buried wiring form in which a conductor fills a groove formed in the lower resin insulating layer 31. The wiring layer 320 having the buried wiring form can have fine wiring FW having a small pattern width and a small distance between patterns. The fine wiring FW can have the smallest pattern width and the smallest distance between patterns among the wirings constituting the wiring substrate 1.

[0051] Further, in the example shown, three of the plurality of (five) wiring layers 320 that the wiring structure WS has have the buried wiring form, one of which has the fine wiring FW, but each of the plurality of wiring layers 320 can have the fine wiring FW. The number of wiring layers having the buried wiring form that the wiring structure WS has is not limited.

[0052] The fine wiring FW that the wiring structure WS has has a pattern width and a distance between patterns that are smaller than the pattern width and the distance between patterns of the wirings that the conductor layers 102, 12, 112, 22 in the above-described wiring substrate 1 have. Specifically, for example, the minimum value of the line width of the fine wiring FW is 3.0 μm or less, and the minimum value of the distance between lines is 3.0 μm or less. Since the wiring structure WS includes the fine wiring FW, a wiring having a more appropriate characteristic impedance corresponding to an electrical signal that can be transmitted by the wiring in the wiring structure WS can be provided. Further, it can be considered that the density of the wirings in the wiring structure WS increases, and the degree of freedom of the wiring design can increase. Further, from the same viewpoint, the aspect ratio of the wiring layer 320 having the fine wiring FW is preferably 1.8 or more and 6.0 or less, and further, the aspect ratio of all the wiring layers 32, 320 that the wiring structure WS has is preferably formed to be 1.8 or more and 6.0 or less.

[0053] The fine wiring FW in the wiring structure WS can be wiring for high-frequency signal transmission. Therefore, the resin insulating layer 31 in contact with the fine wiring FW preferably has excellent high-frequency characteristics. When the insulating layer in contact with the wiring has a relatively high dielectric constant and dielectric loss tangent, the dielectric loss (transmission loss) of the high-frequency signal transmitted by the wiring is relatively large. Therefore, the resin insulating layer 31 in contact with the fine wiring FW is preferably made of a material with a small dielectric constant and dielectric loss tangent, preferably with a relative dielectric constant of 3.3 or less and a dielectric loss tangent of 0.03 or less at a frequency of 1 GHz. Furthermore, since all the resin insulating layers 31 constituting the wiring structure WS have excellent high-frequency characteristics, the wiring structure WS can have excellent signal transmission quality. Therefore, the relative dielectric constant of the resin insulating layer 31 constituting the wiring structure WS is preferably 3.3 or less, and the dielectric loss tangent is preferably 0.03 or less.

[0054] The wiring structure included in the wiring substrate of the embodiment is not limited to a wiring layer having embedded wiring. Figure 2B This illustrates an example of a wiring structure that does not have a wiring layer with embedded wiring. Figure 2B In the wiring structure WS1 shown, the lower four wiring layers 32 of the wiring layers 32 constituting the wiring structure WS1 protrude into the resin insulating layer 31 directly above, while the uppermost wiring layer 32 protrudes outward from the wiring structure WS1. In the illustrated example, one of the multiple wiring layers 32 has a micro-wire FW1. The micro-wire FW1 can have the same size as the micro-wire FW described above. In the illustrated wiring structure WS1 without embedded wiring, the number of wiring layers 32 with micro-wire FW1 is not limited.

[0055] Next, refer to Figures 3A-3F To manufacture Figure 1 Taking the example of wiring substrate 1 shown below, the manufacturing method of the wiring substrate will be explained. First, as shown... Figure 3A As shown, a core substrate 100 is prepared. In the preparation of the core substrate 100, for example, a double-sided copper-clad laminate containing a core insulating layer 101 is prepared. Then, conductor layers 102 containing a predetermined conductor pattern are formed on both sides of the insulating layer 101 by a subtractive process or the like, and through-hole conductors 103 are formed in the insulating layer 101, thereby preparing the core substrate 100.

[0056] Next, as Figure 3BAs shown, an insulating layer 11 is formed on one side F1 of the core substrate 100, and a conductor layer 12 is stacked on the insulating layer 11. An insulating layer 21 is formed on the other side F2 of the core substrate 100, and a conductor layer 22 is stacked on the insulating layer 21. For example, each insulating layer 11 and 21 is formed by hot-pressing a film-like insulating resin onto the core substrate 100. The conductor layers 12 and 22, along with via conductors 13 and 23 that fill the insulating layers 11 and 21 with openings 13a and 23a, for example, that can be formed by laser, are formed using any conductor pattern forming method such as a semi-additive method.

[0057] Next, as Figure 3C As shown, on one side F1 of the core substrate 100, insulating layers and conductor layers are repeatedly stacked to form a first stacked layer 10. On the other side F2 of the core substrate 100, insulating layers and conductor layers are repeatedly stacked to form a second stacked layer 20. The outermost conductor layer (first conductor layer 112) in the first stacked layer 10 is formed as a pattern including multiple conductor pads (first conductor pad P1 and second conductor pad P2). The outermost conductor layer 22 in the second stacked layer 20 is formed as a pattern including conductor pad 22p. On the surfaces of the first conductor pad P1, the second conductor pad P2, and the conductor pad 22p, a protective layer including a nickel layer, a palladium layer, and a gold layer can be formed, for example, by electroless plating using a plating method.

[0058] Next, as Figure 3D As shown, a second insulating layer 110 is formed on the first laminate 10, and a third insulating layer 210 is formed on the second laminate 20. The second insulating layer 110 has an opening 110a exposing the first conductor pad P1 and an opening 110b exposing the second conductor pad P2. The third insulating layer 210 has an opening 210a exposing the conductor pad 22p. For example, a photosensitive epoxy resin film is formed by spraying, curtain coating, or film bonding, thereby forming the second and third insulating layers 110 and 210. The openings 110a, 110b, and 210a can be formed by exposure and development.

[0059] Next, as Figure 3E As shown, the opening 110a is filled with a conductor to form a metal pillar MP. The metal pillar MP is formed in the same way as the via conductors 13 and 23 and conductor layers 12 and 22 described above, for example, by a semi-additive process. It should be noted that the metal pillar MP can also be formed simply by electroless plating onto the first conductor pad P1. Furthermore, during the metal pillar MP formation process, the surface formed by the third insulating layer 210 and the upper surface of the conductor pad 22p can be appropriately protected by providing a protective plate such as PET.

[0060] Next, as Figure 3FAs shown, a wiring structure WS is provided within the opening 110b. The wiring structure WS is provided such that its second surface B faces the first stacked portion 10, and a bottom-filling insulating film UF is sandwiched between the first insulating layer 111 and the second surface B. The second-side connecting pad IP included in the second surface B is electrically and mechanically connected to the second conductor pad P2 constituting the bottom of the opening 110b via a connecting member (not shown) that is conductive, for example, as solder. The wiring structure WS can be configured such that the distance from the upper surface of the first-side connecting pad OP included in its first surface A to the upper surface of the first insulating layer 111 is approximately equal to the distance from the upper surface of the metal pillar MP to the upper surface of the first insulating layer 111.

[0061] Next, refer to Figures 4A-4I right Figure 2A The manufacturing of the wiring structure WS and its arrangement within the opening 110b will be described. Regarding the manufacturing of the wiring structure WS, firstly, as shown... Figure 4A As shown, a first support substrate GS1 with good surface flatness, such as a glass substrate, is prepared. A metal film layer np is formed on one surface of the first support substrate GS1 via an adhesive layer AL1, for example, containing an azobenzene-based polymer adhesive that can be applied and removed by light irradiation. The metal film layer np is, for example, a metal film (preferably a copper film) formed by electroless plating or sputtering. The metal film layer np may also be composed of a relatively thin metal foil.

[0062] Furthermore, in the description of the manufacturing of the wiring structure, the side closer to the first support substrate GS1 is referred to as "lower" or "lower side", and the side farther away from the first support substrate GS1 is referred to as "upper" or "upper side". Therefore, the surface of each element constituting the wiring structure facing the first support substrate GS1 is also referred to as the "lower surface", and the surface facing the side opposite to the first support substrate GS1 is also referred to as the "upper surface".

[0063] Next, as Figure 4B As shown, on the support substrate GS1, a wiring layer 32 having five connection pads IP comprising a metal film layer np and an electroplated film layer ep is formed through an adhesive layer AL1. Figure 4B In the diagram, regarding wiring layer 32, five of the multiple connection pads IP formed on a first support substrate GS1 are illustrated. In the method for manufacturing the wiring structure WS, multiple wiring structures WS are formed on a single first support substrate GS1, but... Figures 4A-4I The description shows and explains one of the multiple wiring structures WS.

[0064] In the formation of wiring layer 32, for example, a resist is formed on the metal film layer np, and openings corresponding to the formation areas of the pattern of the connection pad IP are formed on the resist, for example, by photolithography. Next, an electroplated film layer ep is formed in the openings by electroplating using the metal film layer np as a seed layer. After the electroplated film layer ep is formed, the resist is removed, and the metal film layer np exposed by the removal of the resist is etched, thereby forming... Figure 4B The state shown.

[0065] Next, as Figure 4C As shown, a resin insulating layer 31 is stacked over a wiring layer 32 having a second-side connecting pad IP. For example, epoxy resin, phenolic resin, or other insulating resins can be used as the resin insulating layer 31. Fluoropolymers, liquid crystal polymers (LCP), fluorinated vinyl resins (PTFE), polyester resins (PE), and modified polyimide resins (MPI) can also be used. The insulating resin used in the resin insulating layer 31 preferably has a small relative permittivity and dielectric loss tangent; materials with a relative permittivity of 3.3 or less and a dielectric loss tangent of 0.03 or less at a frequency of 1 GHz are preferred.

[0066] Grooves T1 and T2 are formed in the stacked resin insulating layer 31. Groove T1 is formed at the location where a via conductor is to be formed, penetrating the resin insulating layer 31 and exposing the wiring layer 32 directly below the resin insulating layer 31. Groove T2 has a shaped form for embedding wiring and is formed at the junction with the wiring layer 320 (see reference). Figure 2A The pattern corresponds to the position. In the formation of trenches T1 and T2, laser processing utilizing an excimer laser is used, for example. Next, a metal film layer np is formed to cover the entire upper surface of the wiring layer 32 exposed from the resin insulating layer 31 and trench T1. This metal film layer np is then used as a seed layer for electrolytic plating, thereby forming an electroplated film layer ep. Figure 4C The state shown.

[0067] Next, as Figure 4D As shown, a portion of the electroplated film layer ep and the metal film layer np are removed by grinding. A further layer of resin insulating layer 31 is then deposited on the exposed upper surfaces of the resin insulating layer 31 and the wiring layer 320, repeating the formation of the wiring layer 320. The grinding of the electroplated film layer ep and the metal film layer np can be performed, for example, by chemical mechanical polishing (CMP).

[0068] Next, as Figure 4EAs shown, a resin insulating layer 31, serving as the uppermost resin insulating layer of the wiring structure WS, and a wiring layer 32, serving as the uppermost wiring layer, are formed on the upper side of the conductor layer 320. An opening 33a is formed into the resin insulating layer 31, and the wiring layer 32 is formed together with the via conductor 33, for example, by a semi-additive method. The uppermost wiring layer 32 is formed as a pattern containing a plurality of connection pads OP. On the upper surface of the connection pads OP, for example, a plating layer P containing a nickel layer N and a tin layer S may be formed. The formation of the laminated structure that the wiring structure WS should have is thus completed.

[0069] Next, as Figure 4F As shown, after the formation of the laminated structure that the wiring structure WS should have is completed, a second support substrate GS2 is mounted on the upper surface of the plating P of the uppermost wiring layer 32. The second support substrate GS2 is made of glass, for example, with one side facing the wiring layer 32, and is mounted with an adhesive layer AL2, for example, made of the same material as the adhesive layer AL1, spaced apart from the upper surface of the wiring layer 32.

[0070] Then, as Figure 4G As shown, the first support substrate GS1 is removed. The lower surface of the connecting pad IP and the lower surface of the resin insulating layer 31 are exposed. During the removal of the first support substrate GS1, after softening the adhesive layer AL1 by irradiating it, for example with a laser, the first support substrate GS1 is peeled off from the connecting pad IP and the resin insulating layer 31. It should be noted that any adhesive layer AL1 remaining on the second surface B can be removed by cleaning.

[0071] Next, as Figure 4H As shown, a bonding material, such as a solder bump (BP), is formed on the exposed surface (lower surface) of the connector pad IP. The bump BP can be formed on the lower surface of the connector pad IP, for example, through a diffusion-preventing metal film (not shown) formed on the surface of the connector pad IP. After forming the bump BP, an underfill insulating film (UF) is provided to cover both the bump BP and the lower surface of the resin insulating layer 31. The underfill insulating film (UF) is, for example, adhered to the bump BP and the lower surface of the resin insulating layer 31 under vacuum.

[0072] Next, as Figure 4I As shown, the wiring structure WS and the second support substrate GS2 are monolithically formed together. For example, monolithic formation is achieved by cutting the second support substrate GS2, the wiring structure WS, and the bottom filling insulating film UF along a predetermined cutting line using a cutting saw. The second support substrate GS2 is disposed on the first surface A, forming the wiring structure WS covered by the bottom filling insulating film UF.

[0073] like Figure 3FAs shown, the singulated wiring structure WS is disposed in the opening 110b. In the disposition of the wiring structure WS in the opening 110b, the alignment is performed in a manner that the bump BP corresponds to the position of the second conductor pad P2 in a state where the second support substrate GS2 is disposed. In a state where the underfill insulating film UF is heated to a temperature (e.g., around 60 to 150°C) having fluidity but not significantly starting to cure, the bump BP is brought into contact with the second conductor pad P2 by pressing downward. Thereafter, the bump BP is joined to the second conductor pad P2 by heating to a melting temperature of the bump BP. After the joining is completed, the second support substrate GS2 is removed by the same method as the peeling of the first support substrate GS1 described above. Figure 4G The second support substrate GS2 is removed by the same method as the peeling of the first support substrate GS1 described above. The disposition of the wiring structure WS in the opening 110b is completed.

[0074] Further, in the case of the wiring structure WS1 shown in FIG. 1, instead of the wiring layer 320 having the form of the buried wiring described above with reference to FIG. 3, the wiring layer 32 is formed by the same method as the formation of the resin insulating layer 31 and the conductor layer 32 described above. Figure 2B Figure 4C 、 Figure 4D Further, in the case of the wiring structure WS1 shown in FIG. 1, instead of the wiring layer 320 having the form of the buried wiring described above with reference to FIG. 3, the wiring layer 32 is formed by the same method as the formation of the resin insulating layer 31 and the conductor layer 32 described above.

[0075] The wiring substrate of the embodiment is not limited to having the configuration exemplified in each drawing and the configuration, shape, and material exemplified in the present specification. For example, the wiring structure can have any number of resin insulating layers and wiring layers. The first build-up portion and the second build-up portion can have any number of layers of insulating layers and conductor layers. The number of layers of insulating layers and conductor layers possessed by the first build-up portion formed on both faces of the core substrate can be different from the number of layers of insulating layers and conductor layers possessed by the second build-up portion. In addition, the wiring substrate is not limited to having the form of the core substrate, and the wiring substrate of the embodiment can have a structure having at least an upper side than the first insulating layer. In the description of the embodiment, an example is described in which the connection pads of one wiring structure are disposed across three component mounting regions, but a structure can be realized in which the connection pads of one wiring structure are disposed across four or more component mounting regions, and the electronic components that can be mounted on each component mounting region can be electrically connected to each other.​

Claims

1. A wiring substrate, comprising: First insulating layer; A first conductor layer is formed on the first insulating layer and has a plurality of first conductor pads and a plurality of second conductor pads; A second insulating layer is formed on the first conductor layer and has a first opening that exposes the first conductor pad and a second opening that exposes the plurality of second conductor pads; A metal pillar is formed on the first conductor pad and fills the first opening; as well as A wiring structure has a first surface and a second surface. The first surface has a plurality of first-side connecting pads, and the second surface has a second-side connecting pad on the opposite side of the first surface. The wiring structure connects the second-side connecting pads to the second conductor pads and is disposed within the second opening. in, The upper surfaces of the plurality of first-side connecting gaskets and the upper surface of the metal pillar constitute a component mounting surface. This component mounting surface has a first component mounting area, a second component mounting area adjacent to the first component mounting area, and a third component mounting area adjacent to the first component mounting area. The plurality of first-side connecting gaskets are respectively disposed in the first component mounting area, the second component mounting area, and the third component mounting area. The first-side connecting pads of the plurality of first-side connecting pads disposed in the first component mounting area and the second component mounting area are electrically connected to each other, and the first-side connecting pads disposed in the first component mounting area and the third component mounting area are electrically connected to each other.

2. The wiring substrate according to claim 1, wherein, The wiring structure has a wiring layer that includes wiring with the smallest line width and line spacing in the wiring substrate.

3. The wiring substrate according to claim 1, wherein, The second insulating layer has a second opening such that one of the wiring structures is disposed in the first component mounting region, the second component mounting region, and the third component mounting region.

4. The wiring substrate according to claim 1, wherein, The distance from the upper surface of the first insulating layer to the upper surface of the metal pillar is approximately equal to the distance from the upper surface of the first insulating layer to the upper surface of the first side connecting gasket.

5. The wiring substrate according to claim 1, wherein, The second-side connecting pad and the first-side connecting pad are electrically connected to each other via conductors provided by the wiring structure.

6. The wiring substrate according to claim 1, wherein, The wiring structure has a wiring layer consisting of conductors that fill grooves formed in a resin insulating layer.

7. The wiring substrate according to claim 1, wherein, The wiring structure is configured within the second opening in such a way that the entire area of ​​the side and top surfaces of the wiring structure is exposed.

8. The wiring substrate according to claim 1, wherein, The wiring structure contains wiring with a minimum line width of 3.0 μm and a minimum inter-line distance of 3.0 μm. The aspect ratio of the wiring contained in the wiring structure is 1.8 or higher and 6.0 or lower.

9. The wiring substrate according to claim 1, wherein, The wiring structure includes a resin insulating layer. The dielectric loss tangent of the resin insulating layer at a frequency of 1 GHz is less than 0.03 and the relative permittivity is less than 3.3.

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