Chiplet Package Chip with Clock Signal Distribution

Abstract

The present invention discloses a chiplet package chip with clock signal distribution, which relates to integrated circuit packaging technology and includes: a packaging substrate; the packaging substrate is located on a PCB substrate; the PCB substrate includes a first clock source; a plurality of chiplets are packaged on the packaging substrate; two adjacent chiplets are connected through an inter-chip interconnection interface; each chiplet includes an input clock buffer, an output clock buffer, and at least one inter-chip interconnection interface; the input clock buffer outputs a clock signal to each inter-chip interconnection interface and the output clock buffer within the chiplet where it is located; the plurality of chiplets includes a first chiplet and at least one second chiplet; the first clock source is connected to the input clock buffer of the first chiplet; the input clock buffer of the second chiplet is connected to the output clock buffer of an adjacent chiplet, and the adjacent chiplet is the first chiplet or the second chiplet; the output clock buffers of the first chiplet and the second chiplet are connected to the input clock buffers of the adjacent second chiplets.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit packaging technology, and in particular, to a chiplet package chip with clock signal distribution. Background Art

[0002] With the continuous development of chip technology, the complexity of chip structures has increased accordingly. Currently, the Chiplet technology is used to package multiple chiplets. The operation of chiplets requires the support of a reference clock. Multiple chiplets within the package are interconnected through high-speed inter-chip interconnect interfaces, and a low-jitter, same-source reference clock is required for data transmission through the high-speed inter-chip interconnect interfaces.

[0003] Currently, the reference clock is routed on a Printed Circuit Board (PCB) substrate or a package substrate and connected to each chiplet respectively. However, problems such as wire routing resource congestion and impedance interference exist during the wire routing process. How to improve the quality of clock signals while reducing wire routing has become an urgent problem to be solved. Summary of the Invention

[0004] The present invention provides a chiplet package chip with clock signal distribution to improve the quality of clock signals while reducing wire routing, which can not only reduce the wire routing cost but also improve the quality of clock signals.

[0005] In a first aspect, embodiments of the present invention provide a chiplet package chip with clock signal distribution, which is characterized by including a package substrate;

[0006] The package substrate is located on the PCB substrate; the PCB substrate includes a first clock source;

[0007] A plurality of chiplets are packaged on the package substrate; two adjacent chiplets are connected through an inter-chip interconnect interface;

[0008] Each chiplet includes an input clock buffer, an output clock buffer, and at least one inter-chip interconnect interface; the input clock buffer outputs a clock signal to each inter-chip interconnect interface and the output clock buffer within the chiplet where it is located;

[0009] The plurality of chiplets includes a first chiplet and at least one second chiplet;

[0010] The first clock source is connected to the input clock buffer of the first chiplet; the input clock buffer of the second chiplet is connected to the output clock buffer of an adjacent chiplet, and the adjacent chiplet is the first chiplet or a second chiplet;

[0011] The output clock buffers of the first chiplet and the second chiplet are connected to the input clock buffers of adjacent second chiplets.

[0012] Based on the above solution, the first die includes an output clock buffer, the second die includes an output clock buffer, and there are multiple second dies;

[0013] The clock signal starts from the first die and is unidirectionally serially transmitted on multiple second dies in a preset order.

[0014] Based on the above solution, the first die includes multiple output clock buffers, the second die includes one or more output clock buffers, and there are multiple second dies;

[0015] The clock signal starts from the first die and is multi-path parallel transmitted on multiple second dies in a preset order.

[0016] Based on the above solution, the output pin of the output clock buffer of the second die at the transmission end is left floating or removed.

[0017] Based on the above solution, the PCB substrate further includes a second clock source; the multiple dies include a third die and at least one fourth die;

[0018] The second clock source is connected to the input clock buffer of the third die; the input clock buffer of the fourth die is connected to the output clock buffer of an adjacent die, and the adjacent die is the third die or the fourth die;

[0019] The output clock buffers of the third die and the fourth die are connected to the input clock buffers of adjacent fourth dies;

[0020] The third die and / or the fourth die are interconnected with the first die and / or the second die through an inter-die interconnect interface.

[0021] Based on the above solution, the inter-die interconnect interface unifies the clock signals of the first clock source and the second clock source through an elastic cache method.

[0022] Based on the above solution, the die further includes at least one relay buffer;

[0023] The input clock buffer outputs the clock signal to the inter-die interconnect interface within the die through the at least one relay clock buffer respectively.

[0024] Based on the above solution, multiple dies are encapsulated in an interposer, and the interposer is encapsulated in a package substrate; or, the multiple dies are directly encapsulated in the package substrate.

[0025] Based on the above solution, the input of the input clock buffer is a differential clock signal, the output of the input clock buffer is a single-ended or differential signal, the input of the output clock buffer is a single-ended or differential signal, and the output of the output clock buffer is a differential signal; or, the input and output of the input clock buffer are single-ended clock signals, and the output and input of the output clock buffer are single-ended clock signals.

[0026] Based on the above solution, the multiple dielets are isomorphic or heterogeneous.

[0027] For the dielet package chip with clock signal distribution provided by the present invention, the clock signal of the first clock source is input into the first dielet through the input clock buffer of the first dielet, and reaches the output clock buffer of the first dielet through the conduction of the clock buffer inside the first dielet. It is output from the output clock buffer of the first dielet to the input clock buffer of the adjacent second dielet, realizing the transfer of the clock signal inside the dielet. There is no need to set clock signals for each dielet on the package substrate or PCB substrate. The clock signal of the first clock source only needs to be input into the first dielet to realize the transfer of the first clock source between the first dielet and at least one second dielet. Since the clock signal is transferred inside the dielet, the clock signal will not be subject to impedance interference, and there is no need to set multiple clock signal wirings on the package substrate or PCB substrate, thus solving the problem of squeezing of wiring resources and achieving the effect of improving the clock signal quality while reducing wire winding. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a dielet package chip with clock signal distribution provided by an embodiment of the present invention Figure 1 ;

[0029] Figure 2 is a schematic structural diagram of a dielet package chip with clock signal distribution provided by an embodiment of the present invention Figure 2 ;

[0030] Figure 3 is a schematic structural diagram of a dielet package chip with clock signal distribution provided by an embodiment of the present invention Figure 3 ;

[0031] Figure 4 is a schematic structural diagram of a dielet package chip with clock signal distribution provided by an embodiment of the present invention Figure 4 ;

[0032] Figure 5 is a schematic structural diagram of a dielet package chip with clock signal distribution provided by an embodiment of the present invention Figure 5 ;

[0033] Figure 6Schematic structure of a chiplet package chip with clock signal distribution provided by an embodiment of the present invention Figure 6 ;

[0034] Figure 7 Schematic structure of a chiplet package chip with clock signal distribution provided by an embodiment of the present invention Figure 7 ;

[0035] Figure 8 Schematic structure of a chiplet package chip with clock signal distribution provided by an embodiment of the present invention Figure 8 。

[0036] 1 - Package substrate, 2 - PCB substrate, 3 - Inter - die interconnection interface, 4 - First clock source, 5 - First chiplet, 6 - Second chiplet, 7 - Input clock buffer, 8 - Output clock buffer, 9 - Second clock source, 10 - Third chiplet, 11 - Fourth chiplet. Detailed implementation manners

[0037] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all the structures.

[0038] Figure 1 Schematic structure of a chiplet package chip with clock signal distribution provided by an embodiment of the present invention Figure 1 , including a package substrate 1;

[0039] The package substrate 1 is located on the PCB substrate 2; the PCB substrate 2 includes a first clock source 4;

[0040] A plurality of chiplets are packaged on the package substrate 1; two adjacent chiplets are connected through an inter - die interconnection interface 3;

[0041] Each chiplet includes an input clock buffer 7, an output clock buffer 8 and at least one inter - die interconnection interface 3; the input clock buffer 7 outputs the clock signal to each inter - die interconnection interface 3 and the output clock buffer 8 within the chiplet where it is located;

[0042] The plurality of chiplets include a first chiplet 5 and at least one second chiplet 6;

[0043] The first clock source 4 is connected to the input clock buffer 7 of the first chiplet 5; the input clock buffer 7 of the second chiplet 6 is connected to the output clock buffer 8 of an adjacent chiplet, and the adjacent chiplet is the first chiplet 5 or the second chiplet 6;

[0044] The output clock buffers 8 of the first die 5 and the second die 6 are connected to the input clock buffers 7 of the adjacent second die 6.

[0045] As an example, as Figure 1 shown, a package structure including one first die 5 and three second dies 6. Among them, any die in the embodiments of the present invention includes an input clock buffer 7, an output clock buffer 8, and at least one inter-die interconnection interface 3, and any die can be the first die 5 or the second die 6. The output ends of the input clock buffers 7 are respectively connected to each inter-die interconnection interface 3 on the first die 5. The number of inter-die interconnection interfaces 3 can be determined according to design requirements and can be one or more.

[0046] The input end of the input clock buffer 7 of the first die 5 is connected to the first clock source 4. The output end of the input clock buffer 7 can be directly connected to the output clock buffer 8 of the first die 5, or a relay clock buffer can be added according to design requirements to maintain the clock signal strength. Correspondingly, the die further includes at least one relay buffer; the input clock buffer 7 outputs the clock signal to the inter-die interconnection interface 3 within the die through the at least one relay clock buffer.

[0047] Optionally, Figure 2 is a schematic structure of a die package chip with clock signal distribution provided by the embodiments of the present invention Figure 2 As Figure 2 shown, a die package chip with clock signal distribution can have one first die 5 and one second die 6. The first die 5 is provided with one inter-die interconnection interface 3, and the second die 6 is provided with one inter-die interconnection interface 3. The input end of the input clock buffer 7 of the first die 5 is connected to the first clock source 4. The output end of the input clock buffer 7 of the first die 5 is connected to the inter-die interconnection interface 3 of the first die 5, and the inter-die interconnection interface 3 of the first die 5 is connected to the inter-die interconnection interface 3 of the second die 6. The output end of the input clock buffer 7 of the first die 5 is connected to the input end of the output clock buffer 8 of the first die 5, and the output end of the output clock buffer 8 of the first die 5 is connected to the input end of the input clock buffer 7 of the second die 6. The output end of the input clock buffer 7 of the second die 6 is connected to the inter-die interconnection interface 3 of the second die 6. Optionally, other output pins at the output end of the input clock buffer 7 of the second die 6 are left floating or removed.

[0048] The chiplet package chip with clock signal distribution provided by the embodiments of the present invention, the clock signal of the first clock source is input into the first chiplet through the input clock buffer of the first chiplet, and reaches the output clock buffer of the first chiplet through the conduction of the clock buffer inside the first chiplet. It is output from the output clock buffer of the first chiplet to the input clock buffer of the adjacent second chiplet, realizing the transfer of the clock signal inside the chiplet, without setting clock signals for each chiplet on the package substrate or PCB substrate. The clock signal of the first clock source only needs to be input into the first chiplet to realize the transfer of the first clock source between the first chiplet and at least one second chiplet. Since the clock signal is transferred inside the chiplet, the clock signal will not be affected by impedance interference, and there is no need to set multiple clock signal wirings on the package substrate or PCB substrate, thus solving the problem of squeezing of wiring resources and achieving the effect of improving the clock signal quality while reducing the winding.

[0049] In one implementation, the first chiplet 5 includes an output clock buffer 8, the second chiplet 6 includes an output clock buffer 8, and there are multiple second chiplets 6; the clock signal starts from the first chiplet 5 and is unidirectionally serially transferred on multiple second chiplets 6 in a preset order.

[0050] The number of the second chiplets 6 can be determined according to the design requirements. Usually, multiple second chiplets 6 and the first chiplet 5 form an N*N or M*N matrix. For example, as Figure 3 shown, three second chiplets 6 and the first chiplet 5 form a 2*2 chiplet matrix. Another example, as Figure 4 shown, eight second chiplets 6 and the first chiplet 5 form a 3*3 chiplet matrix. It can also be composed of fifteen second chiplets 6 and the first chiplet 5 to form a 4*4 chiplet matrix, and so on. The clock signal of the first clock source 4 is accessed by one first chiplet 5, and then the clock signal is transferred from the first chiplet 5 to the adjacent second chiplet 6, and then from this second chiplet 6 to the adjacent other second chiplets 6.

[0051] In Figure 3Among them, the first die 5 is die a, and the second die 6 includes die b, die c, and die d. Die a, die b, die c, and die d are arranged in counterclockwise order in sequence to form a 2×2 die matrix. Adjacent dies are connected through the inter-die interconnect interface 3. Each die includes an input clock buffer 7 and an output clock buffer 8. The output terminals of the input clock buffer 7 of each die are respectively connected to the inter-die interconnect interface 3 and the output clock buffer 8 of this die. The input terminal of the input clock buffer 7 of die a is connected to the first clock source 4. The output terminal of the output clock buffer 8 of die a is connected to the input terminal of the input clock buffer 7 of die b. The output terminal of the output clock buffer 8 of die b is connected to the input terminal of the input clock buffer 7 of die c. The output terminal of the output clock buffer 8 of die c is connected to the input terminal of the input clock buffer 7 of die d. Through the conduction of the clock buffer, the clock signal sequentially passes through die a, die b, die c, and die d, realizing counterclockwise serial transmission.

[0052] It should be noted that the transmission direction of serial transmission is not limited to clockwise or counterclockwise. For example, when a multi-layer die matrix such as 3×3 or 4×4 is set, as long as all dies are connected in a serial manner, it is acceptable.

[0053] Such as Figure 4Among them, the first die 5 is die a, and the second die 6 includes die b, die c, die d, die e, die f, die g, die h, and die i. Adjacent dies are connected through the inter-die interconnect interface 3. Each die includes an input clock buffer 7 and an output clock buffer 8. The output ends of the input clock buffers 7 of each die are respectively connected to the inter-die interconnect interface 3 and the output clock buffer 8 of this die. The input end of the input clock buffer 7 of die a is connected to the first clock source 4. The output end of the output clock buffer 8 of die a is connected to the input end of the input clock buffer 7 of die b. The output end of the output clock buffer 8 of die b is connected to the input end of the input clock buffer 7 of die c. The output end of the output clock buffer 8 of die c is connected to the input end of the input clock buffer 7 of die d. The output end of the output clock buffer 8 of die d is connected to the input end of the input clock buffer 7 of die e. The output end of the output clock buffer 8 of die e is connected to the input end of the input clock buffer 7 of die f. The output end of the output clock buffer 8 of die f is connected to the input end of the input clock buffer 7 of die g. The output end of the output clock buffer 8 of die g is connected to the input end of the input clock buffer 7 of die h. The output end of the output clock buffer 8 of die h is connected to the input end of the input clock buffer 7 of die i. Through the conduction of the clock buffer, the clock signal sequentially passes through die a, die b, die c, die d, die e, die f, die g, die h, and die i, realizing serial transfer in a preset order.

[0054] In the above embodiment, one input clock buffer 7 and one output clock buffer 8 are provided on each die, controlling the number of clock buffers to the lowest, thereby reducing costs.

[0055] In another implementation, the first die 5 includes multiple output clock buffers 8, the second die 6 includes one or more output clock buffers 8, and there are multiple second dies 6; the clock signal starts from the first die 5 and is multiplexed and transferred in parallel on multiple second dies 6 in a preset order.

[0056] As the number of packaged dies increases, the time for unidirectional serial transfer of the clock signal increases accordingly. In addition to unidirectional serial transfer between dies, the embodiments of the present invention can also perform multiplexed parallel transfer between multiple second dies 6 to improve the transfer efficiency of the clock signal.

[0057] The number of second dies 6 can be determined according to design requirements. Usually, multiple second dies 6 and the first die 5 form an N*N or M*N matrix. For example, as Figure 5 shown, three second dies 6 and the first die 5 form a 2*2 die matrix. Another example, as Figure 6As shown, eight second die chips 6 and a first die chip 5 form a 3×3 die chip matrix. Fifteen second die chips 6 and a first die chip 5 can also form a 4×4 die chip matrix, and so on. A first die chip 5 receives the clock signal from a first clock source 4, then the first die chip 5 transfers the clock signal to multiple adjacent second die chips 6, and then the second die chips 6 transfer it to other adjacent second die chips 6.

[0058] In Figure 5 , the first die chip 5 is die chip a, and the second die chips 6 include die chips b, c, and d. Die chips a, b, c, and d are arranged counterclockwise in sequence to form a 2×2 die chip matrix. Adjacent die chips are connected through an inter-die interconnect interface 3. The output end of the input clock buffer 7 of each die chip is respectively connected to the inter-die interconnect interface 3 and the output clock buffer 8 of this die chip. The input end of the input clock buffer 7 of die chip a is connected to the first clock source 4. The output end of the output clock buffer 8A of die chip a is connected to the input end of the input clock buffer 7 of die chip b. The output end of the output clock buffer 8B of die chip a is connected to the input end of the input clock buffer 7 of die chip d. The output end of the output clock buffer 8 of die chip b is connected to the input end of the input clock buffer 7 of die chip c. Through the conduction of the clock buffer, the clock signal is sequentially transmitted through Route 1 composed of die chips a and d and Route 2 composed of die chips a, b, and c. Route 1 and Route 2 are two parallel transmission routes. Further, to save costs, output clock buffers are not provided at the ends of die chips c and d as the path ends.

[0059] As Figure 6 , the first die chip 5 is die chip a, and the second die chips 6 include die chips b, c, d, e, f, g, h, and i. Adjacent die chips are connected through an inter-die interconnect interface 3. The output end of the input clock buffer 7 of the die chip is respectively connected to the inter-die interconnect interface 3 and the output clock buffer 8 of this die chip.

[0060] The input end of the input clock buffer 7 of die chip f is connected to the first clock source 4. The output end of the output clock buffer 8G of die chip f is connected to the input end of the input clock buffer 7 of die chip a; the output end of the output clock buffer 8H of die chip f is connected to the input end of the input clock buffer 7 of die chip e; the output end of the output clock buffer 8I of die chip f is connected to the input end of the input clock buffer 7 of die chip g.

[0061] The output end of the output clock buffer 8 of the die a is connected to the input end of the input clock buffer 7 of the die b. The output end of the output clock buffer 8 of the die e is connected to the input end of the input clock buffer 7 of the die d. The output end of the output clock buffer 8 of the die g is connected to the input end of the input clock buffer 7 of the die h. The output end of the output clock buffer 8 of the die h is connected to the input end of the input clock buffer 7 of the die i.

[0062] Through the conduction of the clock buffer, the clock signal sequentially passes through Route 1 composed of die f, die a, die b, and die c, Route 2 composed of die f, die e, and die d, and Route 3 composed of die f, die g, die h, and die i to complete the transmission. Route 1, Route 2, and Route 3 are three parallel transmission routes, realizing parallel transmission in a preset order.

[0063] It should be noted that the parallel transmission can be multiple parallel routes starting from the dispersion point of the first die 5, or can be in a radial or other way for multi-channel transmission. Exemplarily, as Figure 7 shown, the first die 5 is die a, and the second die 6 includes die b, die c, die d, die e, die f, die g, die h, and die i. Adjacent dies are connected through the inter-die interconnection interface 3. The output end of the input clock buffer 7 of each die is respectively connected to the inter-die interconnection interface 3 and the output clock buffer 8 of this die. The input end of the input clock buffer 7 of die a is connected to the first clock source 4. The output end of the output clock buffer 8A of die a is connected to the input end of the input clock buffer 7 of die b; the output end of the output clock buffer 8B of die a is connected to the input end of the input clock buffer 7 of die f. The output end of the output clock buffer 8 of die f is connected to the input end of the input clock buffer 7 of die g. The output end of the output clock buffer 8C of die b is connected to the input end of the input clock buffer 7 of die c; the output end of the output clock buffer 8D of die b is connected to the input end of the input clock buffer 7 of die e. The output end of the output clock buffer 8E of die e is connected to the input end of the input clock buffer 7 of die d; the output end of the output clock buffer 8F of die e is connected to the input end of the input clock buffer 7 of die h. The output end of the output clock buffer 8 of die h is connected to the input end of the input clock buffer 7 of die i.

[0064] It can be seen that the clock signal transmission between dies can be in a serial, parallel, or a combination of serial and parallel manner. The transmission route of the clock signal can be configured according to design requirements such as design cost and clock conduction efficiency.

[0065] Based on the above embodiments, the output pin of the output clock buffer 8 of the second die 6 located at the transmission end is left floating or removed.

[0066] The output clock buffer 8 of the second die 6 at the end of the transmission path can be retained or cancelled. For the convenience of design, the dies adopt a homogeneous method. Then, there is an output clock buffer 8 in the second die 6 at the transmission end. This output clock buffer 8 is the end of the clock signal transmission, and the output pin of the output clock buffer 8 is floating. Thus, the reliability of the die pins is improved.

[0067] Based on the above embodiments, the PCB substrate 2 further includes a second clock source 9; the multiple dies include a third die 10 and at least one fourth die 11;

[0068] The second clock source 9 is connected to the input clock buffer 7 of the third die 10; the input clock buffer 7 of the fourth die 11 is connected to the output clock buffer 8 of the adjacent die, and the adjacent die is the third die 10 or the fourth die 11;

[0069] The output clock buffers 8 of the third die 10 and the fourth die 11 are connected to the input clock buffer 7 of the adjacent fourth die 11;

[0070] The third die 10 and / or the fourth die 11 are interconnected with the first die 5 and / or the second die 6 through the inter-die interconnect interface 3.

[0071] In some usage scenarios, the packaging scale of the dies is large. At this time, it may be necessary to connect a second clock source 9 to the die matrix. The second clock source 9 is a clock source other than the first clock source 4, and the second clock source 9 is provided by the PCB substrate. The number of the second clock sources 9 can be multiple.

[0072] The setting methods of the third die 10 and the fourth die 11 are the same as those of the first die 5 and the second die 6. The role of the third die 10 in the clock signal conduction is the same as that of the first die 5, and it is used to connect to the clock source. The third die 10 is connected to the second clock source 9. The role of the fourth die 11 in the clock signal conduction is the same as that of the second die 6, and it is used to conduct the clock signal inside the package.

[0073] The arrangement positions of the third die 10 and the fourth die 11 are designed according to design requirements. The third die 10 and the fourth die 11 form an N*N or M*N matrix.

[0074] The third die 10 and the fourth die 11 together with the first die 5 and the second die 6 form a die matrix. The third die 10 and the fourth die 11 are a group of dies, and the first die 5 and the second die 6 are another group of dies. Data interaction is carried out between the two groups of dies through the inter-die interconnect interface 3 provided on the adjacent dies.

[0075] Exemplarily, such as Figure 8As shown, the first group of die includes a first die 5 and a second die 6. Among them, die a serves as the first die 5, and die b, die c, die d, die e, die f, die g, and die h serve as the second die 6. The second group of die includes a third die 10 and a fourth die 11. Among them, die p serves as the third die 10, and die i, die j, die k, die l, die m, die n, and die o serve as the fourth die 11.

[0076] The first group of die and the second group of die together form a 4*4 die matrix.

[0077] The die at the intersection of the first die 5 group and the second die 6 group are die e, die i, die f, die j, die g, die k, die h, and die l respectively. Among them, die e is adjacent to die i, die f is adjacent to die j, die g is adjacent to die k, and die h is adjacent to die l. The clock signal conduction of the same-source clock can be realized both inside the first die 5 and inside the second die 6 group.

[0078] It should be noted that the die at the intersection of the first die 5 group and the second die 6 group can include not only the second die 6 and the fourth die 11, but also the first die 5 and the third die 10.

[0079] If the first clock source 4 and the second clock source 9 are the same-source clock, the clock signals transmitted within the first die 5 group and the second die 6 group are the same-source.

[0080] If the first clock source 4 and the second clock source 9 are not the same-source clock, the inter-die interconnect interface 3 adopted by the die at the intersection of the first die 5 group and the second die 6 group unifies the clock signals of the first clock source 4 and the second clock source 9 through an elastic cache method. By unifying the clock signals of the first clock source 4 and the second clock source 9 through the elastic cache method, the clocks within the first die 5 group and the second die group are the same-source.

[0081] Applying the inductive cache method on the inter-die interconnect interface 3 can unify non-same-source clock signals, and thus multiple non-same-source clocks can be incorporated in die packaging.

[0082] Based on the above embodiments, multiple die are packaged in an interposer, and the interposer is packaged on a package substrate 1; or, the multiple die are directly packaged on the package substrate 1.

[0083] Generally, a packaging substrate 1 is provided on a PCB substrate 2. The packaging substrate 1 is connected to the chiplets through pins, and multiple chiplets are directly packaged on the packaging substrate 1 to realize the packaging structure of the PCB substrate 2, the packaging substrate 1, and the chiplets. In another implementation, an interposer can also be provided on the packaging substrate 1. The interposer is connected to the chiplets through pins to realize the packaging structure of the PCB substrate 2, the packaging substrate 1, the interposer, and the chiplets.

[0084] Optionally, the input of the input clock buffer 7 is a differential clock signal, the output of the input clock buffer 7 is a single-ended or differential signal, the input of the output clock buffer 8 is a single-ended or differential signal, and the output of the output clock buffer 8 is a differential signal.

[0085] The input of the input clock buffer 7 is a differential clock signal, and the output of the input clock buffer 7 can be a single-ended signal or a differential signal. Inside the chiplet, the output of the input clock buffer 7 can be set according to design requirements. If there is a relay clock buffer, the relay clock buffer transmits the clock signal while keeping the signal type unchanged. Assuming the clock signal type remains unchanged, the signal type of the input of the output clock buffer 8 is the same as that of the output of the input clock buffer 7, and the clock signal type is a single-ended signal or a differential signal. The output of the output clock buffer 8 is a differential signal so that the input received by the input clock buffer 7 of adjacent chiplets is a differential clock signal.

[0086] Optionally, the input and output of the input clock buffer 7 are single-ended clock signals, and the output and input of the output clock buffer 8 are single-ended clock signals.

[0087] If the input of the input clock buffer 7 is a single-ended clock signal, the clock signal transmitted inside the chiplet and between subsequent chiplets is also a single-ended clock signal.

[0088] The chiplet packaging chip provided by the above embodiments can adapt to different types of clock signals and improve usability.

[0089] Based on the above embodiments, multiple chiplets are homogeneous or heterogeneous. If they are homogeneous, it means that in terms of the hardware structure, the number and positions of the input clock buffer 7 and the output clock buffer 8 provided on multiple chiplets are the same. If they are heterogeneous, it means that in terms of the hardware structure, the number and positions of the input clock buffer 7 and the output clock buffer 8 provided on multiple chiplets are the same.

[0090] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A chiplet package chip with clock signal distribution, characterized in that including a packaging substrate; The packaging substrate is located on a PCB substrate; the PCB substrate includes a first clock source; A plurality of dielets are packaged on the packaging substrate; two adjacent dielets are connected through an inter-die interface; Each dielet includes an input clock buffer, an output clock buffer, and at least one inter-die interface; the input clock buffer outputs a clock signal to each inter-die interface and the output clock buffer within the dielet where it is located; The plurality of dielets includes a first dielet and at least one second dielet; The first clock source is connected to the input clock buffer of the first dielet; the input clock buffer of the second dielet is connected to the output clock buffer of an adjacent dielet, and the adjacent dielet is the first dielet or a second dielet; The output clock buffers of the first dielet and the second dielet are connected to the input clock buffers of adjacent second dielets.

2. The chiplet-packaged chip according to claim 1, wherein The first dielet includes one output clock buffer, the second dielet includes one output clock buffer, and there are multiple second dielets; The clock signal starts from the first dielet and is unidirectionally serially transmitted on multiple second dielets in a preset order.

3. The chiplet-packaged chip according to claim 1, wherein The first dielet includes multiple output clock buffers, the second dielet includes one or more output clock buffers, and there are multiple second dielets; The clock signal starts from the first dielet and is multi-path parallel transmitted on multiple second dielets in a preset order.

4. The chiplet packaged chip according to claim 2 or 3, characterized in that, The output pin of the output clock buffer of the second dielet located at the transmission end is left floating or removed.

5. The chiplet-packaged chip according to claim 1, wherein The PCB substrate further includes a second clock source; the plurality of dielets includes a third dielet and at least one fourth dielet; The second clock source is connected to the input clock buffer of the third dielet; the input clock buffer of the fourth dielet is connected to the output clock buffer of an adjacent dielet, and the adjacent dielet is the third dielet or a fourth dielet; The output clock buffers of the third dielet and the fourth dielet are connected to the input clock buffers of adjacent fourth dielets; The third dielet and / or the fourth dielet is interconnected with the first dielet and / or the second dielet through an inter-die interface.

6. The chiplet-packaged chip according to claim 5, wherein, The inter-die interface unifies the clock signals of the first clock source and the second clock source through an elastic cache method.

7. The chiplet package chip according to claim 1, characterized in that, The dielet further includes at least one relay buffer; The input clock buffer outputs the clock signal to the inter-die interfaces within the dielet where it is located through the at least one relay clock buffer.

8. The chiplet-packaged chip according to claim 1, wherein, A plurality of dielets are packaged in an interposer, and the interposer is packaged in the packaging substrate; alternatively, the plurality of dielets are directly packaged in the packaging substrate.

9. The dielet-packaged chip according to claim 1, wherein The input of the input clock buffer is a differential clock signal, the output of the input clock buffer is a single-ended or differential signal, the input of the output clock buffer is a single-ended or differential signal, and the output of the output clock buffer is a differential signal; or, the input and output of the input clock buffer are single-ended clock signals, and the output and input of the output clock buffer are single-ended clock signals.

10. The chiplet-packaged chip according to claim 1, characterized in that, The plurality of dielets are homogeneous or heterogeneous.

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