Shielded gate trench field effect transistor and method of manufacturing the same

Abstract

Shielded gate trench field effect transistor and manufacturing method thereof, the present invention relates to power semiconductor devices, in order to improve the reliability of the existing shielded gate trench field effect transistor device, UIS performance, reverse conduction performance, and reduce the waste of silicon area. The present invention provides a kind of shielded gate trench field effect transistor, the field effect transistor utilizes integrated high resistance field plate trench, improves the breakdown problem caused by the uneven opening of cell in the switching process of device, and the high resistance field plate trench can also be used as a buffer to improve the overshoot current when the device switches and reverse recovers.

Description

TECHNICAL FIELD

[0001] The present application relates to the structure of power semiconductor devices, especially shielded gate trench MOSFET devices, and the manufacturing method thereof. BACKGROUND

[0002] The following will describe the related technical background of the existing shielded gate trench MOSFET. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "vertical" in this document are corresponding to the relative position of the reference drawing. In the specific implementation, it is not limited to the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn in specific proportions. The straight lines shown by the boundaries of the doped regions and trenches in the drawings, as well as the sharp corners formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0003] The shielded gate trench MOSFET has the characteristics of low on-resistance and fast switching speed. Figure 1 The shielded gate trench MOSFET has the characteristics of low on-resistance and fast switching speed.

[0004] The shielded gate electrode is usually formed by polysilicon, which provides a horizontal electric field for the device to improve the breakdown voltage of the cell. During switching, the source potential needs to be conducted to each cell along the shielded gate polysilicon. Due to the high resistivity of the polysilicon, there will be a delay in the potential signal between the cells, which will cause the potential of the shielded gate electrode in each cell to be different at the switching moment, causing some cells to break down early, or causing the avalanche current to concentrate in some cells, thereby damaging the device and affecting the reliability of the device. The shielded gate trench MOSFET device is provided with a termination region. The termination region of the conventional shielded gate trench MOSFET device is usually provided with a termination trench (112), and the shielded gate electrode (105) is in the termination trench. The shielded gate electrode (105) and the corresponding trench sidewall are isolated by a trench oxide layer (116). Generally, it is necessary to ensure that the breakdown voltage of the termination region is higher than that of the cell region, in order to ensure the reliability and UIS (UIS, Unclamped Inductive Switching) performance of the device. In the conventional device, methods such as setting a termination trench (112) deeper and wider than the cell trench, setting a termination region trench oxide layer (116) thicker than the cell region trench oxide layer (115), and forming a P-type island under the termination trench by additional ion implantation are usually used. These methods usually require additional silicon area or complex processes to achieve. In addition, as the breakdown voltage of the shielded gate trench MOSFET device increases, the thickness of the trench oxide layer needs to be increased. In high-voltage devices, an excessively thick trench oxide layer will waste more silicon area.

[0005] In addition, in the conventional shield gate trench field effect transistor device, due to the existence of the parasitic diode, the voltage drop is about 0.4V to 1V when the reverse conduction, the direct current loss is large, and the reverse recovery time is long. In order to reduce the reverse conduction voltage drop and shorten the reverse recovery time, the Schottky diode is usually integrated into the device. Although the field effect transistor device integrated with the Schottky diode improves the reverse conduction performance, it is easy to cause the reduction of the UIS capability of the device. Therefore, it is necessary to ensure that the breakdown voltage of the integrated Schottky diode is higher than the avalanche breakdown voltage of the field effect transistor, so as to ensure the reverse breakdown capability of the whole device. At the same time, the integrated Schottky diode is easy to cause the circuit to oscillate due to the small soft factor during the reverse recovery, which is not conducive to the reliability of the circuit system. SUMMARY

[0006] In order to improve the reliability, UIS performance, reverse conduction performance of the existing shield gate trench field effect transistor device, and reduce the waste of silicon area, the present application provides a shield gate trench field effect transistor, which comprises a drain metal layer at the bottom, a first conductive type heavily doped substrate layer above the drain metal layer, a first conductive type epitaxial layer above the first conductive type heavily doped substrate layer, a second conductive type doped body region and a first conductive type heavily doped source region above the first conductive type epitaxial layer; a source metal on the upper surface of the device, a series of cell trenches and high resistance field plate trenches are further provided on the first conductive type epitaxial layer, the cell trench comprises a gate electrode and a shield gate electrode, the gate electrode and the shield gate electrode are separated by an inter-electrode isolation layer, the shield gate electrode is connected to the source metal on the upper surface of the device; the high resistance field plate trench is provided with a high resistance field plate, the high resistance field plate is connected to the source metal on the upper surface of the device above and to the semiconductor in the trench bottom below; the width of the high resistance field plate trench is narrower than that of the cell trench, generally, the width of the high resistance field plate trench is 20-50% of the width of the cell trench (202).

[0007] The shield gate electrode extends from below the trench to above the trench, the gate electrode is divided into left and right electrodes, which are respectively located at the upper left and upper right positions of the shield gate electrode, or one electrode is directly located above the shield gate electrode.

[0008] Further, the left and right sides of the cell trench and the high resistance field plate trench are respectively provided with an insulating medium layer and a thin oxide layer for isolating the insulating medium layer and the side wall of the trench.

[0009] Further, the high resistance field plate trench is deeper than the cell trench, and the high resistance field plate trench can even extend into the first conductive type heavily doped substrate layer.

[0010] Further, the high-resistance field plate can also be composed of multiple materials with different resistivities from top to bottom. For example, the resistivity of the material used to make the high-resistance field plate increases from top to bottom. When the resistivity increases, the coupling electric field near the field plate also decreases. Therefore, the coupling electric field can be obtained by changing the resistivity of the field plate.

[0011] Further, the high-resistance field plate includes one or more Zener diodes composed of the second-conductivity-type semiconductor layer and the first-conductivity-type semiconductor layer from top to bottom. The PN junction structure formed in the high-resistance field plate can adjust the coupling voltage as required and reduce the leakage current.

[0012] Further, the high-resistance field plate also includes a high-resistance film. The thickness of the high-resistance film can be adjusted to obtain the required resistivity, and the problem of resistivity deviation in different trenches caused by process deviation of the trench width can be avoided.

[0013] Further, the high-resistance field plate trenches are arranged periodically near the cell trenches.

[0014] Further, a series of cell trenches form the active region, and a contact hole parallel to the cell trenches is arranged between the cell trenches, and the contact hole is connected to the upper surface metal. A series of high-resistance field plate trenches form the high-resistance field plate region, and the high-resistance field plate region is connected to the upper surface metal through another contact hole. Multiple high-resistance field plate regions and high-resistance field plate trenches can be uniformly arranged in the active region of the device to balance the transmission of the shielding gate type between the cells in the active region. Therefore, the high-resistance field plate region arranged in the easy breakdown region of the device can improve the overall avalanche breakdown resistance of the device. In addition, the high-resistance field plate region can also stabilize the current distribution during the reverse recovery of the field effect transistor, reduce the reverse current overshoot, and slow down the oscillation.

[0015] A Schottky diode can also be arranged in the high-resistance field plate region to form a new type of integrated Schottky diode shielding gate trench field effect transistor device.

[0016] Further, the high-resistance field plate region is distributed in the active region.

[0017] Further, the high-resistance field plate trenches in the high-resistance field plate region are perpendicular or parallel to the cell trenches in the active region.

[0018] In the active region, one or more small high-resistance field plate regions composed of a series of high-resistance field plate trenches are arranged.

[0019] Further, the contact hole above the high-resistance field plate trench of the part of the active region forms a Schottky contact between the semiconductor and the upper surface metal, and the area of the Schottky contact accounts for 5-20% of the total area of the device.

[0020] Further, the outermost periphery of the active region is provided with a second high-resistance field plate trench, and the second high-resistance field plate trench surrounds the series of cell trenches.

[0021] Further, the outermost periphery of the active region is provided with a second high-resistance field plate trench, and the second high-resistance field plate trench surrounds the series of cell trenches.

[0022] Further, the outermost periphery of the active region is provided with a second high-resistance field plate trench, and the second high-resistance field plate trench surrounds the series of cell trenches.

[0023] Further, the outermost periphery of the active region is provided with a second high-resistance field plate trench, and the second high-resistance field plate trench surrounds the series of cell trenches.

[0024] Further, the outermost periphery of the active region is provided with a second high-resistance field plate trench, and the second high-resistance field plate trench surrounds the series of cell trenches.

[0025] The application also provides a preparation method of the shield gate trench type field effect transistor, and the method comprises the following steps:

[0026] Firstly, a wider trench and a narrower trench are formed, and a thin oxide layer and an insulating medium layer are formed in the trenches; the two types of trenches can be formed by the same photoetching and ion etching, or can be formed by different photoetching steps and multiple ion etching to achieve different trench depths and trench slopes.

[0027] Secondly, the thin oxide layer and the insulating medium layer at the bottom of the trench are removed by dry etching.

[0028] Third step, high resistance material is formed in the trench and fills the narrow trench completely, while the wide trench is not filled completely; before filling the high resistance material or before removing the bottom thin oxide layer, one step ion implantation can be performed on the bottom of the trench to form ohmic contact area or PN junction area of the high resistance field plate; or before filling the high resistance material, the bottom semiconductor of the trench is etched further to increase the depth of the trench, which is beneficial to increase the contact area of the bottom of the high resistance field plate and the semiconductor.

[0029] If the material with the resistance changing from top to bottom is to be formed, the forming method is chemical vapor deposition (CVD), and the resistance is controlled by the change of the composition of the material in CVD.

[0030] If the high resistance thin film structure is to be formed in the high resistance field plate trench, it can be formed in this step, first depositing a high resistance thin film in the semiconductor trench, and then filling the trench with an insulating filler.

[0031] Fourth step, the high resistance material in the wide trench is removed by isotropic etching, while the narrow trench is still filled with high resistance material and forms a high resistance field plate trench structure; the high resistance material on the upper part of the narrow trench can be partially etched; after isotropic etching, one step dry etching can be performed to remove the residual high resistance material on the surface of the semiconductor.

[0032] Fifth step, a thick oxide layer is formed in the wide trench, the shielding gate electrode material is filled and etched back, and then the thick oxide layer is etched back; the thick oxide layer can be formed by chemical vapor deposition; or the trench can be first filled with polysilicon, and then the polysilicon is thermally oxidized to form; the etching depth of the shielding gate electrode material is usually 0.1-0.5um below the upper surface of the semiconductor, or it can be etched to a position below the gate electrode in the final structure, about 0.5-1.5um below the upper surface of the semiconductor, and a whole gate electrode structure is formed above the trench in the subsequent process. Before etching the thick oxide layer, the shielding gate electrode material can be subjected to one step ion implantation with the thick oxide layer as the hardest mask to increase the oxidation rate of the shielding gate electrode material in the subsequent process. During the etching back of the thick oxide layer, the insulating medium layer plays a role in protecting the sidewall of the trench.

[0033] Sixth step, thermal oxidation is performed to form an inter-electrode oxide layer on the shielding gate electrode material; the thickness of the inter-electrode oxide layer is between 0.1-0.5um. During the thermal oxidation process, the insulating medium layer plays a role in protecting the sidewall of the trench.

[0034] Seventh step, gate oxide layer and gate electrode are formed and the device is finally formed.

[0035] Further, the high-resistance thin film formed in the third step is deposited in the semiconductor trench first, and then the trench is filled with an insulating filler.

[0036] The trench type field effect transistor device structure of the present application integrates the high-resistance field plate trench, which improves the breakdown problem caused by the uneven opening of the cell during the switching process of the device. In addition, the high-resistance field plate trench in the structure can be used as a snubber, which improves the overshoot current during the switching and reverse recovery of the device.

[0037] The trench type field effect transistor device structure of the present application uses the high-resistance field plate trench as the terminal of the device, which improves the reliability and UIS performance of the device.

[0038] The trench type field effect transistor device structure of the present application integrates the high-resistance trench and Schottky diode, which uses the high-resistance field plate to improve the breakdown voltage of the Schottky diode, ensures the reverse breakdown performance of the device, and integrates the reverse recovery performance of the Schottky diode, thereby improving the reliability of the circuit system. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 It is a cross-sectional view of an existing shield gate trench type field effect transistor device.

[0040] Figure 2 It is a cross-sectional view of an embodiment of the device of the present application.

[0041] Figures 3A-3F It is a cross-sectional view of an embodiment of the device of the present application. Figure 2 It is a cross-sectional view of the key steps of the manufacturing process of the embodiment of the present application.

[0042] Figure 4A It is a cross-sectional view of the key steps of the manufacturing process of the high-resistance field plate trench structure in an embodiment of the device of the present application.

[0043] Figure 5 It is a cross-sectional view of an embodiment of the device of the present application.

[0044] Figure 6A It is a top view of the structure of part of the trench and the contact hole of an embodiment of the device of the present application.

[0045] Figure 6B It is a top view of the structure of part of the trench and the contact hole of an embodiment of the device of the present application.

[0046] Figure 6C It is a top view of the structure of part of the trench and the contact hole of an embodiment of the device of the present application.

[0047] Figure 6DTop view of trench and contact hole structure for one embodiment of the inventive device.

[0048] Figure 7A Top view of trench structure for the termination region of one embodiment of the inventive device.

[0049] Figure 7B Top view of trench and contact hole structure for the termination region of one embodiment of the inventive device.

[0050] Figure 7C Top view of trench and contact hole structure for the termination region of one embodiment of the inventive device. DETAILED DESCRIPTION

[0051] The present invention is described in detail below with reference to the attached drawing figures and embodiments. It is noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be made of silicon (Si) material. However, the substrate can also be made of any other suitable material for the manufacture of shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type), a P-type conductivity semiconductor region can be formed by doping one or more impurities into the original semiconductor region, which can be but not limited to: boron (B), aluminum (Al), gallium (Ga), etc., and an N-type conductivity semiconductor region can also be formed by doping one or more impurities into the original semiconductor region, which can be but not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), proton (H+), etc. In the following description, a heavily doped P-type conductivity semiconductor region is labeled as P + region, and a heavily doped N-type conductivity semiconductor region is labeled as N + region. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is generally between 1 x 1018 19 cm -3 and 1 x 1020 21 cm -3 -3. Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in the present invention can be interchanged.

[0052] Figure 2 A semiconductor field effect transistor device of the first embodiment, which includes at least two types of trenches: cell trenches (202), and high resistance field plate trenches (212). In addition, it includes: a bottom drain metal layer (213); an N + substrate layer (200) above the drain metal layer; an N +N-type epitaxial layer (201) on the substrate layer; P-doped body region (208) and N + doped source region (209); wherein the cell trench (202) at least contains a gate electrode (206) above the trench and a shield gate electrode (204) below. The gate electrode (206) is separated from the trench sidewall by a gate oxide layer. The gate electrode (206) is separated from the shield gate electrode (204) by an inter-electrode separation layer. The shield gate electrode (204) is connected to the source metal (211) on the top surface of the device. In addition, there is a thick oxide layer (225) between the shield gate electrode (204) and the trench sidewall. The high-resistance field plate trench (212) at least contains a high-resistance field plate (223) in the trench. The high-resistance field plate (223) is connected to the source metal (211) on the top surface of the device above and to the semiconductor in the bottom of the trench below.

[0053] In addition, as shown in Figure 2 the left and right sidewalls of the cell trench (202) and the high-resistance field plate trench (212), there can also be a thin oxide layer (221) and an insulating medium layer (222). The insulating medium layer (222) is beneficial to the formation of a thicker inter-electrode separation layer during the manufacture of the shield gate trench type field effect transistor, and reduces the stress on the trench sidewall during the manufacturing process. The thin oxide layer (221) acts on the insulating medium layer (222) and the isolation trench, and can prevent lattice defects from occurring at the trench sidewall.

[0054] The gate electrode (206) and the shield gate electrode (204) in the cell trench (202) are usually composed of polysilicon, but can also be composed of amorphous silicon, metal, or metal compounds. As shown in Figure 2 the shield gate electrode (204) extends from below the trench to above the trench, and the gate electrode (206) is located above and to the left and right of the shield gate electrode (204). However, in some embodiments, the shield gate electrode (204) can not extend above the trench, but can be located directly below the gate electrode (206); at the same time, the gate electrode (206) can not be divided into left and right electrodes, but can be combined into one electrode located directly above the shield gate electrode (204).

[0055] The width of the high-resistance field plate trench (212) is narrower than the width of the cell trench (202), and the narrower trench (212) is beneficial to the formation of a high-resistance field plate (223) with a larger resistance value. For example, in a 100V embodiment, the width of the high-resistance field plate trench (212) is 20-50% of the width of the cell trench (202).

[0056] The depth of the high-resistance field plate trench (212) is usually comparable to or deeper than the depth of the cell trench (202), and can even extend to the N +In the substrate layer (200).

[0057] When the device is reverse biased, the shield gate (204) connected to the source potential in the cell trench (202) creates a horizontal electric field in the adjacent semiconductor through the thick oxide layer (225). At this time, the electric field generated on the sidewall at the deep of the trench is large, which can result in uneven electric field distribution and limit the breakdown voltage. In the high resistance field plate trench (212), because the high resistance field plate (223) forms a current path from the upper source metal (211) to the lower drain metal (213), a uniformly distributed electric field is generated and coupled into the adjacent semiconductor, so that a higher breakdown voltage can be achieved.

[0058] The high resistance field plate (223) can be composed of high resistance polysilicon (SIPOS), amorphous silicon, silicon oxynitride, metal compounds (such as TiN, SiTi, etc.), or organic compounds, etc., and the temperature coefficient of resistivity of the material is positive.

[0059] Generally, a narrower trench (212) is conducive to forming a high resistance field plate (223) with a larger resistance value. In an embodiment of a 100V device, the width of the high resistance field plate is between 0.05-0.5um, and the resistivity of the high resistance field plate is between 1e-4 Ohm-m to 1e-7 Ohm-m.

[0060] In addition, the high resistance field plate (223) can also be composed of multiple materials with different resistivities from top to bottom. When the resistivity increases, the coupling electric field near the corresponding field plate also decreases. Therefore, by changing the resistivity in the field plate, the coupling electric field required by the design can be obtained. In an embodiment, the resistivity of the high resistance field plate (223) changes with depth, which is low at the top and high at the bottom. In an embodiment, the upper part of the high resistance field plate (223), which is 0-0.5um away from the upper surface of the semiconductor, has a resistivity between 1e-6 to 1e-10 Ohm-m, and the resistivity is lower than that of the lower part.

[0061] The high resistance field plate (223) can also be composed of multiple semiconductor materials with different doping from top to bottom, and form one or more PN junction structures. Through the PN junction structure, the coupling voltage required by the design can be adjusted, and the leakage current in the high resistance field plate can be reduced. In an embodiment, the high resistance field plate (223) contains multiple P-type and N-type semiconductor layers from top to bottom and forms a Zener diode.

[0062] Generally, the shield gate electrode (204) is made of polysilicon, and the source signal needs to pass through a long polysilicon material from the source metal to the cell far away from the source contact hole, which affects the response speed of the cell's inner shield gate electrode (204). The additional high-resistance field plate and shield gate electrode (204) can form a new RC network, balance the response speed of the shield gate electrode (204) in different cells, and prevent device breakdown problems caused by inconsistent cell response speeds.

[0063] Figures 3A to 3D A key step in the implementation of a manufacturing method for the above-mentioned first embodiment device is shown.

[0064] First, two types of trenches with different widths are formed, wide trenches (202) and narrow trenches (212), and thin oxide layers (221) and insulating medium layers (222) are formed in the trenches, as shown in Figure 3A . The two types of trenches can be formed by the same photolithography and ion etching step; or they can be formed by different photolithography steps and multiple ion etching steps to achieve different trench depths and trench slopes. The insulating medium layer (222) can be nitride, polymer, or a combination thereof.

[0065] Second, use dry etching to remove the thin oxide layer (221) and the insulating medium layer (222) at the bottom of the trench, as shown in Figure 3B .

[0066] Third, form a high-resistance material (223) in the trench and completely fill the narrower trench (212), while the wider trench (202) is not completely filled, as shown in Figure 3C . Before filling the high-resistance material (223) or removing the bottom thin oxide layer, it is possible to perform a step of ion implantation at the bottom of the trench to form an ohmic contact area or a PN junction area of the high-resistance field plate. Before filling the high-resistance material (223), it is also possible to further etch the semiconductor at the bottom of the trench to increase the trench depth, which is beneficial to increasing the contact area between the high-resistance field plate bottom and the semiconductor.

[0067] Fourth, use isotropic etching to remove the high-resistance material (223) in the wider trench (202), while the narrower trench still has high-resistance material (223) and forms a high-resistance field plate trench (212) structure, as shown in Figure 3D . The high-resistance material (223) at the top of the narrow trench can be partially etched. In addition, after isotropic etching, a step of dry etching can be performed to remove the remaining high-resistance material on the surface of the semiconductor.

[0068] Fifth, form a thick oxide layer (225) in the wider trench (202), fill and etch back the shield gate electrode material (204), and then etch back the thick oxide layer (225), as shown inFigure 3E The thick oxide layer can be formed by chemical vapor deposition (CVD) or by first filling the trench with polysilicon and then thermally oxidizing the polysilicon. The etch stop gate electrode material (204) is typically etched using a dry etch process that can stop at a depth of 0.1-0.5 um below the top surface of the semiconductor or can be etched to a depth of 0.5-1.5 um below the top surface of the semiconductor to form a full gate electrode structure over the trench in a subsequent process. Prior to etching the thick oxide layer (225), an ion implantation can be performed on the etch stop gate electrode material (204) using the thick oxide layer (225) as a hard mask to increase the oxidation rate of the etch stop gate electrode material (204) in a subsequent process. The insulating dielectric layer (222) protects the trench sidewalls during the etching of the thick oxide layer (225).

[0069] In a sixth step, a thermal oxidation is performed to form an interpoly oxide layer (206) on the etch stop gate electrode material (204), as shown in FIG. 2F. The thickness of the interpoly oxide layer is between 0.1-0.5 um. The insulating dielectric layer (222) protects the trench sidewalls during the thermal oxidation. Figure 3F

[0070] In a seventh step, a gate oxide layer and a gate electrode are formed to complete the device.

[0071] The above process steps do not require additional photolithography steps to form the two trench structures (202, 212) and can form a high quality interpoly oxide layer to prevent gate-to-source leakage. In some embodiments, the steps related to the insulating dielectric layer (222) in the first and second steps can be omitted and the interpoly oxide layer is formed at the same time as the gate oxide layer in the sixth step to simplify the process flow.

[0072] In the third step of the above process, different variations can be used in the process flow depending on the specific structure and material of the high resistance field plate trench (212). In one embodiment, the high resistance field plate (223) is formed from a material with a varying resistance from top to bottom by a chemical vapor deposition (CVD) process and the resistance is controlled by varying the composition of the material in the CVD process.

[0073] In another embodiment, the high resistance field plate trench (212) includes a high resistance film (223) structure and the key steps to form the high resistance film (223) are as follows:

[0074] In the third step of the above process, a high resistance film (223) is deposited in the semiconductor trench, as shown in FIG. 2C. Then, an insulating filler (227) is filled in the trench, as shown in FIG. 2D. Figure 4A Figure 4B

[0075] ​​​The insulating fill (227) can be nitride, oxide, or organic compound. In the above structure, the desired resistivity can be adjusted by adjusting the thickness of the high-resistance film (223), and the problem of resistivity deviation in different trenches due to process deviation of the trench width can be avoided.

[0076] The high-resistance field plate trenches (212) mentioned above are usually arranged periodically and distributed near the cell trenches (202), as shown in the following figure. Figure 5

[0077] The distance between the high-resistance field plate trenches (212) can be different from the distance between the cell trenches (202). The high-resistance field plate in the high-resistance field plate trenches (212) is directly connected to the upper surface metal (211) and forms a vertical current path.

[0078] Usually, there is an ion implantation region (218) on the semiconductor upper surface between the high-resistance field plate trenches (212). The ion implantation region can be a P-type region and formed by the ion implantation process for forming the P-doped body region (208); or formed by etching the contact hole and then performing P-type ion implantation. + The ion implantation region can also be formed by the above two steps.

[0079] The ion implantation region (218) can also be a lightly doped region and form a Schottky contact with the upper surface metal to form an integrated Schottky diode structure. In one embodiment, there is a layer of material containing TiN or TiSi between the upper surface metal and the ion implantation region (218), and the doping concentration of the ion implantation region is lower than or equal to the semiconductor epitaxial layer (201).

[0080] In addition, there can be an ion implantation region under the high-resistance field plate trench (212) and form an ohmic contact with the high-resistance field plate.

[0081] In addition, there can be a P-type ion implantation region on the sidewall or under the high-resistance field plate trench (212) and generate a depletion region when the device is reverse biased to further improve the breakdown voltage of the high-resistance field plate trench (212).

[0082] In the embodiment device mentioned in the present application, the high-resistance field plate trenches (212) can have various layout implementations:

[0083] One layout implementation method is as follows: Figure 6A ​As shown in FIG. 6A, the series of high-resistance field plate trenches (212) and the series of cell trenches (202) have the same direction of arrangement, and form high-resistance field plate regions (301) and active regions (302), respectively. The series of cell trenches (202) are connected to the upper surface metal through contact holes (220) parallel to the cell trenches (202). The series of high-resistance field plate trenches (212) are connected to the upper surface metal through contact holes (220) above the high-resistance field plate trenches (212).

[0084] In another layout implementation method, the series of high-resistance field plate trenches (212) and the series of cell trenches (202) have perpendicular directions of arrangement, as shown in FIG. 6B. Figure 6B

[0085] In another layout implementation method, one or more small high-resistance field plate regions (301) composed of the series of high-resistance field plate trenches (212) are arranged in the active region (302), as shown in FIG. 6C. Figure 6C

[0086] In another layout implementation method, a small section of high-resistance field plate trenches (212) with the same direction and connected to each other are arranged in a section of cell trenches (202), as shown in FIG. 6D. Figure 6D

[0087] In the above structure, the high-resistance field plate trenches (212) and the series of cell trenches (202) can be connected together, as shown in FIG. 6D. In fact, the two types of trenches can also be separated to form independent trenches. Figure 6C

[0088] In combination with the above various layout implementation examples, multiple high-resistance field plate regions (301) and high-resistance field plate trenches (212) can be uniformly arranged in the active region (302) of the device to balance the transmission of the shield gate type number between the cells in the active region. At the same time, since the breakdown voltage of the high-resistance field plate region (301) is higher than that of the active region (302), arranging the high-resistance field plate region (301) in the easy breakdown region of the device can improve the overall avalanche breakdown resistance of the device. In addition, the high-resistance field plate region (301) can also stabilize the current distribution during the reverse recovery of the field effect transistor, reduce the reverse current overshoot, and slow down the oscillation.

[0089] In the above structure, Schottky diodes can be arranged in the high-resistance field plate region (301) to form a new type of integrated Schottky diode shield gate trench type field effect transistor device.

[0090] In a specific embodiment, the series of high-resistance field plate trenches (212) in a part of the active region, the contact holes (220) above which, form Schottky contact between the semiconductor and the upper surface metal.

[0091] ​​​​In one embodiment, the area of the above-mentioned Schottky contact forming region is 5-20% of the whole device. The above-mentioned integrated Schottky diode region can reduce the reverse voltage drop and reverse recovery time of the device. Meanwhile, the high-resistance field plate (212) in this region can ensure the reliability of the Schottky diode region when the device is reversely broken down, and can reduce the resonance between the source and the drain in the reverse recovery, ensuring the reliability of the circuit system.

[0092] In addition to the above structure, the high-resistance field plate trench (212) can be arranged at the outermost periphery of the series of cell trenches (202) as a terminal region of the device.

[0093] Figure 7A The top view of the trench of the terminal region of one embodiment of the present application. At least one second high-resistance field plate trench (212) is located at the outermost periphery of the active region (302) and surrounds the series of cell trenches (202).

[0094] The cell trench (202) can be connected to the high-resistance field plate (223) in the high-resistance field plate trench (212) in the vertical direction, and the shielding gate electrode (204) in the cell trench (202) is connected to the high-resistance field plate (223) in the high-resistance field plate trench (212).

[0095] Figure 7B The top view of the trench and contact hole of the terminal region of another embodiment of the present application. Compared with the above-mentioned embodiment, a series of extension trenches (242) are extended outwardly at the periphery of the second high-resistance field plate trench (212) surrounding the active region. The extension trench (242) is the high-resistance field plate trench (212). The high-resistance field plate trench (212) surrounding the active region can have a contact hole (220) above it connected to the source metal on the upper surface. The contact hole can be connected to the contact hole in the active region.

[0096] The extension trenches (242) are usually parallel to each other, and a P-type implantation region can be located between the trenches or at the bottom of the trenches. At the corners of the high-resistance field plate trench (212) surrounding the active region, a series of extension trenches can be at a 45-degree angle to the cell trench.

[0097] In one embodiment, the outermost end of the extension trench (242) is connected to the drain potential. In a 100V device embodiment, the length of the extension trench (242) extended outwardly is between 3 and 15um.

[0098] In the above-mentioned structure, the extension trench (242) can make the electric field distribution of the source on the upper surface of the semiconductor to the chip periphery direction more uniform, improve the breakdown voltage of this region, enhance the UIS capability of the device, and reduce the influence of mobile ions on the terminal, thereby improving the reliability of the device.

[0099] Figure 7C A top view of a terminal region of a device according to another embodiment of the present application. The structure is similar to the above embodiment, but in the outermost periphery of the active region (302), there are at least two rings of high resistance field plate trenches (212) surrounding the active region (302), and between the outermost high resistance field plate trenches, there is a series of high resistance field plate trenches (252) perpendicular to the outermost high resistance field plate trenches, forming a ladder-like high resistance field plate trench structure.

[0100] The ladder-like high resistance field plate trenches (252) can have P-type implant regions between the trenches and at the bottom of the trenches. The terminal region of the device can be composed of multiple ladder-like high resistance field plate trench structures, forming a network-like structure. In one embodiment, the outermost ladder-like high resistance field plate trenches (252) are in the form of cell trenches (202) structure. The cell trenches function to connect the outermost ladder-like high resistance field plate trenches (252) to the same potential.

[0101] In one embodiment, the outermost ladder-like high resistance field plate trenches (252) are connected to the drain potential through contact holes.

[0102] In the above structure, the ladder-like high resistance field plate trenches (252) achieve the function of the epitaxial trenches (242) in the above embodiment, and further adjust the electric field distribution in different regions of the semiconductor surface by adjusting the density of the multi-layer ladder-like high resistance field plate trench network. For example, to further reduce the electric field in regions that are prone to breakdown, such as the corners of the trenches or near the gate metal. Figure 7B In addition to the function of the epitaxial trenches (242) in the above embodiment, the ladder-like high resistance field plate trenches (252) can further adjust the electric field distribution in different regions of the semiconductor surface by adjusting the density of the multi-layer ladder-like high resistance field plate trench network. For example, to further reduce the electric field in regions that are prone to breakdown, such as the corners of the trenches or near the gate metal.

[0103] It should be understood by those skilled in the art that the structural features and process steps mentioned in each of the above embodiments of the present application can be combined to form more device structures and manufacturing processes.

Claims

1. A shielded-gate trench field effect transistor comprising a bottom drain metal layer, a first conductivity type heavily doped substrate layer overlying the drain metal layer, a first conductivity type epitaxial layer overlying the first conductivity type heavily doped substrate layer, a second conductivity type body region and a first conductivity type heavily doped source region overlying the first conductivity type epitaxial layer, and a source metal on the top surface of the device, characterized by, A series of cell trenches and high-resistance field plate trenches are arranged on the first-conductivity-type epitaxial layer, the cell trenches contain gate electrodes and shielding gate electrodes, the shielding gate electrodes are connected to the source metal on the upper surface of the device, the high-resistance field plate trenches contain high-resistance field plates, the high-resistance field plates are connected to the source metal on the upper surface of the device above and to the semiconductor at the bottom of the trench below, the width of the high-resistance field plate trench is 20-50% of the width of the cell trench (202), and the left and right sides of the cell trench and the high-resistance field plate trench are respectively provided with an insulating dielectric layer and a thin oxide layer for isolating the insulating dielectric layer and the sidewall of the trench. ​ 2. The shielded gate trench field effect transistor of claim 1, wherein, The high-resistance field plate trench is deeper than the cell trench.

3. The shielded gate trench field effect transistor of claim 1, wherein: The resistivity of the high-resistance field plate increases from top to bottom.

4. The shielded gate trench field effect transistor of claim 1, wherein: The high-resistance field plate contains one or more Zener diodes composed of a second-conductivity-type semiconductor layer and a first-conductivity-type semiconductor layer from top to bottom.

5. The shielded gate trench field effect transistor of claim 1, wherein: The high-resistance field plate contains a high-resistance film.

6. The shielded gate trench field effect transistor of claim 1, wherein: The high-resistance field plate trenches are periodically arranged near the cell trenches.

7. The shielded gate trench field effect transistor of claim 1, wherein: A series of cell trenches form an active region, the cell trenches are provided with contact holes parallel thereto, the contact holes are connected to the upper surface metal, and a series of high-resistance field plate trenches form a high-resistance field plate region, the high-resistance field plate region is connected to the upper surface metal through another contact hole.

8. The shielded gate trench field effect transistor of claim 7, wherein the gate trench is formed in the substrate and the gate trench is filled with a gate electrode material. The high-resistance field plate region is distributed in the active region.

9. The shielded gate trench field effect transistor of claim 8, wherein the gate trench is formed in the substrate and the gate trench is filled with a gate electrode material. The high-resistance field plate trenches in the high-resistance field plate region are perpendicular or parallel to the cell trenches in the active region.

10. The shielded gate trench field effect transistor of claim 7, wherein: In the contact holes above the high-resistance field plate trenches in a part of the active region, the semiconductor and the upper surface metal form a Schottky contact, and the area of the Schottky contact region accounts for 5-20% of the total area of the device.

11. The shielded gate trench field effect transistor of claim 7, wherein: The outermost periphery of the active region is further provided with one or more second high-resistance field plate trenches, and the series of cell trenches are surrounded by the second high-resistance field plate trenches.

12. The shielded gate trench field effect transistor of claim 11, wherein: The outer periphery of the second high-resistance field plate trench is further provided with a series of epitaxial trenches perpendicular to the second high-resistance field plate trench, and the outermost end of the epitaxial trench is connected to the drain potential. And / or a series of epitaxial trenches at a 45-degree angle to the cell trenches are arranged at the corners of the high-resistance field plate trenches surrounding the active region.

13. The shielded gate trench field effect transistor of claim 12, wherein: The outer periphery of the epitaxial trench is further provided with a third high-resistance field plate trench perpendicular to the epitaxial trench, the third high-resistance field plate trench and the epitaxial trench form a ladder-shaped high-resistance field plate trench structure, and the device periphery is provided with one or more ladder-shaped high-resistance field plate trench structures.

14. The shielded gate trench field effect transistor of claim 1, wherein: The high-resistance field plate trench is connected to the cell trench.

15. A method for manufacturing a shielded-gate trench field-effect transistor, characterized by: The method comprises the following steps: First step, form wide trenches and narrow trenches, and form thin oxide layers and insulating dielectric layers in the trenches respectively; Second step, remove the thin oxide layers and insulating dielectric layers at the bottom of the trench; Third step, form high-resistance material in the trench and completely fill the narrow trench, at this time the wide trench is not completely filled; Fourth step, remove the high-resistance material in the wide trench by isotropic etching, at this time the narrow trench is still filled with high-resistance material and forms a high-resistance field plate trench structure; In the fifth step, a thick oxide layer is formed in the wider trench, the shield gate electrode material is filled and etched back, and the thick oxide layer is etched back; In the sixth step, thermal oxidation is performed to form an inter-electrode oxide layer on the shield gate electrode material; In the seventh step, a gate oxide layer and a gate electrode are formed, and the device is finally formed.

16. The manufacturing method of a shielded gate trench field effect transistor according to claim 15, wherein In the third step, a high-resistance thin film is formed by first depositing a high-resistance thin film in the semiconductor trench, and then filling the trench with an insulating filler.

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