Fast protection control circuit for an ultrafast laser and its control method

Abstract

The present invention relates to a fast protection control circuit and a control method for an ultrafast laser. The host computer sends a laser startup instruction to the MCU through a communication interface. After receiving the instruction, an alarm reset signal is output to the alarm monitoring module of the FPGA, and a seed source enable signal is sent to the enable module. The seed source enable signal is then input to the seed source pump driver, and the seed pump source is driven to emit laser through the port of the optical path system. Mode-locked laser pulses are generated under the action of the optical path system. A part of the laser is split by the optical splitter of the optical system and output from the port, and the rest is pre-amplified and re-amplified by the amplifier stage pump. The pulsed laser output by the optical path system is input to the photodetector, which converts the pulsed optical signal into a pulsed electrical signal for output. The electrical pulse is input to the optical power meter module for power reading, and an analog quantity is output to the MCU for acquisition by the analog-to-digital converter. The calibration coefficient is used to calculate the seed optical power, and whether the optical power of the seed is abnormal is monitored.

Description

Technical Field

[0001] The present invention relates to a fast protection control circuit for an ultrafast laser and a control method thereof. Background Art

[0002] Currently, in the field of laser processing, ultrafast lasers such as picosecond lasers and femtosecond lasers are increasingly widely used. However, if a fatal abnormality occurs in the laser itself, it will cause damage to internal optical components of the laser, such as crystals. For example, when an abnormality occurs in the seed optical pulse of an ultrafast laser, it will cause giant pulses in the subsequent amplification stage and break down the amplification stage crystal, and the laser will show a power disappearance. This not only prolongs the laser repair time, but also directly affects the processing quality and production capacity.

[0003] Therefore, it is necessary to develop a control method for achieving fast protection when an abnormality occurs in the laser. Summary of the Invention

[0004] The object of the present invention is to overcome the deficiencies of the prior art and provide a fast protection control circuit for an ultrafast laser and a control method thereof, which can immediately protect when the seed power is too low or the seed mode locking is abnormal, and avoid direct damage to the laser.

[0005] The object of the present invention is achieved by the following technical solutions:

[0006] Fast protection control circuit for an ultrafast laser, characterized in that: the communication interface is connected to the communication terminal of the MCU; the reset output port of the MCU is connected to the global reset input terminal of the FPGA; the frequency division data output port of the MCU is connected to the input pin of the FPGA and then connected to the input terminal of its frequency divider; the enable data output port of the MCU is connected to the input pin of the FPGA and then connected to the input terminal of its enable module; the alarm clearing output signal port of the MCU is connected to the input pin of the FPGA and then connected to the input terminal of its alarm monitoring module; the data output port of the MCU is connected to the input pin of the digital-to-analog converter, and the analog-to-digital conversion channel input port of the MCU is connected to the output terminal of the optical power meter module; the crystal oscillator is connected to the clock input port of the FPGA; the output of the digital-to-analog converter is connected to the input terminal of the comparator; the output of the photodetector is connected to the input port of the optical power meter module; the output of the photodetector is connected to the input terminal of the comparator and connected to the input terminal of the FPGA and then connected to the input terminal of its phase-locked loop frequency multiplication module; the frequency multiplication clock output terminal of the phase-locked loop frequency multiplication module is connected to the input port of the frequency divider; the latch output port of the phase-locked loop frequency multiplication module is connected to the input terminal of the alarm monitoring module; the output port of the comparator is connected to the input pin of the FPGA and then connected to the input port of its alarm monitoring module; the output terminal of the frequency divider is connected to the input terminal of the AOM driver; the output terminal 1# of the enable module is connected to the input terminal of the seed source pump drive; the output terminal 2# of the enable module is connected to the output terminal of the first amplifier stage pump drive; the output terminal 3# of the enable module is connected to the output terminal of the second amplifier stage pump drive; the output terminal 4# of the enable module is connected to the output terminal of the third amplifier stage pump drive; the output terminal of the alarm monitoring module is connected to the input terminal of the enable module; the output terminal of the alarm monitoring module is connected to the input port of the MCU and connected to the alarm signal interface; the output terminal of the AOM driver is connected to the input terminal 1# of the optical path system; the output terminal of the seed source pump drive is connected to the input terminal 2# of the optical path system; the output terminal of the first amplifier stage pump drive is connected to the input terminal 3# of the optical path system; the output terminal of the second amplifier stage pump drive is connected to the input terminal 4# of the optical path system; the output terminal of the third amplifier stage pump drive is connected to the input terminal 5# of the optical path system; one output terminal of the optical path system is connected to the input terminal of the photodetector; one output terminal of the optical path system is used to output laser.

[0007] Further, in the above fast protection control circuit for an ultrafast laser, the FPGA is a field programmable gate array FPGA of model XC6SLX4-2TQG144C.

[0008] Further, in the above fast protection control circuit for an ultrafast laser, the crystal oscillator is a 20M crystal oscillator.

[0009] Further, in the above fast protection control circuit for an ultrafast laser, the MCU is an MCU of model STM32F103.

[0010] Further, for the fast protection control circuit of the above-mentioned ultrafast laser, the digital-to-analog converter is a digital-to-analog converter of model MCP4822T.

[0011] Further, for the fast protection control circuit of the above-mentioned ultrafast laser, the comparator is a comparator of model TLV1805.

[0012] For the fast protection control method of the ultrafast laser of the present invention, the MCU outputs a low-level reset signal to the FPGA, and the FPGA resets and clears each of its registers with the clock input by the crystal oscillator;

[0013] The host computer sends a laser startup instruction to the MCU through the communication interface. After receiving the instruction, the MCU outputs an alarm clearing signal to the alarm monitoring module of the FPGA, sends a seed source enabling signal to the enabling module through the enabling data port. The enabling module outputs the seed source enabling signal to the seed source pump drive. The seed source pump drive drives the seed pump source to emit laser through the port of the optical path system. At the same time, mode-locked laser pulses are generated under the action of the saturable absorber optical device in the optical path system; a part of the mode-locked laser pulses is split by the optical splitter of the optical system and output from the port, and the rest is pre-amplified and re-amplified by the amplifier stage pump.

[0014] The pulsed laser output from the port of the optical path system is input to the photodetector. The photodetector converts the pulsed optical signal into a pulsed electrical signal and outputs it; the electrical pulse output by the photodetector is input to the optical power meter module for power reading. The optical power meter module outputs an analog quantity to the MCU. The analog-to-digital converter of the MCU collects it and calculates the current seed optical power size using the calibration coefficient, and can monitor whether the optical power of the seed is abnormal;

[0015] The stable mode locking of the ultrafast laser seed corresponds to a certain current range of the pump source. Therefore, different currents have different amplitudes of the electrical pulse signals output from the photodetector. The signal is input to the positive input terminal of the comparator. The negative input terminal of the comparator is used to set the threshold voltage. Therefore, when the amplitude of the electrical pulse output by the photodetector is higher than the set threshold voltage, the comparator outputs an electrical pulse signal with a frequency consistent with the seed mode locking frequency. If the amplitude of the electrical pulse output by the photodetector is lower than the set threshold, the comparator outputs a low level; the threshold voltage of the negative input terminal of the comparator is sent by the host computer to the MCU through the communication interface, and the MCU then sends data to the digital-to-analog converter to achieve the output of the analog voltage; during normal operation, the comparator outputs a pulsed signal to the alarm monitoring module. If the seed power is too low, a low-level signal is output to the alarm monitoring module;

[0016] The optoelectronic detector outputs an electrical pulse frequency signal consistent with the seed mode-locking frequency to the phase-locked loop frequency doubling module of the FPGA. The input frequency is doubled to 100 MHz and then output to the frequency divider of the FPGA. After the frequency doubling is completed, the phase-locked loop frequency doubling module outputs a latch signal indicating that the synchronous phase-locking is completed. Normally, the signal is at a high level. If the seed source mode-locking is abnormal during operation, the input frequency of the phase-locked loop frequency doubling module suddenly becomes abnormal, the phase-locking fails, and the latch signal becomes low. The latch signal is directly input to the alarm monitoring module;

[0017] Since the laser needs to work at different fundamental frequencies, corresponding frequencies need to be set. The host computer sends frequency parameters to the MCU through the communication interface. The MCU converts the frequency parameters into corresponding data and sends them to the frequency divider. The frequency divider divides the frequency-doubled clock and then outputs it to the AOM driver. After the AOM driver outputs, it is input through one end of the optical path system and acts on the AOM, enabling the laser of the corresponding frequency to be output from one end of the output optical path system;

[0018] After receiving the startup instruction sent from the host computer, the MCU not only enables the seed source pump drive but also enables the pump drive of the power amplification stage. The number of amplification stages depends on the output power requirement. The MCU sends enable signals for each stage to the enable module through the enable data line. If the signal at the output end of the alarm monitoring module is low, the enable module outputs enable signals to the first pump drive of the amplification stage, the second pump drive of the amplification stage, and the third pump drive of the amplification stage respectively through the output end. The outputs of the first pump drive of the amplification stage, the second pump drive of the amplification stage, and the third pump drive of the amplification stage act on the output light of the pump source of the amplification stage of the optical path system through the input end of the optical path system.

[0019] Further, in the above-mentioned fast protection control method of the ultrafast laser, the latch output of the phase-locked loop frequency doubling module and the output of the comparator are used as fast and timely alarm signals to act on the alarm monitoring module. Since the seed light frequency is 25 MHz or 40 MHz, the response time of these two signals does not exceed 100 nS; when the alarm monitoring module receives one of the two signals, it immediately shuts off the enables of the first pump drive of the amplification stage, the second pump drive of the amplification stage, and the third pump drive of the amplification stage to avoid damaging the optical crystal; the alarm monitoring module outputs an alarm signal from the output end to the MCU and at the same time outputs it to an external device through the alarm signal interface; from the time when the alarm monitoring module receives the abnormal signal from the phase-locked loop frequency doubling module or the comparator to the time when it outputs a disable signal to the first pump drive of the amplification stage, the second pump drive of the amplification stage, and the third pump drive of the amplification stage, the time does not exceed 5 crystal oscillator clock cycles, and the total time from the seed abnormality of the laser to the shutdown of the pump enables of each stage is within 1 μS, achieving fast protection.

[0020] Compared with the prior art, the present invention has remarkable advantages and beneficial effects, which are specifically reflected in the following aspects:

[0021] The present invention realizes abnormal detection of the mode-locked frequency of the seed, monitoring of the seed optical power, and comparison and output of the amplitude threshold of the optoelectronic signal. The pump drive of the amplification stage can be quickly cut off, and the response time is less than 1 microsecond; rapid abnormal alarm output; greatly improving the response speed when the laser is abnormal. Compared with the traditional power monitoring and protection method, the time is greatly shortened, and the laser is effectively protected; low cost, convenient to use, and easy to integrate and popularize on ultrafast lasers.

[0022] Other features and advantages of the present invention will be described in the subsequent specification, and, in part, will become apparent from the specification, or will be understood by implementing the specific embodiments of the present invention. The objectives and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the written specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 : Schematic diagram of the circuit of the present invention;

[0025] Figure 2 : Schematic diagram of the working timing of the frequency divider;

[0026] Figure 3 : Schematic diagram of the working timing of the enable module;

[0027] Figure 4 : Schematic diagram of the working timing of the alarm monitoring module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present invention provided in the drawings below is not intended to limit the scope of the present invention to be protected, but only represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of the present invention.

[0029] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it will not be further defined or explained in subsequent figures. At the same time, in the description of the present invention, orientation terms, sequence terms, etc. are only used for differentiating descriptions and cannot be construed as indicating or implying relative importance.

[0030] Such as Figure 1As shown, for the fast protection control circuit of an ultrafast laser, the communication interface 1 is connected to the communication terminal of the MCU 2; the reset output port of the MCU 2 is connected to the global reset input terminal of the FPGA 3; the frequency division data output port of the MCU 2 is connected to the input pin of the FPGA 3 and then connected to the input terminal of its frequency divider 302; the enable data output port of the MCU 2 is connected to the input pin of the FPGA 3 and then connected to the input terminal of its enable module 303; the alarm clear output signal port of the MCU 2 is connected to the input pin of the FPGA 3 and then connected to the input terminal of its alarm monitoring module 304; the data output port of the MCU 2 is connected to the input pin of the digital-to-analog converter 5, and the analog-to-digital conversion channel input port of the MCU 2 is connected to the output terminal of the optical power meter module 15; the crystal oscillator 4 is connected to the clock input port of the FPGA 3; the output of the digital-to-analog converter 5 is connected to the input terminal of the comparator 6; the output of the photodetector 13 is connected to the input port of the optical power meter module 15; the output of the photodetector 13 is connected to the input terminal of the comparator 6 and connected to the input terminal of the FPGA 3 and then connected to the input terminal of its phase-locked loop frequency multiplication module 301; the frequency multiplication clock output terminal of the phase-locked loop frequency multiplication module 301 is connected to the input port of the frequency divider 302; the latch output terminal of the phase-locked loop frequency multiplication module 301 is connected to the input terminal of the alarm monitoring module 304; the output port of the comparator 6 is connected to the input pin of the FPGA 3 and then connected to the input port of its alarm monitoring module 304; the output terminal of the frequency divider 302 is connected to the input terminal of the AOM driver 7; the output terminal 1# of the enable module 303 is connected to the input terminal of the seed source pump drive 8; the output terminal 2# of the enable module 303 is connected to the output terminal of the first amplifier stage pump drive 9; the output terminal 3# of the enable module 303 is connected to the output terminal of the second amplifier stage pump drive 10; the output terminal 4# of the enable module 303 is connected to the output terminal of the third amplifier stage pump drive 11; the output terminal of the alarm monitoring module 304 is connected to the input terminal of the enable module 303; the output terminal of the alarm monitoring module 304 is connected to the input port of the MCU 2 and connected to the alarm signal interface 12; the output terminal of the AOM driver 7 is connected to the input terminal 1# of the optical path system 14; the output terminal of the seed source pump drive 8 is connected to the input terminal 2# of the optical path system 14; the output terminal of the first amplifier stage pump drive 9 is connected to the input terminal 3# of the optical path system 14; the output terminal of the second amplifier stage pump drive 10 is connected to the input terminal 4# of the optical path system 14; the output terminal of the third amplifier stage pump drive 11 is connected to the input terminal 5# of the optical path system 14; one output terminal of the optical path system 14 is connected to the input terminal of the photodetector 13; one output terminal of the optical path system 14 is used to output laser light.

[0031] FPGA 3 is a Field Programmable Gate Array (FPGA) of model XC6SLX4 - 2TQG144C. The crystal oscillator 4 is a 20M crystal oscillator. MCU 2 is an MCU of model STM32F103. The digital - to - analog converter 5 is a digital - to - analog converter of model MCP4822T. The comparator 6 is a comparator of model TLV1805. The structure of the optical path system 14 can be seen in the authorized patent (Patent Publication No. CN215452034U). The Field Programmable Gate Array (hereinafter referred to as FPGA) realizes fast timing logic judgment, and the Microcontroller Unit (hereinafter referred to as MCU) realizes the execution of laser application programs and communication with the host computer.

[0032] MCU 2 outputs a 1uS low - level reset signal to FPGA 3, and FPGA 3 resets and clears its respective registers with the clock input from the crystal oscillator 4;

[0033] The host computer sends a laser start instruction to MCU 2 through the communication interface 1. After receiving the instruction, MCU 2 outputs an alarm clearing signal to the alarm monitoring module 304 of FPGA 3, and sends a seed source enabling signal to the enabling module 303 through the enabled data port. The enabling module 303 outputs the seed source enabling signal to the seed source pump driver 8. The seed source pump driver 8 drives the seed pump source to emit laser through the port of the optical path system. At the same time, under the action of the saturable absorber optical device in the optical path system 14, a mode - locked laser pulse of 25M Hz is generated; the mode - locked laser pulse is split by the optical splitter of the optical system 14, and a part of the laser is output from the port, and the rest is pre - amplified and re - amplified by the amplifier stage pump;

[0034] The 25M Hz or 40M HZ pulsed laser output from the port of the optical path system 14 is input to the photodetector 13. The photodetector 13 converts the pulsed optical signal into a pulsed electrical signal and outputs it; the electrical pulse output by the photodetector 13 is input to the optical power meter module 15 for power reading. The structure of the optical power meter module 15 can be seen in the authorized patent (Patent Publication No. CN212059100U). The optical power meter module 15 outputs an analog quantity to MCU 2. The analog - to - digital converter of MCU 2 collects it and calculates the current seed optical power size using the calibration coefficient, and can monitor whether the optical power of the seed is abnormal;

[0035] The stable mode locking of the ultrafast laser seed corresponds to a certain current range of the pump source. Therefore, the electrical pulse signals output from the photodetector 13 at different currents have different amplitudes. The signals are input to the positive input terminal of the comparator 6, and the negative input terminal of the comparator 6 is used to set the threshold voltage. Therefore, when the amplitude of the electrical pulse output from the photodetector 13 is higher than the set threshold voltage, the comparator 6 outputs an electrical pulse signal with a frequency consistent with the seed mode locking frequency. If the amplitude of the electrical pulse output from the photodetector 13 is lower than the set threshold, the comparator 6 outputs a low level; the threshold voltage of the negative input terminal of the comparator 6 is sent by the host computer to the MCU2 through the communication interface 1, and the MCU2 then sends data to the digital-to-analog converter 5 to achieve the output of the analog voltage; during normal operation, the comparator 6 outputs a pulse signal to the alarm monitoring module 304. If the seed power is too low, a low level signal is output to the alarm monitoring module 304;

[0036] The photodetector 13 outputs an electrical pulse frequency signal consistent with the seed mode locking frequency to the phase-locked loop frequency multiplication module 301 of the FPGA 3, multiplies the input frequency by 100 MHz and then outputs it to the frequency divider 302 of the FPGA. After the phase-locked loop frequency multiplication module 301 completes the frequency multiplication, it outputs a latch signal indicating that the synchronous phase locking is completed. Normally, the signal is high level. If the mode locking of the seed source is abnormal during operation, the input frequency of the phase-locked loop frequency multiplication module 301 suddenly becomes abnormal, the phase locking fails, and the latch signal becomes low. The latch signal is directly input to the alarm monitoring module 304;

[0037] Since the laser needs to work at different fundamental frequencies, the corresponding frequencies need to be set; the host computer sends frequency parameters to the MCU2 through the communication interface 1, and the MCU2 converts the frequency parameters into corresponding data and sends it to the frequency divider 302. The frequency divider 302 divides the multiplied clock frequency and then outputs it to the AOM driver 7. The AOM driver 7 outputs and inputs through one end of the optical path system 14 and acts on the AOM to achieve the output of the laser with the corresponding frequency from one end of the output optical path system 14; the working timing of the frequency divider 302 is as Figure 2 shown;

[0038] After receiving the power-on instruction sent by the host computer, the MCU2 not only enables the seed source pump drive, but also enables the pump drive of the power amplification stage. The number of amplification stages depends on the output power requirement. Taking three-stage amplification as an example; the MCU2 sends the enable signals of each stage to the enable module 303 through the enable data line. If the signal at the output terminal of the alarm monitoring module 304 is low, the enable module 303 outputs the enable signals to the first-stage pump driver 9 of the amplification stage, the second-stage pump driver 10 of the amplification stage, and the third-stage pump driver 11 of the amplification stage through the output terminal respectively. The outputs of the first-stage pump driver 9 of the amplification stage, the second-stage pump driver 10 of the amplification stage, and the third-stage pump driver 11 of the amplification stage act on the output light of the amplification stage pump source of the optical path system 14 through the input terminal of the optical path system 14; the working timing of the enable module 303 is asFigure 3 as shown

[0039] The existing traditional laser protection method is to monitor the seed optical power. If it is lower than a certain value, the MCU cuts off the enable of the amplifier stage pump drive. However, the time for the MCU to perform the output process from power monitoring is at least more than 1 mS. If the seed optical power is too low or the mode locking of the seed source is abnormal, the crystal of the optical path system 14 can be damaged within dozens of microseconds. Therefore, the existing traditional method cannot provide fast and timely protection. The present invention uses the latched output of the phase-locked loop frequency doubling module 301 and the output of the comparator 6 as fast and timely alarm signals to act on the alarm monitoring module 304. Since the seed optical frequency is 25 MHz or 40 MHz, the response time of these two signals does not exceed 100 nS. When the alarm monitoring module 304 receives one of the two signals, it immediately shuts off the enables of the amplifier stage pump driver one 9, the amplifier stage pump driver two 10, and the amplifier stage pump driver three 11 to avoid damaging the optical crystal. The alarm monitoring module 304 outputs the alarm signal from the output terminal to the MCU 2 and at the same time outputs it to the external device from the alarm signal interface 12. The time for the alarm monitoring module 304 to output the disable signal to the amplifier stage pump driver one 9, the amplifier stage pump driver two 10, and the amplifier stage pump driver three 11 from receiving the abnormal signal of the phase-locked loop frequency doubling module 301 or the comparator 6 does not exceed 5 crystal oscillator clock cycles. The total time from the laser seed abnormality to the shutdown of the enables of each stage of the pump is within 1 μS, achieving fast protection. The working timing of the alarm monitoring module 304 is as Figure 4 shown

[0040] In summary, the present invention realizes the detection of abnormal seed mode locking frequency, the monitoring of seed optical power, and the comparison output of the amplitude threshold of the optoelectronic signal, quickly cuts off the enable of the amplifier stage pump drive, with a response time of less than 1 microsecond; outputs a fast abnormal alarm; greatly improves the response speed of the laser in case of abnormality. Compared with the traditional power monitoring protection method, the time is greatly shortened, and the laser is effectively protected; it has low cost, is easy to use, and is easy to integrate and popularize on ultrafast lasers.

[0041] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0042] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention.

[0043] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

Claims

1. Fast protection control circuit for an ultrafast laser, characterized in that: The communication interface (1) is connected to the communication terminal of the MCU (2); the reset output port of the MCU (2) is connected to the global reset input terminal of the FPGA (3); the frequency division data output port of the MCU (2) is connected to the input pin of the FPGA (3) and then connected to the input terminal of its frequency divider (302); the enable data output port of the MCU (2) is connected to the input pin of the FPGA (3) and then connected to the input terminal of its enable module (303); the alarm clearing output signal port of the MCU (2) is connected to the input pin of the FPGA (3) and then connected to the input terminal of its alarm monitoring module (304); the data output port of the MCU (2) is connected to the input pin of the digital-to-analog converter (5), and the analog-to-digital conversion channel input port of the MCU (2) is connected to the output terminal of the optical power meter module (15); the crystal oscillator (4) is connected to the clock input port of the FPGA (3). The output of the digital-to-analog converter (5) is connected to the input terminal of the comparator (6); the output of the photodetector (13) is connected to the input port of the optical power meter module (15); the output of the photodetector (13) is connected to the input terminal of the comparator (6) and connected to the input terminal of the FPGA (3) and then connected to the input terminal of its phase-locked loop frequency doubling module (301); the frequency doubling clock output terminal of the phase-locked loop frequency doubling module (301) is connected to the input port of the frequency divider (302); the latch output port of the phase-locked loop frequency doubling module (301) is connected to the input terminal of the alarm monitoring module (304); the output port of the comparator (6) is connected to the input pin of the FPGA (3) and then connected to the input port of its alarm monitoring module (304); the output terminal of the frequency divider (302) is connected to the input terminal of the AOM driver (7); the output terminal 1# of the enable module (303) is connected to the input terminal of the seed source pump drive (8); the output terminal 2# of the enable module (303) is connected to the output terminal of the first amplifier stage pump drive (9); the output terminal 3# of the enable module (303) is connected to the output terminal of the second amplifier stage pump drive (10); the output terminal 4# of the enable module (303) is connected to the output terminal of the third amplifier stage pump drive (11); the output terminal of the alarm monitoring module (304) is connected to the input terminal of the enable module (303); the output terminal of the alarm monitoring module (304) is connected to the input port of the MCU (2) and connected to the alarm signal interface (12); the output terminal of the AOM driver (7) is connected to the input terminal 1# of the optical path system (14); the output terminal of the seed source pump drive (8) is connected to the input terminal 2# of the optical path system (14); the output terminal of the first amplifier stage pump drive (9) is connected to the input terminal 3# of the optical path system (14); the output terminal of the second amplifier stage pump drive (10) is connected to the input terminal 4# of the optical path system (14); the output terminal of the third amplifier stage pump drive (11) is connected to the input terminal 5# of the optical path system (14); one output terminal of the optical path system (14) is connected to the input terminal of the photodetector (13); one output terminal of the optical path system (14) is used to output laser light.

2. The fast protection control circuit of the ultrafast laser according to claim 1, characterized in that: The FPGA (3) is a field programmable gate array FPGA of model XC6SLX4-2TQG144C.

3. The fast protection control circuit of the ultrafast laser according to claim 1, wherein: The crystal oscillator (4) is a 20M crystal oscillator.

4. The fast protection control circuit of the ultrafast laser according to claim 1, characterized in that: The MCU (2) is an MCU of model STM32F103.

5. The fast protection control circuit of the ultrafast laser according to claim 1, characterized in that: The digital-to-analog converter (5) is a digital-to-analog converter of model MCP4822T.

6. The fast protection control circuit of the ultrafast laser according to claim 1, characterized in that: The comparator (6) is a comparator of model TLV1805.

7. The rapid protection control method for an ultrafast laser implemented by the circuit according to claim 1, characterized in that: The MCU (2) outputs a low-level reset signal to the FPGA (3), and the FPGA (3) resets and clears its registers with the clock input from the crystal oscillator (4). The host computer sends a laser enabling instruction to the MCU (2) through the communication interface (1). After receiving the instruction, the MCU (2) outputs an alarm clearing signal to the alarm monitoring module (304) of the FPGA (3), and sends a seed source enabling signal to the enabling module (303) through the enabling data port. The enabling module (303) outputs the seed source enabling signal to the seed source pump drive (8). The seed source pump drive (8) drives the seed pump source to emit laser through the port of the optical path system, and at the same time generates mode-locked laser pulses under the action of the saturable absorber optical device in the optical path system (14). The mode-locked laser pulses are split by the beam splitter of the optical system (14), and a part of the laser is output from the port, and the rest is pre-amplified and re-amplified by the amplifier stage pump. The pulsed laser output from the port of the optical path system (14) is input to the photodetector (13). The photodetector (13) converts the pulsed optical signal into a pulsed electrical signal and outputs it. The electrical pulse output by the photodetector (13) is input to the optical power meter module (15) for power reading. The optical power meter module (15) outputs an analog quantity to the MCU (2). The analog-to-digital converter of the MCU (2) collects it and calculates the current seed optical power using the calibration coefficient, and can monitor whether the optical power of the seed is abnormal. The stable mode locking of the ultrafast laser seed corresponds to a certain current range of the pump source. Therefore, different currents have different amplitudes of the electrical pulse signals output from the photodetector (13). The signal is input to the positive input terminal of the comparator (6). The negative input terminal of the comparator (6) is used to set the threshold voltage. Therefore, when the amplitude of the electrical pulse output by the photodetector (13) is higher than the set threshold voltage, the comparator (6) outputs an electrical pulse signal with a frequency consistent with the seed mode-locking frequency. If the amplitude of the electrical pulse output by the photodetector (13) is lower than the set threshold, the comparator (6) outputs a low level. The threshold voltage of the negative input terminal of the comparator (6) is achieved by the host computer sending an instruction to the MCU (2) through the communication interface (1), and the MCU (2) then sends data to the digital-to-analog converter (5) to output an analog voltage. During normal operation, the comparator (6) outputs a pulsed signal to the alarm monitoring module (304). If the seed power is too low, it outputs a low-level signal to the alarm monitoring module (304). The photodetector (13) outputs an electrical pulse frequency signal consistent with the seed mode-locking frequency to the phase-locked loop frequency doubling module (301) of the FPGA (3). After doubling the input frequency to 100 MHz, it is output to the frequency divider (302) of the FPGA. The phase-locked loop frequency doubling module (301) outputs a latch signal after completing the frequency doubling, indicating that the synchronous phase-locking is completed. Normally, the signal is at a high level. If the seed source mode-locking is abnormal during operation, the input frequency of the phase-locked loop frequency doubling module (301) suddenly becomes abnormal, the phase-locking fails, and the latch signal becomes low. The latch signal is directly input to the alarm monitoring module (304); Since the laser needs to operate at different fundamental frequencies, corresponding frequencies need to be set. The host computer sends frequency parameters to the MCU (2) through the communication interface (1). The MCU (2) converts the frequency parameters into corresponding data and sends it to the frequency divider (302). The frequency divider (302) divides the frequency-doubled clock and outputs it to the AOM driver (7). After the AOM driver (7) outputs, it is input through one end of the optical path system (14) and acts on the AOM, enabling the laser of the corresponding frequency to be output from one end of the output optical path system (14); After receiving the power-on instruction sent from the host computer, the MCU (2) not only enables the seed source pump drive but also enables the pump drive of the power amplification stage. The number of amplification stages depends on the output power requirement. The MCU (2) sends enable signals for each stage to the enable module (303) through the enable data line. If the signal at the output end of the alarm monitoring module (304) is low, the enable module (303) outputs enable signals to the first amplification stage pump driver (9), the second amplification stage pump driver (10), and the third amplification stage pump driver (11) respectively through the output end. The outputs of the first amplification stage pump driver (9), the second amplification stage pump driver (10), and the third amplification stage pump driver (11) act on the light output of the amplification stage pump source of the optical path system (14) through the input end of the optical path system (14).

8. The fast protection control method of the ultrafast laser according to claim 7, characterized in that: The latched output of the phase-locked loop frequency multiplication module (301) and the output of the comparator (6) are used as fast and timely alarm signals to act on the alarm monitoring module (304). Since the seed light frequency is 25 MHz or 40 MHz, the response time of these two signals does not exceed 100 nS. When the alarm monitoring module (304) receives one of the two signals, it immediately shuts off the enables of the amplifier stage pump driver one (9), the amplifier stage pump driver two (10), and the amplifier stage pump driver three (11) to avoid damaging the optical crystal. The alarm monitoring module (304) outputs the alarm signal from the output terminal to the MCU (2) and simultaneously outputs it to the external device from the alarm signal interface (12). The time from when the alarm monitoring module (304) receives the abnormal signal from the phase-locked loop frequency multiplication module (301) or the comparator (6) to when it outputs the disable signal to the amplifier stage pump driver one (9), the amplifier stage pump driver two (10), and the amplifier stage pump driver three (11) does not exceed 5 crystal oscillator clock cycles. The total time from the laser seed abnormality to the shutdown of the enables of each stage of the pump is within 1 μS, achieving fast protection.

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