Hysteresis comparator and chip based on op amp

Abstract

The present application provides a hysteresis comparator and chip based on an op amp. The hysteresis comparator is used to compare a first voltage and a second voltage. The hysteresis comparator includes: an input stage and an amplifier stage. The input stage includes: a first input branch that generates a first current based on the first voltage and a second input branch that generates a second current based on the second voltage. The first input branch includes N connected sub-input branches, or the second input branch includes M connected sub-input branches, N is determined by a first selection signal, and M is determined by a second selection signal. The first current and the second current are respectively connected to the first input terminal and the second input terminal of the amplifier stage. When the first current is greater than the second current, the output terminal of the amplifier stage outputs a first level, and when the first current is less than the second current, the output terminal outputs a second level. The present application reduces the instability caused by positive feedback and reduces the layout area and power consumption of the hysteresis comparator by changing the way the hysteresis voltage is generated.

Description

[0001] This application is a divisional application of Chinese patent application 202211099992.9 entitled “Hysteresis comparator and chip based on op amp” filed on September 9, 2022. Technical Field

[0002] The present invention relates to the technical field of electronic circuits, and in particular to a hysteresis comparator and a chip based on an operational amplifier. Background Art

[0003] Conventional comparators take an analog input voltage and a reference voltage as input and output a binary digital signal, typically high or low. These comparators can be used as interface circuits between analog and digital circuits. However, these comparators are significantly affected by noise near the threshold. Hysteresis comparators, however, introduce positive feedback, creating a "hysteresis" characteristic near the threshold. Hysteresis comparators typically exhibit hysteresis near the threshold, and the voltage range of this hysteresis is called the hysteresis window. Compared to conventional comparators, hysteresis comparators have stronger noise immunity. However, they also suffer from circuit instability and excessive layout area. Summary of the Invention

[0004] The embodiments of the present application relate to a hysteresis comparator and chip based on an operational amplifier, which partially or completely solve the above-mentioned technical problems by changing the hysteresis voltage generation method of the hysteresis comparator.

[0005] According to a first aspect of the present application, a hysteresis comparator based on an operational amplifier is provided, wherein the hysteresis comparator is used to compare a first voltage and a second voltage, the hysteresis comparator comprising: an input stage, and an amplifier stage connected to the input stage, the input stage comprising: a first input branch and a second input branch, the first input branch generating a first current based on the first voltage, the second input branch generating a second current based on the second voltage, the first input branch comprising N connected sub-input branches, wherein N is determined by a first selection signal, and if N is greater than or equal to 2, the N sub-input branches are connected in parallel, the second input branch comprising M connected sub-input branches, wherein M is determined by a second selection signal, and if M is greater than or equal to 2, the M sub-input branches are connected in parallel, and M and N are positive integers. number, at least one of M and N is greater than or equal to 2, the amplifier stage includes: a first input terminal, a second input terminal, and an output terminal, the first current and the second current are connected to the first input terminal and the second input terminal respectively, when the first current is greater than the second current, the output terminal outputs a first level, when the first current is less than the second current, the output terminal outputs a second level, the first level and the second level are respectively a high level and a low level. If N is a positive integer greater than or equal to 2, the hysteresis comparator provides a negative hysteresis window, and the input transistors of each sub-input branch of the N sub-input branches have different width-to-length ratios; if M is a positive integer greater than or equal to 2, the hysteresis comparator provides a positive hysteresis window, and the input transistors of each sub-input branch of the M sub-input branches have different width-to-length ratios.

[0006] According to a second aspect of the present application, a chip is provided, comprising the above-mentioned hysteresis comparator.

[0007] The input stage of the hysteresis comparator of the embodiment of the present application includes: a first input branch and a second input branch, the first input branch includes N connected sub-input branches, N is determined by a first selection signal, the second input branch includes M connected sub-input branches, M is determined by a second selection signal, and at least one of M and N is greater than or equal to 2, thereby being able to generate a hysteresis voltage by changing the number of sub-input branches of the first input branch and / or the second input branch of the input stage of the operational amplifier, thereby changing the effective width-to-length ratio of the first input branch and / or the second input branch to provide a negative hysteresis window and / or a positive hysteresis window. The embodiment of the present application reduces the instability caused by positive feedback, uses a small number of transistors, and reduces the layout area and power consumption of the hysteresis comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a schematic circuit diagram of a hysteresis comparator in the related art.

[0010] Figure 2 FIG. 4 is a schematic circuit diagram of another hysteresis comparator in the related art.

[0011] Figure 3 This is a typical circuit diagram of an operational amplifier.

[0012] Figure 4 4 is a schematic block diagram of a hysteresis comparator according to an embodiment of the present application.

[0013] Figure 5 An output characteristic of the hysteresis comparator according to an embodiment of the present application is shown.

[0014] Figure 6 Another output characteristic of the hysteresis comparator according to an embodiment of the present application is shown.

[0015] Figure 7 Another output characteristic of the hysteresis comparator according to an embodiment of the present application is shown.

[0016] Figure 8 A circuit diagram of a hysteresis comparator according to an embodiment of the present application is shown.

[0017] Figure 9 The circuit for generating the first selection signal and the second selection signal is shown.

[0018] Figure 10 A switch implementation is shown.

[0019] Figure 11 Shown Figure 8 The waveform diagram of the hysteresis comparator is shown in FIG.

[0020] Figure 12 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown.

[0021] Figure 13 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown.

[0022] Figure 14 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown.

[0023] Figure 15 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown.

[0024] Figure 16 A schematic block diagram of a chip according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] To help those skilled in the art better understand the present invention, the following will provide a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings. Obviously, the described embodiments are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0026] Figure 1 A hysteresis comparator of related art is shown. The hysteresis comparator includes transistors M0-M9 and a current source IBIAS. When the input voltage VIN is greater than the reference voltage Vref, most of the bias current provided by the current source IBIAS flows through transistor M0, with only a very small portion, or even no current, flowing through transistor M1. In this case, the output signal VOUT is low. As VIN changes from high to low, the current flowing through transistors M1 and M3 gradually increases. When the current flowing through transistors M1 and M3 equals the current flowing through transistors M0 and M2, the output signal VOUT flips. Figure 1 The hysteresis comparator shown uses transistors M2 and M3 to generate positive feedback to achieve hysteresis. In order to ensure the stability of the circuit, negative feedback is usually present in the circuit. If positive feedback also exists in the circuit, the strength of the negative feedback must be greater than the strength of the positive feedback. This is the basic principle of circuit design. Therefore, Figure 1 The positive feedback generated by transistors M2 and M3 in the circuit introduces an instability factor into the circuit.

[0027] Figure 2 Another hysteresis comparator of the related art is shown, which realizes the hysteresis function by forming a positive feedback form through an external resistor. Figure 2 The hysteresis comparator shown includes a comparator COMP, a resistor Ra, and a resistor Rb. Figure 2 The hysteresis comparator shown uses a positive feedback path added externally to the op amp. In addition to the potential risk of circuit instability caused by positive feedback, Figure 2 The hysteresis comparator occupies a large area.

[0028] It can be seen from this that how to change the way the hysteresis voltage is generated to obtain good output characteristics is a problem that needs to be solved urgently by those skilled in the art. The present application proposes a hysteresis comparator based on an operational amplifier, which changes the number of sub-input branches of the first input branch and / or the second input branch of the input stage, thereby changing the effective width-to-length ratio of the first input branch and / or the second input branch to provide a negative hysteresis window and / or a positive hysteresis window to generate a hysteresis voltage. The embodiment of the present application reduces the instability caused by positive feedback. In addition, the number of transistors used in the embodiment of the present application is small, which reduces the layout area and power consumption of the hysteresis comparator.

[0029] Figure 3 This is a typical circuit diagram of an operational amplifier (op amp for short). Figure 3 The operational amplifier includes PMOS transistors M10 and M11, and NMOS transistors M12, M13, and M14. PMOS transistor M10 and NMOS transistor M12 are connected in series. PMOS transistor M11 and NMOS transistor M13 are connected in series. PMOS transistors M10 and M11 form a current mirror. The sources of NMOS transistors M12 and M13 are connected to the drain of NMOS transistor M14. The gate of NMOS transistor M14 receives a bias voltage VBIAS, providing a bias current. The gate of NMOS transistor M12 receives an input voltage VIN, and the gate of NMOS transistor M13 receives a reference voltage Vref. NMOS transistors M12 and M13 have the same width-to-length ratio, and PMOS transistors M10 and M11 have the same width-to-length ratio. The current of NMOS transistor M12 is copied to PMOS transistor M11 via the current mirror. When the input voltage VIN is greater than the reference voltage Vref, the current of NMOS transistor M12 is greater than the current of NMOS transistor M13, and the output voltage Vout is high. When the input voltage VIN is lower than the reference voltage Vref, the current of the NMOS transistor M12 is lower than the current of the NMOS transistor M13 , and the output voltage Vout is at a low level.

[0030] If the aspect ratio of the NMOS transistor M12 is not equal to that of the NMOS transistor M13, the flipping point of the output voltage Vout is no longer when the input voltage VIN equals the reference voltage Vref. If the aspect ratio of the NMOS transistor M12 is greater than that of the NMOS transistor M13, the output voltage Vout becomes high when the input voltage VIN exceeds the first flipping voltage, and the first flipping voltage is less than the reference voltage Vref. If the aspect ratio of the NMOS transistor M12 is less than that of the NMOS transistor M13, the output voltage Vout becomes high only when the input voltage VIN exceeds the second flipping voltage, and the first flipping voltage is greater than the reference voltage Vref. However, after the NMOS transistors M12 and M13 are manufactured, the aspect ratio cannot be changed, and the first flipping voltage and the second flipping voltage cannot be changed.

[0031] The present application provides a hysteresis comparator based on an op amp. The hysteresis comparator can be based on any type of op amp, such as Figure 3 The operational amplifier shown, an operational amplifier with multiple amplifier stages, a cascode operational amplifier, and a folded cascode operational amplifier. A hysteresis comparator is used to compare a first voltage with a second voltage. Specifically, the hysteresis comparator is used to perform a hysteresis comparison on the first voltage and the second voltage. The hysteresis comparator includes an input stage and an amplifier stage connected to the input stage. The input stage includes: a first input branch and a second input branch, the first input branch generating a first current based on the first voltage, and the second input branch generating a second current based on the second voltage. The first input branch includes N connected sub-input branches, and if N is greater than or equal to 2, the N sub-input branches are connected in parallel. The second input branch includes M connected sub-input branches, and if M is greater than or equal to 2, the M sub-input branches are connected in parallel. N is determined by a first selection signal, and M is determined by a second selection signal. M and N are positive integers, and at least one of M and N is greater than or equal to 2. The amplifier stage includes: a first input terminal and a second input terminal, the first current and the second current are connected to the first input terminal and the second input terminal, respectively. When the first current is greater than the second current, the output terminal outputs a first level, and when the first current is less than the second current, the output terminal outputs a second level. The first level and the second level are high and low levels, respectively. That is, when the first level is high, the second level is low; when the first level is low, the second level is high.

[0032] The first input branch includes N connected sub-input branches, and the second input branch includes M connected sub-input branches. The number of M and / or N is changed by the first selection signal and / or the second selection signal to change the number of sub-input branches of the first input branch and / or the second input branch of the input stage, thereby changing the effective width-to-length ratio of the first input branch and / or the second input branch to provide a negative hysteresis window and / or a positive hysteresis window to generate a hysteresis voltage. Compared to Figure 1 and Figure 2 The hysteresis comparator adopts positive feedback to realize hysteresis. The embodiment of the present application reduces the instability caused by positive feedback. Figure 1 and Figure 2 The hysteresis comparator of the present application uses a small number of transistors, which reduces the layout area and power consumption.

[0033] If N is a positive integer greater than or equal to 2, the hysteresis comparator provides a negative hysteresis window; if M is a positive integer greater than or equal to 2, the hysteresis comparator provides a positive hysteresis window.

[0034] Figure 4 is a schematic block diagram of a hysteresis comparator according to an embodiment of the present application. The hysteresis comparator 10 receives a first voltage VIN and a second voltage Vref, as well as a first enable signal n_hys_en and a second enable signal p_hys_en. The first voltage VIN and the second voltage Vref are analog signals. The first enable signal n_hys_en and the second enable signal p_hys_en are digital signals. The hysteresis comparator 10 is configured to compare the magnitudes of the first voltage VIN and the second voltage Vref. The hysteresis comparator 10 outputs a binary digital signal of a high or low level. For example, the hysteresis comparator 10 outputs a high level indicating a "1" or a low level indicating a "0". The first enable signal n_hys_en and the second enable signal p_hys_en are used to set the hysteresis mode of the hysteresis comparator 10. The hysteresis comparator 10 can have three hysteresis modes: a first hysteresis mode, a second hysteresis mode, and a third hysteresis mode. In the first hysteresis mode, the hysteresis comparator 10 has a positive hysteresis window and a negative hysteresis window. In the second hysteresis mode, the hysteresis comparator 10 has a negative hysteresis window. In the third hysteresis mode, the hysteresis comparator 10 has a positive hysteresis window. In some embodiments, the hysteresis comparator 10 may also have one or two of the first hysteresis mode, the second hysteresis mode, and the third hysteresis mode. Figure 4For example, the hysteresis comparator 10 has three hysteresis modes. The first enable signal n_hys_en and the second enable signal p_hys_en are used to select the hysteresis mode of the hysteresis comparator 10. For example, when the first enable signal n_hys_en is at a high level, the negative hysteresis window is enabled, selecting the second hysteresis mode; when the second enable signal p_hys_en is at a high level, the positive hysteresis window is enabled, selecting the third hysteresis mode; and when both the first enable signal n_hys_en and the second enable signal p_hys_en are at high levels, both the positive and negative hysteresis windows are enabled, selecting the first hysteresis mode.

[0035] Figure 5 The output characteristics of the hysteresis comparator in the first hysteresis mode are shown. The hysteresis comparator 10 has a positive hysteresis window and a negative hysteresis window. Take the second voltage Vref as an example of a voltage of fixed size. The first voltage VIN starts to increase from a voltage less than the second voltage Vref. When the first voltage VIN is less than the second voltage Vref, the hysteresis comparator 10 outputs a low level indicating 0. When the first voltage VIN increases to the second voltage Vref, the output signal of the hysteresis comparator 10 does not flip (that is, the output signal changes between high and low levels). When the first voltage VIN increases to the second voltage Vref plus the hysteresis voltage Vhsy1, the output signal of the hysteresis comparator 10 flips. When the first voltage VIN is greater than the second voltage Vref plus the hysteresis voltage Vhsy1, the hysteresis comparator 10 outputs a high level indicating 1. As shown Figure 5 As shown, the positive hysteresis window is (Vref, Vref+Vhsy1), that is, the hysteresis window during the increase of the first voltage VIN.

[0036] The first voltage VIN decreases from a voltage greater than the second voltage Vref. When the first voltage VIN is greater than the second voltage Vref, the hysteresis comparator 10 outputs a high level indicating 1. When the first voltage VIN is equal to the second voltage Vref, the output signal of the hysteresis comparator 10 does not flip. When the first voltage VIN is equal to the second voltage Vref minus the hysteresis voltage Vhsy2, the output signal of the hysteresis comparator 10 flips. When the first voltage VIN is less than the second voltage Vref minus the hysteresis voltage Vhsy2, the hysteresis comparator 10 outputs a low level indicating 0. Figure 5 As shown, the negative hysteresis window is (Vref-Vhsy2, Vref), that is, the hysteresis window during the decrease of the first voltage VIN. The hysteresis voltage Vhsy1 and the hysteresis voltage Vhsy2 can be the same or different.

[0037] Figure 6The output characteristics of the hysteresis comparator in the second hysteresis mode are shown. The hysteresis comparator 10 has a negative hysteresis window. For example, the second voltage Vref is a fixed voltage. The first voltage VIN increases from a voltage value less than the second voltage Vref. When the first voltage VIN equals the second voltage Vref, the output signal of the hysteresis comparator 10 flips. The first voltage VIN decreases from a voltage value greater than the second voltage Vref. When the first voltage VIN is greater than the second voltage Vref, the hysteresis comparator 10 outputs a high level indicating a 1. When the first voltage VIN is equal to the second voltage Vref, the output signal of the hysteresis comparator 10 does not flip. When the first voltage VIN equals the second voltage Vref minus the hysteresis voltage Vhsy4, the output signal of the hysteresis comparator 10 flips. When the first voltage VIN is less than the second voltage Vref minus the hysteresis voltage Vhsy4, the hysteresis comparator 10 outputs a low level indicating a 0.

[0038] Figure 7 The output characteristics of the hysteresis comparator in the third hysteresis mode of an embodiment of the present application are shown. The hysteresis comparator 10 has a positive hysteresis window. For example, the second voltage Vref is a fixed voltage. The first voltage VIN increases from a voltage value less than the second voltage Vref. When the first voltage VIN is less than the second voltage Vref, the hysteresis comparator 10 outputs a low level indicating a 0. When the first voltage VIN equals the second voltage Vref, the output signal of the hysteresis comparator 10 does not flip. When the first voltage VIN equals the second voltage Vref plus the hysteresis voltage Vhsy3, the output signal of the hysteresis comparator 10 flips. When the first voltage VIN is greater than the second voltage Vref plus the hysteresis voltage Vhsy3, the hysteresis comparator 10 outputs a high level indicating a 1. The first voltage VIN decreases from a voltage value greater than the second voltage Vref. When the first voltage VIN is greater than the second voltage Vref, the hysteresis comparator 10 outputs a high level indicating a 1. When the first voltage VIN equals the second voltage Vref, the output signal of the hysteresis comparator 10 flips. When the first voltage VIN is lower than the second voltage Vref, the hysteresis comparator 10 outputs a low level indicating 0.

[0039] The implementation of the hysteresis comparator 10 is described below with reference to an embodiment.

[0040] Figure 8 FIG. 1 shows a circuit diagram of a hysteresis comparator according to an embodiment of the present application. Figure 8As shown, hysteresis comparator 110 includes an input stage and an amplifier stage. The input stage includes a current source Iref, NMOS transistors N1-N4, and first switches S1-S4. Current source Iref is provided between node node1 and ground to provide a bias current (also known as a tail current). A first input branch is provided between node node1 and node node2. A second input branch is provided between node node1 and node node3.

[0041] The first input branch includes a first sub-input branch and a second sub-input branch. The first sub-input branch includes a first input transistor (NMOS transistor N3). The gate of the first input transistor (NMOS transistor N3) selects to receive one of the first voltage VIN and the shutdown voltage based on the first selection signal. When the gate of the first input transistor (NMOS transistor N3) receives the first voltage VIN, the first sub-input branch is connected in parallel with the second sub-input branch. When the gate of the first input transistor (NMOS transistor N3) receives the shutdown voltage, the first sub-input branch is disconnected from the other sub-input branches in the first input branch. The second sub-input branch in the first input branch includes a second input transistor (NMOS transistor N1). The gate of the second input transistor (NMOS transistor N1) receives the first voltage. The drain of the second input transistor (NMOS transistor N1) is connected to node node2, the source of the second input transistor (NMOS transistor N1) is connected to node node1, and the gate of the second input transistor (NMOS transistor N1) receives the first voltage VIN. The second input transistor (NMOS transistor N1) generates a current based on the first voltage VIN.

[0042] Specifically, the first sub-input branch includes a first input transistor NMOS transistor N3 , and first switches S1 and S2 .

[0043] The drain of the first input transistor (NMOS transistor) N3 is connected to node node2, the source of the first input transistor (NMOS transistor) N3 is connected to node node1, and the gate of the first input transistor (NMOS transistor) N3 is connected to the first end of the first switch (S1) and the first end of the second switch (S2). The second end of the first switch (S1) is connected to a terminal providing a shutdown voltage. The shutdown voltage of the first input transistor (NMOS transistor) is ground level (GND). The second end of the second switch (S2) is connected to a terminal providing a first voltage (VIN). The on and off states of the first switches (S1) and (S2) are controlled by a first selection signal (n_hys).

[0044] For example, when the first selection signal n_hys is at a high level, the first switch S1 is turned off and the second switch S2 is turned on. When the first selection signal n_hys is at a low level, the first switch S1 is turned on and the second switch S2 is turned off. When the first switch S1 is turned off and the second switch S2 is turned on, the gate of the first input transistor NMOS transistor N3 receives the first voltage VIN, and the first input transistor NMOS transistor N3 generates a current based on the first voltage VIN. The first sub-input branch and the second sub-input branch are connected in parallel, and the first input branch includes two sub-input branches connected in parallel. When the first switch S1 is turned on and the second switch S2 is turned off, the gate of the NMOS transistor N3 receives the off voltage, and the NMOS transistor N3 is turned off. The first sub-input branch is disconnected from the second sub-input branch, and the first input branch includes one sub-input branch, namely, the second sub-input branch.

[0045] The second input transistor NMOS transistor N1 and the first input transistor NMOS transistor N3 may have the same width-to-length ratio or different width-to-length ratios.

[0046] The second input branch includes a third sub-input branch and a fourth sub-input branch. The fourth sub-input branch in the second input branch includes a fourth input transistor NMOS transistor N4. The gate of the fourth input transistor NMOS transistor N4 selects to receive one of the second voltage Vref and the shutdown voltage based on the second selection signal. When the gate of the fourth input transistor NMOS transistor N4 receives the second voltage Vref, the fourth sub-input branch is connected in parallel with the third sub-input branch. When the gate of the fourth input transistor NMOS transistor N4 receives the shutdown voltage, the fourth sub-input branch is disconnected from the third sub-input branch. The third sub-input branch includes a third input transistor NMOS transistor N2. The gate of the third input transistor NMOS transistor N2 receives the second voltage. The drain of the third input transistor NMOS transistor N2 is connected to node node3, the source of the third input transistor NMOS transistor N2 is connected to node node1, and the gate of the third input transistor NMOS transistor N2 receives the second voltage Vref.

[0047] Specifically, the fourth sub-input branch includes a fourth input transistor (NMOS transistor N4), and third switches S3 and S4. The drain of the fourth input transistor (NMOS transistor N4) is connected to node node3, the source of the fourth input transistor (NMOS transistor N4) is connected to node node1, and the gate of the fourth input transistor (NMOS transistor N4) is connected to a first end of the third switch S3 and a first end of the fourth switch S4. The second end of the third switch S3 is connected to a terminal providing a shutdown voltage. The second end of the fourth switch S4 is connected to a terminal providing a second voltage Vref. The turning on and off of the third switches S3 and S4 is controlled by a second selection signal (p_hys).

[0048] For example, when the second selection signal p_hys is at a high level, the third switch S3 is disconnected and the fourth switch S4 is connected. When the second selection signal p_hys is at a low level, the third switch S3 is connected and the fourth switch S4 is disconnected. When the third switch S3 is disconnected and the fourth switch S4 is connected, the gate of the fourth input transistor NMOS transistor N4 receives the second voltage Vref, the third sub-input branch and the fourth sub-input branch are connected in parallel, and the second input branch includes two sub-input branches connected in parallel. When the third switch S3 is connected and the fourth switch S4 is disconnected, the gate of the fourth input transistor NMOS transistor N4 receives the off voltage, the fourth input transistor NMOS transistor N4 is disconnected from the third sub-input branch, and the second input branch includes one sub-input branch, namely, the third sub-input branch.

[0049] The third input transistor NMOS transistor N2 and the fourth input transistor NMOS transistor N4 may have the same width-to-length ratio or different width-to-length ratios.

[0050] The current In of the first input branch depends on the magnitude of the first voltage VIN and the number of sub-input branches in the first input branch. The current Ip of the second input branch depends on the magnitude of the second voltage Vref and the number of sub-input branches in the second input branch.

[0051] Specifically, the second switch S2 and the fourth switch S4 are preferably transmission gates. Figure 10The circuit diagram of the second switch S2 implemented using a transmission gate is shown. The fourth switch S4 is identical to the second switch S2 and will not be further described. The second switch S2 includes a PMOS transistor PS2 and an NMOS transistor NS2 connected in parallel. The drains of the PMOS transistor PS2 and the NMOS transistor NS2 are connected in parallel to receive the first voltage or the second voltage, and the sources of the PMOS transistor PS2 and the NMOS transistor NS2 are connected in parallel to the gate of the first input transistor or the fourth input transistor. The gate of the NMOS transistor NS2 receives the first selection signal n_hys, and the gate of the PMOS transistor PS2 receives the inverted version of the first selection signal n_hys. For example, the first selection signal n_hys is provided to the gate of the PMOS transistor PS2 via inverter 104. Implementing the second switch S2 using a transmission gate ensures that the first voltage VIN is transmitted to the gate of the NMOS transistor N3, preventing voltage loss across the second switch S2 and ensuring that the gates of the NMOS transistors N1 and N3 receive the same first voltage. The first switch S1 and the third switch S3 are used to transmit the ground level GND. Either a transmission gate or an NMOS transistor can be used.

[0052] The amplifier stage includes PMOS transistors P21-P24 and NMOS transistors N21-N24. PMOS transistors P21 and P23 and NMOS transistors N21 and N23 are connected in series between the power supply and ground, respectively. PMOS transistors P22 and P24 and NMOS transistors N22 and N24 are connected in series between the power supply and ground, respectively. The gates of PMOS transistors P21 and P22 receive a bias voltage Vbp1. PMOS transistors P21 and P22 generate currents I1 and I2, respectively. The gates of PMOS transistors P23 and P24 receive a bias voltage Vbp2. The gates of NMOS transistors N21 and N22 receive a bias voltage Vbn1. The gates of NMOS transistors N23 and N24 are both connected to the drain of NMOS transistor 21. The drain of PMOS transistor P21 and the source of PMOS transistor P23 are connected to node node2. The drain of PMOS transistor P22 and the source of PMOS transistor P24 are connected to node node3. The drain of the PMOS transistor P24 is connected to the drain of the NMOS transistor N22 and serves as the output terminal of the hysteresis comparator 100 .

[0053] In the amplifier stage, the current flowing through NMOS transistors N21 and N23 is equal to I1-In. Current I1-In is replicated to NMOS transistors N22 and N24 by a current mirror formed by NMOS transistors N23 and N24. The current flowing through PMOS transistor P24 is I2-Ip. Current I1-In and current I2-Ip determine whether the output voltage of hysteresis comparator 100 is high or low. Since PMOS transistors P21 and P22 have the same width-to-length ratio, I1 equals I2. In other words, whether the output voltage of hysteresis comparator 100 is high or low depends on current In in the first input branch and current Ip in the second input branch. When current I1-In is greater than current I2-Ip, the output voltage Vout of hysteresis comparator 100 is low. When current I1-In is less than current I2-Ip, the output voltage Vout of hysteresis comparator 100 is high.

[0054] Figure 9 The figure shows a circuit for generating a first selection signal n_hys and a second selection signal p_hys. The first selection signal n_hys is generated by an AND gate 101 based on a first enable signal n_hys_en and the output of a hysteresis comparator 100. The two inputs of the AND gate 101 are connected to the first enable signal n_hys_en and the output of the hysteresis comparator 100, respectively. The second selection signal p_hys is generated by an AND gate 102 and an inverter 103 based on the second enable signal p_hys_en and the output of the hysteresis comparator 100. The input of the inverter 103 is connected to the second enable signal p_hys_en, and the two inputs of the AND gate 102 are connected to the output of the inverter 103 and the output of the hysteresis comparator 100, respectively. When the hysteresis mode of the hysteresis comparator 100 is selected, the first enable signal n_hys_en and the second enable signal p_hys_en remain unchanged, and the first selection signal n_hys and the second selection signal p_hys change with the output voltage Vout of the hysteresis comparator 100 . Therefore, the circuit for generating the first selection signal n_hys and the second selection signal p_hys serves as a feedback path of the hysteresis comparator 100 .

[0055] The output voltage Vout of the hysteresis comparator 100 is provided as a feedback signal to the circuit that generates the first selection signal n_hys and the second selection signal p_hys. A Schmitt trigger is provided at the output of the amplifier stage, with the input of the Schmitt trigger connected to the output of the amplifier stage. The output of the Schmitt trigger serves as the output Vout of the hysteresis comparator 100, stabilizing the output of the hysteresis comparator 100 and preventing repeated glitches between 0 and 1. Vout, output from the Schmitt trigger, is provided as a feedback signal to the circuit that generates the first selection signal n_hys and the second selection signal p_hys, resulting in a more stable Vout.

[0056] Figure 11 Shown Figure 8 The waveform diagram of the hysteresis comparator is shown below. Figure 8 、 Figure 9 and Figure 11 The operation of the hysteresis comparator is described below. For example, the second input transistor NMOS transistor N1 and the third input transistor NMOS transistor N2 have the same width-to-length ratio. When both the first enable signal n_hys_en and the second enable signal p_hys_en are high, the hysteresis comparator 100 can provide a positive hysteresis window and a negative hysteresis window. The second voltage Vref has a fixed voltage. The first voltage VIN increases from a voltage VL less than the second voltage Vref to a voltage VH greater than the second voltage Vref, and then decreases from VH to VL.

[0057] If the first enable signal n_hys_en enables the negative hysteresis window and the output level of the hysteresis comparator is low, the first selection signal is low, and if the output level of the hysteresis comparator is high, the first selection signal is high; if the second enable signal p_hys_en enables the positive hysteresis window and the output level of the hysteresis comparator is low, the second selection signal is high, and if the output level of the hysteresis comparator is high, the second selection signal is low.

[0058] In the initial stage, the first voltage VIN is lower than the second voltage Vref. Figure 9 As shown, the first selection signal n_hys is 0, the second selection signal p_hys is 1, the second switches S2 and S3 are off, and the first switches S1 and S4 are on. The gate of the first input transistor NMOS transistor N3 is connected to the off voltage, and the first input transistor NMOS transistor N3 is off. The gate of the fourth input transistor NMOS transistor N4 is connected to the second voltage Vref. The current In of the first input branch is equal to the current of the second input transistor NMOS transistor N1. The current Ip of the second input branch is equal to the current of the third input transistor NMOS transistor N2 and the current of the fourth input transistor NMOS transistor N4. The current of the second input transistor NMOS transistor N1 depends on the magnitude of the first voltage VIN, the current of the third input transistor NMOS transistor N2 depends on the magnitude of the second voltage Vref, and the current of the fourth input transistor NMOS transistor N4 depends on the magnitude of the second voltage Vref. If the current In of the first input branch is less than the current Ip of the second input branch, the hysteresis comparator 100 outputs a low level.

[0059] When the first voltage VIN is equal to the second voltage Vref, the current In of the first input branch is still smaller than the current Ip of the second input branch, and the output voltage Vout of the hysteresis comparator 100 remains at a low level.

[0060] When the first voltage VIN is equal to the second voltage Vref plus the hysteresis voltage Vhsy1 , the current In of the first input branch is equal to the current Ip of the second input branch, and the output voltage Vout of the hysteresis comparator 100 flips.

[0061] When the first voltage VIN is greater than the second voltage Vref plus the hysteresis voltage Vhsy1, the output voltage Vout of the hysteresis comparator 100 is high, the first selection signal n_hys is 1, the second selection signal p_hys is 0, the second switches S2 and S3 are turned on, and the first switches S1 and S4 are turned off. The gate of the first input transistor NMOS transistor N3 is connected to the first voltage VIN, and the current In of the first input branch is equal to the current of the second input transistor NMOS transistor N1 and the current of the first input transistor NMOS transistor N3. The fourth input transistor NMOS transistor N4 is connected to the cutoff voltage, the fourth input transistor NMOS transistor N4 is turned off, and the current Ip of the second input branch is equal to the current of the third input transistor NMOS transistor N2. The current In of the first input branch is greater than the current Ip of the second input branch. The positive hysteresis window is achieved by (Vref, Vref + Vhsy1) during the increase of the first voltage VIN.

[0062] As the first voltage VIN increases from Vref+Vhsy1 to VH and then decreases to the second voltage Vref, the current In of the first input branch equals the current of the second input transistor N1 and the current of the first input transistor N3, and the current Ip of the second input branch equals the current of the third input transistor N2. The output voltage Vout of the hysteresis comparator 100 remains high.

[0063] When the first voltage VIN decreases to the second voltage Vref, the output voltage Vout of the hysteresis comparator 100 does not flip. As the first voltage VIN decreases from the second voltage Vref to the second voltage Vref minus the hysteresis voltage Vhsy2, the current In of the second input branch gradually decreases, but remains greater than the current Ip of the second input branch. The output voltage Vout of the hysteresis comparator 100 remains high. The equation (Vref - Vhsy2, Vref) during the decreasing process of the first voltage VIN implements a negative hysteresis window.

[0064] When the first voltage VIN decreases to the second voltage Vref minus the hysteresis voltage Vhsy2 , the current In of the first input branch is equal to the current Ip of the second input branch, and the output voltage Vout of the hysteresis comparator 100 reverses.

[0065] As the first voltage VIN continues to decrease by subtracting the hysteresis voltage Vhsy2 from the second voltage Vref, the output voltage Vout of the hysteresis comparator 100 is at a low level, the first selection signal n_hys is 0, the second selection signal p_hys is 1, the second switches S2 and S3 are disconnected, and the first switches S1 and S4 are connected. The gate of the first input transistor NMOS transistor N3 is connected to the off-state voltage, and the first input transistor NMOS transistor N3 is disconnected. The gate of the fourth input transistor NMOS transistor N4 is connected to the second voltage Vref. The current In of the first input branch is equal to the current of the second input transistor NMOS transistor N1. The current Ip of the second input branch is equal to the current of the third input transistor NMOS transistor N2 and the current of the fourth input transistor NMOS transistor N4.

[0066] The size of the negative hysteresis window can be adjusted by changing the ratio of the width-to-length ratios of the second input NMOS transistor N1 and the first input transistor N3. The size of the positive hysteresis window can be adjusted by changing the ratio of the width-to-length ratios of the third input transistor NMOS transistor N2 and the fourth input transistor NMOS transistor N4. In some embodiments, the first input branch includes two or more sub-input branches, that is, multiple first input transistors NMOS transistors N3 are provided, and the gate of each first input transistor NMOS transistor N3 is selectively connected to the first voltage VIN and the shutdown power supply. This provides a wider range of negative hysteresis windows. The multiple first input transistors NMOS transistors N3 can have different width-to-length ratios, for example, the width-to-length ratios of the multiple first input transistors NMOS transistors N3 can increase or decrease, facilitating dynamic adjustment through software. In some embodiments, the second input branch includes two or more sub-input branches, that is, multiple fourth input transistors NMOS transistors N4 are provided, and the gate of each fourth input transistor NMOS transistor N4 is selectively connected to the second voltage Vref and the shutdown power supply. This provides a wider range of positive hysteresis windows. Similarly, the plurality of fourth input transistors NMOS transistors N4 may have different width-to-length ratios. For example, the width-to-length ratios of the plurality of fourth input transistors NMOS transistors N4 may increase or decrease.

[0067] When the first enable signal n_hys_en is 1 and the second enable signal p_hys_en is 0, the negative hysteresis window is enabled. The output characteristics of the hysteresis comparator 100 are as follows: Figure 7When the first enable signal n_hys_en is 0 and the second enable signal p_hys_en is 1, the positive hysteresis window is enabled. The output characteristics of the hysteresis comparator 100 are shown as follows: Figure 6 The specific process is shown in the figure, and no further description is given.

[0068] exist Figure 8 In the hysteresis comparator 100 shown, the gate of the first input transistor NMOS transistor N3 is selectively connected to one of the first voltage VIN and the shutdown voltage through the first switches S1 and S2, and the gate of the fourth input transistor NMOS transistor N4 is selectively connected to one of the second voltage Vref and the shutdown voltage through the third switches S3 and S4.

[0069] Figure 12 FIG. 2 shows a circuit diagram of another hysteresis comparator 200 according to an embodiment of the present application. Figure 12 In the hysteresis comparator 200 shown, the gate of the first input transistor NMOS transistor N3 receives the first voltage VIN, the gate of the fourth input transistor NMOS transistor N4 receives the second voltage Vref, the first input transistor NMOS transistor N3 is selected by the fifth switch S5 to be connected in parallel with the second input transistor NMOS transistor N1 in the first input branch or disconnected from the second input transistor NMOS transistor N1, and the fourth input transistor NMOS transistor N4 is selected by the sixth switch S6 to be connected in parallel with the third input transistor NMOS transistor N2 in the second input branch or disconnected from the third input transistor NMOS transistor N2. Figure 12 As shown, the hysteresis comparator 200 includes an input stage and an amplification stage. Figure 12 The amplifier stage of the hysteresis comparator shown and Figure 8 The amplifier stages of the hysteresis comparators shown are identical. Figure 12 The input stage of the hysteresis comparator shown includes a current source Iref, a first input branch, and a second input branch. One end of the current source Iref is connected to node node1, and the other end is grounded. The first input branch is disposed between node node1 and node node2. The second input branch is disposed between node node1 and node node3.

[0070] The first input branch includes a first sub-input branch and a second sub-input branch. The first sub-input branch includes a second input transistor (NMOS transistor N1), the drain of which is connected to node node2, the source of which is connected to node node1, and the gate of which receives a first voltage VIN. The second sub-input branch includes a first input transistor (NMOS transistor N3) and a fifth switch S5 connected in series between nodes node1 and node2, the gate of which receives the first voltage VIN. One end of the fifth switch S5 is connected to node node2, and the other end is connected to the first input transistor (NMOS transistor N3). In other embodiments, one end of the fifth switch S5 is connected to node node1, and the other end is connected to the first input transistor (NMOS transistor N3). A first select signal n_hys controls the conduction and disconnection of the fifth switch S5. When the first selection signal n_hys is high and the fifth switch S5 is turned on, the first and second sub-input branches are connected in parallel. The current In of the first input branch is equal to the current of the second input transistor NMOS transistor N1 plus the current of the third input transistor NMOS transistor N2. When the first selection signal n_hys is low and the fifth switch S5 is turned off, the first and second sub-input branches are disconnected. The current In of the first input branch is equal to the current of the second input transistor NMOS transistor N1. The first selection signal n_hys adjusts the number of connected sub-input branches in the first input branch, thereby adjusting the current In of the first input branch.

[0071] The second input branch includes a third sub-input branch and a fourth sub-input branch. The third sub-input branch includes a third input transistor (NMOS transistor N2), the drain of which is connected to node node3, the source of which is connected to node node1, and the gate of which receives a second voltage Vref. The fourth sub-input branch includes a fourth input transistor (NMOS transistor N4) and a sixth switch S6 connected in series between nodes node1 and node3, the gate of which receives the second voltage Vref. One end of the sixth switch S6 is connected to node node3, and the other end is connected to the fourth input transistor (NMOS transistor N4). In other embodiments, one end of the sixth switch S6 is connected to node node1, and the other end is connected to the fourth input transistor (NMOS transistor N4). A second selection signal p_hys controls the conduction and disconnection of the sixth switch S6. When the second selection signal p_hys is high and the sixth switch S6 is turned on, the third and fourth sub-input branches are connected in parallel, and the current Ip of the second input branch is equal to the current of the third input transistor NMOS transistor N2 plus the current of the fourth input transistor NMOS transistor N4. When the second selection signal p_hys is low and the sixth switch S6 is turned off, the third and fourth sub-input branches are disconnected, and the current Ip of the second input branch is equal to the current of the third input transistor NMOS transistor N2. The second selection signal p_hys adjusts the number of sub-input branches connected in the second input branch, thereby adjusting the current Ip of the second input branch.

[0072] When the first selection signal n_hys is 1, the fifth switch S5 is turned on, and when the second selection signal p_hys is 1, the sixth switch S6 is turned on. Figure 9 The circuit shown produces. Figure 12 The operation of the hysteresis comparator is shown in Figure 8 The working process of the hysteresis comparator shown is the same and will not be repeated here.

[0073] In some embodiments, the second input branch has a fixed effective aspect ratio, and by changing the effective aspect ratio of the first input branch, a hysteresis comparator that only provides a negative hysteresis window can be implemented. In some embodiments, the first input branch has a fixed effective aspect ratio, and by changing the effective aspect ratio of the second input branch, a hysteresis comparator that only provides a positive hysteresis window can be implemented.

[0074] Figure 13 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown. Figure 13 The hysteresis comparator shown is based on Figure 3operational amplifier shown. Figure 13 The hysteresis comparator 300 shown includes an input stage and an amplification stage.

[0075] The input stage includes: a current source Iref, a first input branch, and a second input branch. One end of the current source Iref is connected to node node1, and the other end is grounded. The first input branch is arranged between node node1 and node node2. The second input branch is arranged between node node1 and node node3. The second input branch includes: a third input transistor NMOS transistor N2, the gate of which receives a second voltage Vref, and the magnitude of the current generated by the third input transistor NMOS transistor N2 depends on the second voltage Vref. The current of the second input branch is equal to the current generated by the third input transistor NMOS transistor N2. The first input branch includes: a first sub-input branch and a second sub-input branch. The first sub-input branch includes a second input transistor NMOS transistor N1, the gate of which receives a first voltage VIN, the drain of which is connected to node node2, and the source of which is connected to node node1. The second sub-input branch includes a first input transistor (NMOS transistor) N3. The drain of the first input transistor (NMOS transistor) N3 is connected to node node2, and the source is connected to node node1. The gate of the first input transistor (NMOS transistor) N3 is connected to the cutoff voltage via a switch (S9) and to the first voltage (VIN) via a first switch (S10). A first selection signal (n_hys) controls the on / off switching of switches (S9) and (S10).

[0076] The amplifier stage includes PMOS transistors P25 and P26. PMOS transistors P25 and P26 form a current mirror. The gate and drain of PMOS transistor P25 and the gate of PMOS transistor P26 are connected to node 2. The drain of PMOS transistor P26 is connected to node 3, which serves as the output of hysteresis comparator 300. Figure 13 The hysteresis comparator 300 can provide a negative hysteresis window and can be used in application scenarios where only a negative hysteresis window is required, that is, M is 1. Figure 8 and Figure 12 The hysteresis comparator 300 shown saves the number of transistors and thus saves the layout area.

[0077] Figure 14 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown. Figure 14 The hysteresis comparator shown is based on Figure 3 operational amplifier shown. Figure 14 The hysteresis comparator 400 shown includes an input stage and an amplification stage.

[0078] The input stage includes a current source Iref, a first input branch, and a second input branch. One end of the current source Iref is connected to node node1, and the other end is grounded. The first input branch is provided between node node1 and node node2. The second input branch is provided between node node1 and node node3. The second input branch includes a third input transistor NMOS transistor N2, whose gate receives a second voltage Vref. The magnitude of the current generated by the third input transistor NMOS transistor N2 depends on the second voltage Vref. The current in the second input branch is equal to the current generated by the third input transistor NMOS transistor N2. The first input branch includes a first sub-input branch and a second sub-input branch. The first sub-input branch includes a second input transistor NMOS transistor N1, whose gate receives a first voltage VIN, whose drain is connected to node node2, and whose source is connected to node node1. The second sub-input branch includes a first input transistor NMOS transistor N3 and a first switch S13 connected in series. The drain of the first input transistor NMOS transistor N3 is connected to the node node2 through the first switch S13, the source is connected to the node node1, and the gate of the first input transistor NMOS transistor N3 receives the first voltage VIN. The first selection signal n_hys controls the on / off of the first switch S13.

[0079] The amplifier stage includes PMOS transistors P25 and P26. PMOS transistors P25 and P26 form a current mirror. The gate and drain of PMOS transistor P25 and the gate of PMOS transistor P26 are connected to node 2. The drain of PMOS transistor P26 is connected to node 3, which serves as the output of hysteresis comparator 400. Figure 14 The hysteresis comparator 400 can provide a negative hysteresis window and can be used in application scenarios where only a negative hysteresis window is required. That is, N is 1. Figure 8 and Figure 12 The hysteresis comparator shown saves transistor count and thus saves layout area.

[0080] Figure 15 A circuit diagram of another hysteresis comparator according to an embodiment of the present application is shown. Figure 14The illustrated hysteresis comparator is based on a cascode operational amplifier. Hysteresis comparator 500 includes an input stage and an output stage. The input stage includes a current source Iref, a first input branch, and a second input branch. One end of current source Iref is connected to node node1, and the other end is grounded. The first input branch is disposed between node node1 and node node2. The second input branch is disposed between node node1 and node node3. The first input branch includes a second input transistor (NMOS transistor N1). The source of the second input transistor (NMOS transistor N1) is connected to node node1, the drain is connected to node node2, and the gate of the second input transistor (NMOS transistor N1) is connected to a first voltage (VIN). The second input transistor (NMOS transistor N1) generates a current based on the first voltage (VIN). The current in the first input branch is equal to the current in the second input transistor (NMOS transistor N1). The second input branch includes a third sub-input branch and a fourth sub-input branch. The third sub-input branch includes a third input transistor (NMOS transistor N2), and the fourth sub-input branch includes a fourth input transistor (NMOS transistor N4). The third input transistor, NMOS transistor N2, has a source connected to node node1, a drain connected to node node3, and a gate receiving the second voltage Vref. The fourth input transistor, NMOS transistor N4, has a source connected to node node1, and a drain connected to node node3. The gate of the fourth input transistor, NMOS transistor N4, is connected to the off voltage via a first switch S16 and to the second voltage Vref via a first switch S17. A second select signal n_hys controls the on / off switching of first switches S16 and S17.

[0081] The input stage further includes an NMOS transistor N11 and an NMOS transistor N12. The NMOS transistor N11 is connected to the node node2, and the NMOS transistor N12 is connected to the node node3. The gates of the NMOS transistors N11 and NMOS transistors N12 receive a bias voltage Vbias3.

[0082] The amplifier stage includes PMOS transistors P27-P30. PMOS transistor P27, PMOS transistor P29, and NMOS transistor N11 are connected in series between a power supply terminal and node node2. PMOS transistors P28, PMOS transistor P30, and NMOS transistor N12 are connected in series between a power supply terminal and node node3. The gates of PMOS transistors P27 and P28 receive bias voltage Vbias1, while the gates of PMOS transistors P28 and P30 receive bias voltage Vbias2. The drain of PMOS transistor P30 is connected to the drain of NMOS transistor N12, serving as the output of hysteresis comparator 500.

[0083] Figure 15The hysteresis comparator 500 can provide a positive hysteresis window and can be used in application scenarios where only a positive hysteresis window is required. Figure 8 and Figure 12 The hysteresis comparator shown saves transistor count and thus saves layout area.

[0084] See also Figure 16 The present application also provides a chip, comprising the hysteresis comparator of the above embodiment and other circuit elements connected to the hysteresis comparator to implement circuit functions corresponding to the other circuit elements.

[0085] It should be noted that in the description of the present invention, the terms "first" and "second" are used solely to facilitate description of different components or names and should not be construed as indicating or implying a sequential relationship, relative importance, or implicitly specifying the number of technical features being referred to. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one such feature.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0087] It should be noted that although the specific embodiments of the present invention are described in detail in conjunction with the accompanying drawings, this should not be construed as limiting the scope of protection of the present invention. Within the scope described by the claims, various modifications and variations that can be made by those skilled in the art without creative effort still fall within the scope of protection of the present invention.

[0088] The examples of the embodiments of the present invention are intended to briefly illustrate the technical features of the embodiments of the present invention so that those skilled in the art can intuitively understand the technical features of the embodiments of the present invention, and are not intended to improperly limit the embodiments of the present invention.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A hysteresis comparator based on an operational amplifier, the hysteresis comparator being configured to compare a first voltage and a second voltage, the hysteresis comparator comprising: an input stage, and an amplifier stage connected to the input stage, The input stage includes: a first input branch and a second input branch, the first input branch generates a first current based on the first voltage, and the second input branch generates a second current based on the second voltage. The first input branch includes N connected sub-input branches, where N is determined by a first selection signal. If N is greater than or equal to 2, the N sub-input branches are connected in parallel. The second input branch includes M connected sub-input branches, where M is determined by a second selection signal. If M is greater than or equal to 2, the M sub-input branches are connected in parallel. M and N are positive integers, at least one of which is greater than or equal to 2. The amplifier stage includes: a first input terminal, a second input terminal, and an output terminal, wherein the first current and the second current are connected to the first input terminal and the second input terminal respectively, and when the first current is greater than the second current, the output terminal outputs a first level, and when the first current is less than the second current, the output terminal outputs a second level, wherein the first level and the second level are high and low levels respectively; If N is a positive integer greater than or equal to 2, the hysteresis comparator provides a negative hysteresis window, and the width-to-length ratios of the input transistors of each of the N sub-input branches are different; if M is a positive integer greater than or equal to 2, the hysteresis comparator provides a positive hysteresis window, and the width-to-length ratios of the input transistors of each of the M sub-input branches are different.

2. The hysteresis comparator according to claim 1, wherein: If N is a positive integer greater than 2, the first input branch includes N-1 first sub-input branches and one second sub-input branch, and the width-to-length ratios of the first input transistors in the N-1 first sub-input branches are different; if M is a positive integer greater than 2, the second input branch includes M-1 fourth sub-input branches and one third sub-input branch, and the width-to-length ratios of the fourth input transistors in the M-1 fourth sub-input branches are different.

3. The hysteresis comparator according to claim 2, wherein: The width-to-length ratio of each first input transistor in the N-1 first sub-input branches is increasing or decreasing; and / or the width-to-length ratio of each fourth input transistor in the M-1 fourth sub-input branches is increasing or decreasing.

4. The hysteresis comparator according to claim 1, wherein: If N is a positive integer greater than or equal to 2, the first input branch includes: a first sub-input branch and a second sub-input branch, the first sub-input branch includes a first input transistor, the gate of the first input transistor selectively receives one of the first voltage and a shutoff voltage according to the first selection signal, when the gate of the first input transistor receives the first voltage, the first sub-input branch is connected in parallel with the second sub-input branch, when the gate of the first input transistor receives the shutoff voltage, the first sub-input branch is disconnected from the second sub-input branch, and the second sub-input branch includes a second input transistor, the gate of the second input transistor receives the first voltage; If N is 1, the first input branch includes: a second sub-input branch, the second sub-input branch includes a second input transistor, and the gate of the second input transistor receives the first voltage; If M is a positive integer greater than or equal to 2, the second input branch includes: a third sub-input branch and a fourth sub-input branch, the fourth sub-input branch includes a fourth input transistor, the gate of the fourth input transistor selectively receives one of the second voltage and the shutdown voltage according to the second selection signal, when the gate of the fourth input transistor receives the second voltage, the fourth sub-input branch is connected in parallel with the third sub-input branch, when the gate of the fourth input transistor receives the shutdown voltage, the fourth sub-input branch is disconnected from the third sub-input branch, the third sub-input branch includes a third input transistor, the gate of the third input transistor receives the second voltage; If M is 1, the second input branch includes: a third sub-input branch, the third sub-input branch includes a third input transistor, and the gate of the third input transistor receives the second voltage; The hysteresis comparator further includes a Schmitt trigger, wherein the input end of the Schmitt trigger is connected to the output end of the amplifier stage.

5. The hysteresis comparator according to claim 4, wherein: The gate of the first input transistor is connected to the shutdown voltage through a first switch and to the first voltage through a second switch. If the first selection signal is at a high level, the first switch is turned off and the second switch is turned on, and the gate of the first input transistor receives the first voltage. If the first selection signal is at a low level, the first switch is turned on and the second switch is turned off, and the gate of the first input transistor receives the shutdown voltage. The gate of the fourth input transistor is connected to the shutdown voltage through the third switch and to the second voltage through the fourth switch. If the second selection signal is at a high level, the third switch is turned off and the fourth switch is turned on, and the gate of the fourth input transistor receives the second voltage. If the second selection signal is at a low level, the third switch is turned on and the fourth switch is turned off, and the gate of the fourth input transistor receives the shutdown voltage.

6. The hysteresis comparator according to claim 5, wherein: The second switch and the fourth switch are transmission gates.

7. The hysteresis comparator according to claim 6, wherein: The transmission gate includes a PMOS transistor and an NMOS transistor connected in parallel, the drains of the PMOS transistor and the NMOS transistor are connected in parallel to receive the first voltage or the second voltage, the sources of the PMOS transistor and the NMOS transistor are connected in parallel to the gate of the first input transistor or the fourth input transistor, the gate of the NMOS transistor receives a first selection signal, and the gate of the PMOS transistor receives an inverted signal of the first selection signal.

8. The hysteresis comparator according to claim 1, wherein: If N is a positive integer greater than or equal to 2, the first input branch includes: a first sub-input branch and a second sub-input branch, the first sub-input branch includes a first input transistor, a gate of the first input transistor receives the first voltage, a drain of the first input transistor receives the first selection signal, the first selection signal controls the first sub-input branch to be connected in parallel with or disconnected from the second sub-input branch, and the second sub-input branch includes a second input transistor, a gate of the second input transistor receives the first voltage; If N is 1, the first input branch includes: a second sub-input branch, the second sub-input branch includes a second input transistor, and the gate of the second input transistor receives the first voltage; If M is a positive integer greater than or equal to 2, the second input branch includes: a third sub-input branch and a fourth sub-input branch, the fourth sub-input branch includes a fourth input transistor, the gate of the fourth input transistor receives the second voltage, the drain of the fourth input transistor receives the second selection signal, the second selection signal controls the fourth sub-input branch to be connected in parallel with or disconnected from the third sub-input branch, the third sub-input branch includes a third input transistor, the gate of the third input transistor receives the second voltage; If M is 1, the second input branch includes: a third sub-input branch, the third sub-input branch includes a third input transistor, and the gate of the third input transistor receives the second voltage.

9. The hysteresis comparator according to claim 8, wherein: The drain of the first input transistor receives the first selection signal through a fifth switch. When the first selection signal is at a high level, the fifth switch is turned on, so that the first sub-input branch is connected in parallel with the second sub-input branch. When the first selection signal is at a low level, the fifth switch is turned off, so that the first sub-input branch is disconnected from the second sub-input branch. The drain of the fourth input transistor receives the second selection signal through the sixth switch. When the second selection signal is at a high level, the sixth switch is turned on, so that the fourth sub-input branch is connected in parallel with the third sub-input branch. When the second selection signal is at a low level, the sixth switch is turned off, so that the fourth sub-input branch is disconnected from the third sub-input branch.

10. The hysteresis comparator according to any one of claims 1 to 9, characterized in that: The hysteresis comparator receives a first enable signal and a second enable signal, the first enable signal is used to enable the negative hysteresis window, and the second enable signal is used to enable the positive hysteresis window, the first selection signal is determined according to the first enable signal and the output level of the hysteresis comparator, and the second selection signal is determined according to the second enable signal and the output level of the hysteresis comparator.

11. The hysteresis comparator according to claim 10, wherein: If the first enable signal enables the negative hysteresis window and the output level of the hysteresis comparator is low, the first selection signal is low; if the output level of the hysteresis comparator is high, the first selection signal is high; If the second enable signal enables the positive hysteresis window and the output level of the hysteresis comparator is low, the second selection signal is high; if the output level of the hysteresis comparator is high, the second selection signal is low.

12. A chip, characterized in that: The invention comprises the hysteresis comparator according to any one of claims 1 to 11.

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