A phase-locked loop without frequency divider and a reference double-delay frequency locking method thereof

Abstract

The application discloses a frequency divider-free phase-locked loop and a reference double-delay frequency locking method thereof. The sub-sampling phase-locked loop architecture receives an output of an oscillator and feeds back the output to a reference double-delay frequency locking loop. The output end of a reference double-delay generator in the reference double-delay frequency locking loop is electrically connected with the input end of a sample-and-hold circuit, and the output end of the sample-and-hold circuit is electrically connected with the input end of an automatic phase error state detector. The sample-and-hold circuit simultaneously receives an oscillator output feedback signal of the sub-sampling phase-locked loop architecture. The output end of the automatic phase error state detector is electrically connected with the input end of an adaptive output frequency corrector, and the output end of the adaptive output frequency corrector is electrically connected with the sub-sampling phase-locked loop architecture. Unequal double-reference clock delays are introduced, the sample-and-hold circuit is combined to realize the detection of the output frequency, a new frequency locking loop working at a reference frequency is used to replace a traditional frequency locking loop, and the problem of high power consumption caused by a high-frequency frequency divider is solved.

Description

Technical Field

[0001] This application relates to the field of phase-locked loop (PLL) technology, specifically to a dividerless PLL and its reference dual-delay frequency locking method. Background Technology

[0002] Classic charge pump phase-locked loop circuits, such as Figure 1 As shown, the circuit consists of five modules: a phase detector, a charge pump, a loop filter, an oscillator, and a frequency divider. The phase-locked loop (PLL) detects the frequency and phase difference between the reference clock and the frequency divider output (feedback clock) through the phase detector, generating a pulse signal to control the output current of the charge pump. This output current charges and discharges the loop filter. The loop filter filters out high-frequency signals generated by the phase detector and charge pump, reducing loop noise, and converts the output current into a control voltage to control the oscillation frequency of the oscillator. The frequency divider then divides the high-frequency output signal of the oscillator and feeds it back to the phase detector, forming a feedback network. The loop eventually reaches a stable state through repeated adjustments. Figure 1 For the charge pump phase-locked loop represented by this example, the noise from the frequency divider, phase detector, and charge pump will be amplified by N within the loop bandwidth. 2 The ratio N (division ratio) introduces phase noise that severely degrades the jitter performance of the phase-locked loop (PLL). To support high data rate mobile wireless communication across multiple millimeter-wave bands, there is a significant demand for millimeter-wave PLLs with wide tuning range, low phase noise, and low power consumption. As a key component of the PLL, the millimeter-wave divider has a limited frequency range, high power consumption, and degrades the phase noise performance of the PLL. Therefore, dividerless PLLs have been extensively studied in recent years.

[0003] Traditional subsampling phase-locked loops can lock the phase without a frequency divider, essentially eliminating the amplification of noise from the phase detector and charge pump. 2 The problem has been solved, and excellent results have been achieved in realizing low in-band phase noise. Its architecture diagram is shown below. Figure 2 As shown in (a), the phase-locked loop circuit consists of a subsampling phase detector, a subsampling charge pump, a loop filter, and an oscillator. Figure 2 (b) shows the phase detection characteristics of the subsampling phase-locked loop (PLL). Near the lock point, the phase detection gain is much greater than that of a traditional charge-pump PLL, thus reducing in-band phase noise. However, the phase detection range of the PLL is very limited; without a frequency divider, it can only guarantee phase locking, not correct frequency locking. Therefore, an additional frequency-locking loop (operating similarly to a traditional charge-pump PLL) is usually needed to control the division ratio to ensure correct locking, such as... Figure 3 As shown. However, the frequency divider, as an important component in the frequency-locked loop, has high power consumption, accounting for most of the power consumption of the frequency-locked loop, which becomes more pronounced at higher frequencies.

[0004] To overcome the problems in traditional technologies, see Figure 4 First, a low-frequency conventional phase-locked loop (PLL) generates an intermediate frequency signal f2 from the input crystal reference f1. The subsampled PLL output frequency f3 is an integer multiple of this intermediate frequency f2. The intermediate frequency signal is used to frequency lock the millimeter-wave subsampled PLL and detect the locking state of the subsampled PLL. When the subsampled PLL uses the intermediate frequency as a reference, the frequency synthesizer performs frequency identification similar to a cascaded PLL. In the design proposed in prior art 2, the intermediate frequency is chosen as f2, so the output frequency f3 = N × f2. During initial calibration, the capacitor bank setting of the voltage-controlled oscillator can be determined to generate the target output frequency range. Using this obtained capacitor bank setting, the subsampled PLL will only lock a harmonic of f2 to generate f3. After frequency acquisition, the subsampled PLL will directly use the crystal signal of f1 as a reference, utilizing the low phase noise of the crystal. Therefore, the f2 signal does not affect the output phase noise of the subsampled PLL in steady state. The reference switching process is automatic and is implemented by the subsampled lock detector. The subsampling lock detector samples the subsampling phase-locked loop (PLL) output using an intermediate frequency (IF) of f2 and uses internal signal processing to detect whether the PLL is locked at f3. If the PLL loses lock or locks to an incorrect f1 harmonic, for example, when the output frequency is between f3 and f1, the subsampling lock detector automatically switches the PLL's reference f2 for frequency acquisition. Once the PLL locks to f3, the subsampling lock detector switches the reference back to f1 and continues to monitor the lock status. Therefore, with the help of the subsampling lock detector, the system achieves automatic lock detection and relocking of the subsampling PLL. However, the PLL output frequency can only be an integer multiple of the intermediate frequency f2, which limits the PLL's output frequency accuracy and makes it difficult to meet the requirements of existing applications. In addition, the voltage-controlled oscillator (VCO) of this scheme needs to have a smaller frequency tuning range than the IF under any capacitor bank setting, and the oscillator output frequency needs to be tested in advance to select the correct capacitor bank, making it difficult to adapt to correct locking over a wide frequency range.

[0005] Application content

[0006] In view of this, this application provides a dividerless phase-locked loop and its reference dual-delay frequency locking method to help solve the problems in the prior art.

[0007] In a first aspect, embodiments of this application provide a dividerless phase-locked loop (PLL), comprising: a subsampling PLL architecture and a reference dual-delay frequency-locked loop (CDL). The subsampling PLL architecture receives a reference signal and feeds back the output of its oscillator to the reference dual-delay CDL. The reference dual-delay CDL includes: a reference dual-delay generator, a sample-and-hold circuit, an automatic phase error state detector, and an adaptive output frequency corrector. The output of the reference dual-delay generator is electrically connected to the input of the sample-and-hold circuit, and the output of the sample-and-hold circuit is electrically connected to the input of the automatic phase error state detector. The sample-and-hold circuit simultaneously receives the oscillator output feedback signal from the subsampling PLL architecture. The output of the automatic phase error state detector is electrically connected to the input of the adaptive output frequency corrector, and the output of the adaptive output frequency corrector is electrically connected to the subsampling PLL architecture.

[0008] In one possible implementation, the subsampling phase-locked loop architecture includes a subsampling phase detector, a subsampling charge pump, a loop filter circuit, and an oscillator connected in sequence. The input of the subsampling phase detector receives the reference signal and the output signal of the oscillator, and the output of the adaptive output frequency corrector is electrically connected to the subsampling charge pump and the loop filter circuit.

[0009] In one possible implementation, the reference dual-delay generator includes a first delay unit, a second delay unit, and a third delay unit. The input terminal of the first delay unit is electrically connected to the reference signal input terminal, and the output terminal of the first delay unit outputs a first delay signal. Therefore, the input terminal of the second delay unit is electrically connected to the reference signal input terminal, and the output terminal of the second delay unit is electrically connected to both the output terminal of the reference dual-delay generator and the input terminal of the third delay unit. The output terminal of the second delay unit outputs a second delay signal, while the third delay unit outputs a third delay signal.

[0010] In one possible implementation, the delay unit consists of an inverter chain, a digital time converter, an RC delay, and a delay line.

[0011] In one possible implementation, the oscillator includes: a digital oscillator, an analog oscillator, an LC oscillator, and a ring oscillator.

[0012] In a second aspect, an embodiment of the present application provides a reference dual-delay frequency locking method, which uses the frequency divider-free phase-locked loop described in any possible implementation manner of the first aspect. The method includes: a reference dual-delay generator generates four reference signals Ref1, Ref1’, Ref2, and Ref2’. Then, the reference dual-delay generator samples the differential output of the oscillator through a sample-and-hold circuit to obtain four corresponding sampling points P1, P1’, P2, and P2’. The voltages V P1 , V P1’ , V P2 , and V P2’ corresponding to the sampling points are used by an automatic phase error state detector to detect the current states of P1’ and P2’. The state information of P1’ and P2’ is then passed through an adaptive output frequency corrector to control the loop filter, thereby controlling the output frequency of the voltage-controlled oscillator, and finally achieving frequency locking.

[0013] In a possible implementation manner, the Refn signal samples the differential output of the oscillator to obtain V Pn and V Pn -. Then, a group of comparators compares the values of V Pn and V Pn -. The comparison result is used to determine the magnitude relationship between V Pn and V DC . The V DC is the DC level output by the oscillator.

[0014] In a possible implementation manner, the polarity and slope of the sampling points are extracted, and the sampling points are divided into four states, namely state I, II, III, and IV. In state I, V Pn < V DC and V Pn > V Pn’ ; in state II, V Pn < V DC and V Pn < V Pn’ ; in state III, V Pn > V DC and V Pn > V Pn’ ; in state IV, V Pn > V DC and V Pn > V Pn’ .

[0015] In a possible implementation manner, the states of P2’ and P1’ are compared. If it is detected that the output frequency f out of the phase-locked loop > f0, then the output current I out < 0; when it is detected that f out < f0, then the output of the frequency locking loop I out>0; when f is detected out =f0, output I out If the value is 0, and this state remains unchanged for N0 reference clock cycles, it means that the frequency has reached the target frequency and the phase-locked loop is locked.

[0016] In this embodiment, by introducing unequal dual reference clock delays and combining them with a sample-and-hold circuit to detect the output frequency, a novel frequency-locked loop operating at the reference frequency is used instead of the traditional frequency-locked loop operating at the oscillator frequency, thus solving the high power consumption problem introduced by the high-frequency divider. Furthermore, the dual-delay mechanism of the reference clock and the frequency detection circuit here are suitable for frequency locking of wideband phase-locked loops. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the architecture of a classic charge pump phase-locked loop;

[0019] Figure 2 A schematic diagram of the architecture and phase detection characteristics of a subsampling phase-locked loop;

[0020] Figure 3 A schematic diagram of a subsampling phase-locked loop architecture with a frequency-locked loop;

[0021] Figure 4 Schematic diagram of a dividerless phase-locked loop architecture;

[0022] Figure 5 A schematic diagram of a dividerless phase-locked loop provided in an embodiment of this application;

[0023] Figure 6 The implementation form of the delay unit provided in the embodiments of this application;

[0024] Figure 7 This application provides an implementation of an oscillator in a phase-locked loop.

[0025] Figure 8 A schematic diagram illustrating the measured locking behavior of a dividerless phase-locked loop provided in an embodiment of this application.

[0026] Figure 9 A schematic diagram illustrating the relationship between the reference double delay and the reference delay Δt2 and the output frequency, provided for embodiments of this application;

[0027] Figure 10A schematic diagram illustrating the polarity and slope of the sampling points provided in the embodiments of this application;

[0028] Figure 11 A schematic diagram illustrating the four states of an automatic phase error detector provided in an embodiment of this application;

[0029] Figure 12 This is a schematic diagram of frequency determination provided for an embodiment of this application;

[0030] Figure 13 This is a schematic diagram of the frequency determination logic provided in an embodiment of this application. Detailed Implementation

[0031] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0032] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0033] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0034] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0035] The reference dual-delay frequency-locked dividerless phase-locked loop architecture of this invention consists of key modules from a traditional subsampling phase-locked loop architecture and a reference dual-delay frequency-locked loop, such as... Figure 5 As shown. This frequency-locked loop includes a reference double delay (REF) loop. D Generator, sample-and-hold circuit, automatic phase error State detector, and adaptive output frequency (f out ) Corrector.

[0036] The subsampled phase-locked loop architecture receives a reference signal and feeds back the oscillator output to the reference dual-delay frequency-locked loop. The reference dual-delay frequency-locked loop includes a reference dual-delay generator, a sample-and-hold circuit, an automatic phase error state detector, and an adaptive output frequency corrector. The output of the reference dual-delay generator is electrically connected to the input of the sample-and-hold circuit, and the output of the sample-and-hold circuit is electrically connected to the input of the automatic phase error state detector. The sample-and-hold circuit simultaneously receives the oscillator output feedback signal from the subsampled phase-locked loop architecture. The output of the automatic phase error state detector is electrically connected to the input of the adaptive output frequency corrector, and the output of the adaptive output frequency corrector is electrically connected to the subsampled phase-locked loop architecture.

[0037] The subsampling phase-locked loop architecture in this embodiment includes a subsampling phase detector, a subsampling charge pump, a loop filter circuit, and an oscillator connected in sequence. The input terminal of the subsampling phase detector receives the reference signal and the output signal of the oscillator. The output terminal of the adaptive output frequency corrector is electrically connected to the subsampling charge pump and the loop filter circuit.

[0038] Furthermore, Figure 5 The reference dual-delay generator described herein includes a first delay unit, a second delay unit, and a third delay unit. The input terminal of the first delay unit is electrically connected to the reference signal input terminal, and the output terminal of the first delay unit outputs a first delay signal. Therefore, the input terminal of the second delay unit is electrically connected to the reference signal input terminal, and the output terminal of the second delay unit is electrically connected to both the output terminal of the reference dual-delay generator and the input terminal of the third delay unit. The output terminal of the second delay unit outputs a second delay signal, while the third delay unit outputs a third delay signal.

[0039] See Figure 6 The delay unit consists of an inverter chain, a digital time converter, an RC delay, and a delay line.

[0040] It should be noted that the dividerless frequency locking technology of this invention is applicable to analog phase-locked loops and digital phase-locked loops, without limitation on arbitrary reference and output frequencies, and is applicable to integer and fractional frequency division phase-locked loops. The oscillator it includes is not limited to any type; it can be an LC oscillator or a ring oscillator, such as... Figure 7 As shown.

[0041] The quadranting technique for distinguishing sinusoidal signals based on reference dual delay of this invention is not limited to frequency identification, but can also be used for delay calibration, phase quadrant selection, etc. The technique for identifying signal information through polarity and slope involved in this invention is not limited to using delay schemes, but can also use orthogonal phase transformation schemes to obtain the polarity and slope of the signal.

[0042] The locking behavior of the dividerless phase-locked loop provided in this application was experimentally tested, and as follows: Figure 8 As shown, the frequency locking function under wideband conditions has been implemented. Without the aid of a frequency divider, the output frequency can be controlled by changing the control code of Δt2, and this remains applicable under wideband millimeter-wave output, which is impossible for traditional subsampling phase-locked loop architectures without a frequency-locked loop.

[0043] This application provides a reference dual-delay frequency locking method, firstly REF D The generator produces four reference signals: Ref1, Ref1', Ref2, and Ref2'. For example... Figure 9 As shown, the delay between Ref1' and Ref1, or between Ref2' and Ref2, is Δt1. This delay is very small, less than one-tenth of the oscillator period. Δt2 is the delay between Ref1 and Ref2, or between Ref1' and Ref2', and it is equal to the period of the oscillator's target output signal. By controlling Δt2, the output frequency can be controlled. Afterwards, REF... D The differential output of the oscillator is sampled using a sample-and-hold circuit to obtain four corresponding sampling points: P1, P1', P2, and P2'. The voltage V corresponding to each sampling point is... P1 V P1’ V P2 V P2’ The automatic phase error state detector is used to detect the current state of P1' and P2'. The relative relationship between the states of P1' and P2' represents the relationship between the current oscillator output signal frequency and the target signal frequency. The state information of P1' and P2' is then passed through an adaptive output frequency corrector to control the loop filter, thereby controlling the output frequency of the voltage-controlled oscillator and finally achieving frequency locking.

[0044] Figure 10 This diagram illustrates how the automatic phase error detector of this invention obtains the states P1' and P2'. To determine the polarity of the sampling point, the differential output of the Refn signal sampling oscillator is used to obtain V. Pn and V Pn - Then a set of comparators compares V Pn and V Pn The value of - is used to determine V. Pn and V DC The size relationship, here V DC V is the DC level output by the oscillator, where n = 1 or 2. To obtain the slope of the sampling points, the oscillator output signal is sampled using reference signals Refn and Refn' respectively to obtain V. Pn and V Pn The value of ' is then compared with another comparator V. Pn and VPn ’s value.

[0045] Figure 11 Shows the definitions of the four states of the automatic phase error detector in the present invention. By extracting the polarity and slope of the sampling points, the sampling points are divided into four states, namely State I, II, III, and IV. In State I, V Pn <V DC And V Pn >V Pn’ ; In State II, V Pn <V DC And V Pn <V Pn’ ; In State III, V Pn >V DC And V Pn >V Pn’ ; In State IV, V Pn >V DC And V Pn >V Pn’ .

[0046] Figure 12 Is the schematic diagram of the frequency determination state machine and the frequency locking behavior diagram of this application. For the case of f out <f0, if P1’ is in State I, II, III, IV, then the corresponding state of P2’ is IV, I, II, III. At this time, the output of the phase-locked loop I out >0, making the output frequency f out Increase and finally equal the target frequency f0. Similarly, for the case of f out >f0, if P1’ is in State I, II, III, IV, then the corresponding state of P2’ is II, III, IV, I. At this time, the output of the phase-locked loop I out <0, making the output frequency f out Decrease and finally equal the target frequency f0. When the states of P1’ and P2’ are the same, the output frequency f out Is equal to the target frequency f0. At this time, the output of the phase-locked loop I out =0, the phase-locked loop is closed, and the remaining phase error is corrected by the sampling loop, and finally the locking of the phase-locked loop is achieved.

[0047] Figure 13 Is the frequency determination logic diagram of this application. First, compare the states of P2’ and P1’. If it is detected that f out >f0, then the output of the phase-locked loop I out <0; Similarly, when it is detected that f out <f0, then the output of the phase-locked loop I out >0; Only when it is detected that f out =f0, the output I outIf the value is 0, and this state remains unchanged for N0 reference clock cycles, it means that the frequency has reached the target frequency. The remaining small phase error will be eliminated by the sampling loop, and finally the phase-locked loop will lock the loop.

[0048] It should be noted that the specific details of the dividerless phase-locked loop architecture with reference dual-delay frequency locking involved in the embodiments of this application can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0049] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0050] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0051] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0052] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A dividerless phase-locked loop, characterized in that, include: A subsampled phase-locked loop (PLL) architecture and a reference dual-delay frequency-locked loop (CDL) are disclosed. The subsampled PLL architecture receives a reference signal and outputs a feedback signal to the reference dual-delay CDL. The reference dual-delay CDL includes a reference dual-delay generator, a sample-and-hold circuit, an automatic phase error state detector, and an adaptive output frequency corrector. The output of the reference dual-delay generator is electrically connected to the input of the sample-and-hold circuit, and the output of the sample-and-hold circuit is electrically connected to the input of the automatic phase error state detector. The sample-and-hold circuit simultaneously receives the feedback signal from the subsampled PLL architecture. The output of the automatic phase error state detector is electrically connected to the input of the adaptive output frequency corrector, and the output of the adaptive output frequency corrector is electrically connected to the subsampled PLL architecture. The subsampling phase-locked loop architecture includes a subsampling phase detector, a subsampling charge pump, a loop filter circuit, and an oscillator connected in sequence. The input terminal of the subsampling phase detector receives the reference signal, and the output terminal of the adaptive output frequency corrector is electrically connected to the subsampling charge pump. The reference dual-delay generator includes a first delay unit, a second delay unit, and a third delay unit. The input terminal of the first delay unit is electrically connected to the reference signal input terminal, and the output terminal of the first delay unit outputs a first delay signal. Therefore, the input terminal of the second delay unit is electrically connected to the reference signal input terminal, and the output terminal of the second delay unit is electrically connected to the output terminal of the reference dual-delay generator and the input terminal of the third delay unit, respectively. The output terminal of the second delay unit outputs a second delay signal, and the third delay unit outputs a third delay signal.

2. The dividerless phase-locked loop according to claim 1, characterized in that, The delay unit consists of an inverter chain, a digital time converter, an RC delay, and a delay line.

3. The dividerless phase-locked loop according to claim 2, characterized in that, The oscillator includes: an LC oscillator and a ring oscillator.

4. A reference dual-delay frequency locking method, characterized in that, The method employs the dividerless phase-locked loop according to any one of claims 1-3, comprising: generating four reference signals Ref1, Ref1', Ref2, and Ref2' using a reference dual-delay generator; then, sampling the differential output of the oscillator through a sample-and-hold circuit to obtain four corresponding sampling points P1, P1', P2, and P2', and the voltage V corresponding to each sampling point. P1 V P1’ V P2 V P2’ The automatic phase error state detector is used to detect the current state of P1' and P2'. The state information of P1' and P2' is then passed through the adaptive output frequency corrector to control the loop filter, thereby controlling the output frequency of the voltage-controlled oscillator and finally achieving frequency locking.

5. The reference dual-delay frequency locking method according to claim 4, characterized in that, The differential output of the Refn signal sampling oscillator yields V. Pn and V Pn - Then a set of comparators compares V Pn and V Pn The value of - is used to determine V. Pn and V DC The size relationship of V DC It is the DC level output by the oscillator.

6. The reference dual-delay frequency locking method according to claim 5, characterized in that, The polarity and slope of the sampling points are extracted, and the sampling points are divided into four states: state I, state II, state III, and state IV; in state I, V Pn <V DC And V Pn >V Pn’ In state II, V Pn <V DC And V Pn <V Pn’ In state III, V Pn >V DC And V Pn >V Pn’ In state IV, V Pn >V DC And V Pn >V Pn’ .

7. The reference dual-delay frequency locking method according to claim 6, characterized in that, Compare the states of P2’ and P1’; if it is detected that the output frequency f of the phase-locked loop out > f0, then the output current I of the frequency-locked loop out < 0; when it is detected that f out < f0, then the output I of the frequency-locked loop out > 0; when it is detected that f out = f0, the output I out is only 0. If this state remains unchanged within N0 reference clock cycles, it means that the frequency has reached the target frequency and the phase-locked loop is locked.

Images