Fully integrated time-domain analog-to-digital converter

Abstract

A fully synthesizable time domain analog-digital converter comprises a sample and hold circuit, a voltage time conversion circuit and a time digital conversion circuit connected in sequence, wherein: the sample and hold circuit converts a continuous time voltage signal into a discrete time voltage signal and outputs to the voltage time converter; the voltage time converter generates a START signal and a STOP signal by charging a capacitor unit and buffering and outputs to the time digital converter; the time digital converter outputs a digital signal according to the START signal and the STOP signal, realizing conversion of an analog voltage signal into a digital signal. The application builds a fully synthesizable sample and hold circuit, a voltage time conversion circuit and a time digital conversion circuit through basic digital logic units and constitutes an ADC, uses HDLs language to completely describe the ADC, and uses a digital circuit design tool to conveniently complete a simulation, synthesis, layout and wiring design process, thereby simplifying the design of the ADC.

Description

Technical Field

[0001] The present invention relates to a technology in the field of analog-to-digital converters, in particular to a fully synthesizable time-domain analog-to-digital converter (ADC). Background Art

[0002] Traditional ADC frameworks, based on analog circuit design concepts and processes, face increasing complexity in circuit design, verification, and layout as CMOS devices continue to shrink. By digitizing analog circuits, analog circuits built from basic digital logic units can be automated and easily completed using digital circuit design tools, including simulation, synthesis, and layout and routing. This significantly simplifies the analog circuit design process, shortens the design cycle, and makes analog circuits more adaptable to today's rapidly advancing technology. Furthermore, the ever-decreasing power supply voltage required to achieve lower power consumption poses challenges to traditional ADC design, such as accuracy, making it increasingly difficult for traditional ADCs to meet increasingly stringent performance specifications. Time-domain signal processing, on the other hand, benefits from advanced technology and declining power supply voltages. A time-domain signal represents an analog signal by the time difference between two digital events, such as the interval between rising edges. A time-domain ADC can use time signals as a transition, first converting the analog voltage signal into a time signal using a voltage-to-time converter (VTC), and then converting the time signal into a digital signal using a time-to-digital converter (TDC). Summary of the Invention

[0003] In view of the complex processes of simulation, layout and routing of existing analog-to-digital conversion circuits, the present invention proposes a fully synthesizable time-domain analog-to-digital converter. The fully synthesizable sample-and-hold circuit, voltage-to-time conversion circuit and time-to-digital conversion circuit are constructed through basic digital logic units to form an ADC. The ADC is fully described using the HDLs language, and digital circuit design tools are used to conveniently complete the design processes of simulation, synthesis, layout and routing, thereby simplifying the design of the ADC.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a fully synthesizable time-domain analog-to-digital converter, comprising: a sample-and-hold circuit, a voltage-to-time conversion circuit, and a time-to-digital conversion circuit connected in sequence, wherein: the sample-and-hold circuit converts a continuous-time voltage signal into a discrete-time voltage signal and outputs the signal to the voltage-to-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering a capacitor unit and outputs the signal to the time-to-digital converter; and the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, thereby converting the analog voltage signal into a digital signal.

[0006] The sample-and-hold circuit is composed of two identical sample-and-hold sub-circuits, each of which includes: a sampling capacitor unit, a shrinking capacitor unit, a first transmission gate, and a second transmission gate, wherein: the two ends of the first transmission gate are respectively connected to the input signal and the sampling capacitor unit, and the two ends of the second transmission gate are respectively connected to the sampling capacitor unit and the shrinking capacitor unit.

[0007] The voltage-to-time conversion circuit includes: a clocked comparator, two inverter arrays, two NOR gates, two buffers, an AND gate, and an OR gate, wherein: the clocked comparator compares the discrete-time voltage signals output by the sample-and-hold circuit and outputs the comparison result, namely the sign signal to time-to-digital converter; the output ends of the first and second inverter arrays are respectively connected to one input end of the corresponding NOR gate, and the other input end receives an inverted clock signal; the output ends of the two NOR gates and the output ends of the corresponding sample-and-hold circuit are respectively connected to the first and second buffers; the logical OR result of the outputs of the two buffers serves as a START signal, and the logical AND result serves as a STOP signal.

[0008] Preferably, the control signals φ and φ adjusted as needed are respectively used as inputs of the inverter arrays φ and φ.

[0009] The time-to-digital converter adopts a vernier delay chain structure, comprising: two parallel delay chains composed of buffers connected in series, a multi-stage clocked comparator and an encoder arranged between the two delay chains, wherein: the first delay chain and the second delay chain receive a START signal and a STOP signal, respectively. The clocked comparator compares the speed of the rising edge signal at each corresponding position in the two delay chains and outputs a temperature code. The clocked comparator's positive input terminal is connected to the node of the first delay chain, and the negative input terminal is connected to the node of the second delay chain. The encoder converts the temperature code into a binary digital signal based on the sign signal from the voltage-to-time conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit structure diagram of the present invention;

[0011] Figure 2 This is a schematic diagram of the sampling and holding circuit and the voltage-time conversion circuit of the present invention;

[0012] Figure 3 Schematic diagram of the timing of the voltage-to-time conversion circuit of the present invention;

[0013] Figure 4 Detailed structural diagram of the charging path of the voltage-to-time conversion circuit of the present invention;

[0014] Figure 5 This is a schematic diagram of a capacitor designed through a two-input NAND gate in the present invention;

[0015] Figure 6 Schematic diagram of the time-to-digital conversion circuit of the present invention;

[0016] Figure 7 Schematic diagram of delay chain signal transmission in the time-to-digital conversion circuit of the present invention;

[0017] Figure 8 A schematic diagram of a method for extending the buffer delay;

[0018] Figure 9 This is a schematic diagram of a synthesizable clocked comparator circuit. DETAILED DESCRIPTION

[0019] like Figure 1 As shown, this embodiment relates to a fully synthesizable time domain analog-to-digital converter, including: a sampling and holding circuit, a voltage-to-time conversion circuit, and a time-to-digital conversion circuit connected in sequence, wherein: the sampling and holding circuit converts a continuous-time voltage signal into a discrete-time voltage signal as the input of the voltage-to-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the signal to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, thereby converting the analog voltage signal into a digital signal.

[0020] like Figure 2 As shown, the sampling and holding circuit includes: a sampling capacitor unit C 1P and C 1N , shrink capacitor unit C 2P and C 2N and transmission gate S 1P 、S 1N 、S 2P and S 2N , where: non-inverting input, first transmission gate S 1P The two ends of the positive phase input signal VINP and the sampling capacitor unit C 1P Connect the second transmission gate S 2P The two ends of the sampling capacitor unit C 1P and the shrinkage capacitor unit C 2P Connection. Sampling capacitor unit C 1P The positive phase input signal VINP is sampled and connected to the shrink capacitor unit C 2P Charge sharing is used to achieve shrink sampling, which can increase the input range of the entire circuit. The connection method and circuit principle of the inverting input circuit are the same as those of the non-inverting input circuit.

[0021] The two sampling capacitor units and the two shrinking capacitor units are both implemented using a NAND gate with a grounded input and a floating output, and the gate capacitance of PMOS and NMOS is used as a capacitor. Figure 5 shown.

[0022] The four transmission gates are all turned on and off by a clock signal.

[0023] like Figure 2 As shown, the voltage-time conversion circuit includes: a clocked comparator CMP, two inverter arrays INV_ARRAP_P and INV_ARRAP_N, two NOR gates NOR_P and NOR_N, two buffers BUF_P and BUF_N, an AND gate AND, and an OR gate OR, wherein: the clocked comparator CMP compares the discrete-time voltage signal V output by the sample-and-hold circuit XP and V XN The comparison result is output as the encoder control signal SIGN of the time-to-digital converter; the output terminals of the first and second inverter arrays are respectively connected to one input terminal of the corresponding NOR gate, and the other input terminal receives the inverted clock signal The output ends of the two NOR gates NOR_P and NOR_N and the output ends of the corresponding sample and hold circuits are connected to the first and second buffers BUF_P and BUF_N respectively. The logic OR result of the outputs of the two buffers is used as the START signal, and the logic AND result is used as the STOP signal.

[0024] The clocked comparator CMP is controlled by the clock signal CLK. When the clock signal CLK is high, the V XP and V XN After comparison, the output sign signal is used as the control signal of the encoder ENC in the time-to-digital converter to determine the positive or negative sign of the output.

[0025] The pull-up path of the NOR gate is composed of two PMOS tubes forming a cascade structure, which serves as a charging path to charge the sampling capacitor unit and the shrink capacitor unit, thereby achieving a better constant current effect. Figure 4 shown. Figure 4 The NOR gate is shown at the non-inverting input circuit, and its output is connected to V XP , V XP The two PMOS tubes above form a cascade structure, which can be connected to V XP The sampling capacitor unit C 1P And the shrink capacitor unit C 2P Provides a relatively constant charging current. The same applies to the inverting input circuit.

[0026] like Figure 4As shown, the inverter array INV_ARRAY_P consists of a certain number of inverters, whose outputs are connected to the input of the PMOS transistor near VDD of the NOR gate NOR_P. The inputs are independent, and the control signal CTRL_P is a multi-bit signal that can independently control the input of each inverter. The inverting input circuit is similar.

[0027] like Figure 6 As shown, the time-to-digital converter adopts a vernier delay chain structure, including: two parallel delay chains composed of buffers connected in series: BUF1_1, ..., BUF1_4, ..., BUF2_1, ..., BUF2_4, ...; a multi-stage clocked comparator CMP1, ..., CMP4, ... disposed between the two delay chains; and an encoder ENC. The first and second delay chains receive a START signal and a STOP signal, respectively. The clocked comparator compares the speed of the rising edge signal at each corresponding position in the two delay chains and outputs a temperature code. The clocked comparator's non-inverting input is connected to the node of the first delay chain, and its inverting input is connected to the node of the second delay chain. The encoder ENC converts the temperature code into a binary digital signal based on the sign signal from the voltage-to-time converter.

[0028] like Figure 2 As shown, when CLK is low, it is in the sampling state, and the first switch S 1P / S 1N Connected, the second switch S 2P / S 2N Disconnect, through the sampling capacitor unit C 1P / C 1N The VINP / VINN is sampled, and the pull-down networks of the two NOR gates are turned on, so that the contraction capacitor unit C 2P / C 2N Fully discharged; when CLK is high, the first switch S 1P / S 1N Open, the second switch S 2P / S 2N Connected, sampling capacitor unit C 1P / C 1N The charge on the shrinkage capacitor C 2P / C 2N Sharing makes V XP / V XN The voltage at the node rises quickly to V XP0 / V XN0 , realize contraction sampling; the pull-up network of the two NOR gates is turned on, and V XP0 / V XN0 Based on the voltage, a constant current is applied to the capacitor C 1P / C1N and C 2P / C 2N charging, so that the node V XP / V XN The voltage continues to rise linearly. The outputs of the two NOR gates pass through the subsequent buffers BUF_P / BUF_N to generate a relatively ideal rising edge signal, which then passes through the AND gate and the OR gate to extract the fast rising edge signal as the START signal and the slow rising edge signal as the STOP signal as the input of the time digital comparator. The timing diagram of the voltage-to-time converter is shown in the figure below. Figure 3 As shown, V TP / V TN It is a relatively ideal rising edge signal obtained after passing through the buffer. The START and STOP signals are delayed step by step in the first delay chain and the second delay chain respectively. The clocked comparator is used to judge the speed between the rising edges of the corresponding nodes in the two delay chains. When the rising edge signal output by the buffer in the first delay chain is faster than the rising edge signal output by the corresponding buffer in the second delay chain, the clocked comparator outputs 1, otherwise it outputs 0. The delay chain signal transmission diagram in the time digital comparator is shown in the figure below. Figure 7 As shown. In the first delay chain, the delay of each buffer is t d1 In the second delay chain, the delay of each buffer is t d2 If the time difference between the START and STOP signals is within the input range of the time digital comparator, due to t d1 >t d2 , the delayed signal of STOP will be ahead of the delayed signal of START. Assuming that after the delay of n buffers, the delayed signal of STOP is just ahead of the delayed signal of START, then the measured value of the time interval between the two is T = n × (t d1 -t d2 ), the first n outputs of the clocked comparator group are 1, and the subsequent outputs are 0, and the temperature code is obtained. At the same time, the resolution T of the time-to-digital converter can be obtained. LSB t d1 -t d2 The encoder ENC determines the positive or negative sign of the output signal according to the sign signal and encodes the temperature code into the corresponding binary code.

[0029] The complementary transmission gate, NAND gate, NOR gate, etc. are implemented using, but not limited to, CMOS.

[0030] like Figure 4 As shown, the inverters in the inverter array have a partial input of 0, the PMOS tube is turned on and the NMOS tube is turned off, and the other part is the opposite, the input is 1, the NMOS tube is turned on and the PMOS tube is turned off, forming a proportional circuit, which is the same as the principle of resistor voltage division, thereby generating a voltage V B, 0<V B <VDD. The gate voltage of PM1 is not directly low level 0 but V B (V B >0) is used to control the charging process to ensure that PM1 and PM2 are both in the saturation region. The cascade current source they form has a large output impedance, achieving a better constant charging current effect. In addition, the voltage V can be adjusted through CTRL_P in the case of PVT changes. B , control the charging current to cope with the changes in PVT. It should be noted that the voltage V B It should not be higher than the threshold voltage of NM1 tube to avoid charging and discharging at the same time. The same applies to the inverting input circuit.

[0031] In the time-to-digital converter, the delay of each buffer in the first delay chain is t d1 In the second delay chain, the delay of each buffer is t d2 , need to have t d1 >t d2 t can be achieved by bypassing additional buffers d1 >t d2 .like Figure 8 As shown, a buffer with a floating output is bypassed at the output node of each buffer in the first delay chain. The bypassed buffer increases the output capacitance of the previous buffer, thereby increasing the delay. This approach allows all buffers in the time-to-digital converter to be the same size.

[0032] like Figure 9 As shown, the clocked comparator is implemented in this embodiment by a dynamic circuit, including: two NAND3 gates, two inverters, and a latch connected in sequence. When CLK is low, the comparator is in a reset state, and the output nodes of the two NAND3 gates are precharged to 1, so that both outputs of the latch are 0. When CLK is high, the comparator is in an evaluation state. The truth table of the comparator is as follows:

[0033]

[0034] The input stage of the NAND3 gate changes the voltage of the output node according to VINP and VINN: when VINP is 1 and VINN is 0, the input stage of the NAND3 gate discharges the POUT_NAND3 node to 0 through positive feedback, and the NOUT_NAND3 node remains at 1. After passing through the inverter, the output Q of the latch is 1 and QN is 0; conversely, Q is 0 and QN is 1; when VINP and VINN are both 0 or 1, the clocked comparator can maintain the original output, ensuring that the encoder ENC completes the encoding and outputs the corresponding digital signal. Figure 2 and Figure 6In the structure shown, the outputs of all clocked comparators are Figure 9 The Q and QN in the circuit are left floating.

[0035] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principles and purpose of the present invention. The scope of protection of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. All implementation schemes within its scope shall be subject to the constraints of the present invention.

Claims

1. A fully synthesizable time-domain analog-to-digital converter, characterized in that include: A sampling and holding circuit, a voltage-to-time conversion circuit, and a time-to-digital conversion circuit are connected in sequence, wherein: the sampling and holding circuit converts a continuous-time voltage signal into a discrete-time voltage signal and outputs the signal to the voltage-to-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the signals to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, thereby converting the analog voltage signal into a digital signal; The sample-and-hold circuit is composed of two identical sample-and-hold sub-circuits, each of which includes: a sampling capacitor unit, a shrinking capacitor unit, a first transmission gate, and a second transmission gate, wherein: the two ends of the first transmission gate are respectively connected to the input signal and the sampling capacitor unit, and the two ends of the second transmission gate are respectively connected to the sampling capacitor unit and the shrinking capacitor unit; The voltage-to-time conversion circuit includes: a clocked comparator, two inverter arrays, two NOR gates, two buffers, an AND gate, and an OR gate, wherein: the clocked comparator compares the discrete-time voltage signals output by the sample-and-hold circuit and outputs the comparison result, namely, a sign signal to time-to-digital converter; the outputs of the first and second inverter arrays are respectively connected to one input of the corresponding NOR gate, the other input of which receives an inverted clock signal; the outputs of the two NOR gates and the outputs of the corresponding sample-and-hold circuit are respectively connected to the first and second buffers; the logical OR result of the outputs of the two buffers serves as a START signal, and the logical AND result serves as a STOP signal; The time-to-digital converter adopts a vernier delay chain structure, comprising: two parallel delay chains composed of buffers connected in series, a multi-stage clocked comparator and an encoder arranged between the two delay chains, wherein: the first delay chain and the second delay chain receive a START signal and a STOP signal, respectively. The clocked comparator compares the speed of the rising edge signal at each corresponding position in the two delay chains and outputs a temperature code. The clocked comparator's non-phase input terminal is connected to the node of the first delay chain, and the inverting input terminal is connected to the node of the second delay chain. The encoder converts the temperature code into a binary digital signal based on the sign signal from the voltage-to-time converter.

2. The fully synthesizable time-domain analog-to-digital converter according to claim 1, wherein: The two sampling capacitor units and the two shrinking capacitor units are both implemented by using a NAND gate with a grounded input terminal and a floating output terminal, and the gate capacitances of PMOS and NMOS are used as capacitors.

3. The fully synthesizable time-domain analog-to-digital converter according to claim 1, wherein: The control signals adjusted as needed are respectively used as inputs of the two inverter arrays.

4. The fully synthesizable time-domain analog-to-digital converter according to claim 1, wherein: The clocked comparator is controlled by a clock signal. When the clock signal is high, the output of the sample-and-hold circuit is compared. The output sign signal serves as the control signal of the encoder ENC in the time-to-digital converter to determine the positive or negative sign of the output, i.e., the sign signal.

5. The fully synthesizable time-domain analog-to-digital converter according to claim 1, wherein: The pull-up path of the NOR gate is two PMOS tubes forming a cascade structure, which serve as a charging path to charge the sampling capacitor unit and the contraction capacitor unit.

6. The fully synthesizable time-domain analog-to-digital converter according to claim 1, wherein: The inverter array is composed of inverters, and the output end of each inverter is connected to the input end of the corresponding PMOS transistor close to VDD of the NOR gate. The control signal CTRL_P or CTRL_N is a multi-bit signal for individually controlling the input of each inverter.

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