A media independent interface
By designing selector and detection module in the RMII interface and selecting the appropriate clock interface to receive external clocks, the problem of requiring two clock sources in the prior art is solved, and a RMII interface that can work with only one 50MHz clock source is realized. Save crystal oscillator components.
Patent Information
- Application Number
- CN202211735505.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-31
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2042-12-31
AI Technical Summary
In the prior art, two clock sources are required to implement the RMII interface, a 25MHz clock source and a 50MHz clock source. Each clock source requires a crystal oscillator. There is no working plan to implement the RMII interface using only one clock source.
Design a media independent interface, select one of the external input clock sources through the first selector and the second selector as the operating clock, and use the clock detection module and the clock configuration module to select an appropriate clock interface according to the clock frequency to receive the external input. The clock, another interface is suspended, and only one 50MHz clock source can work.
It realizes that only one 50MHz external input clock source can work, saving a crystal oscillator, simple circuit, and reducing the number of components.
Smart Images
Figure CN116094854B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of Ethernet interfaces, and in particular to a media independent interface. Background Art
[0002] Reduced Media Independent Interface (RMII) is another implementation of the IEEE802.3u standard in addition to the MII interface. The RMII interface has fewer I / O transmissions than the MII interface. It has half the signal lines for data transmission and reception than the MII interface. RMII generally does not arrange two clocks for transmission and reception for each port, but all data ports share one clock for transmission and reception of all ports, which saves a lot of ports.
[0003] In the prior art, two external clock sources are usually required, a 25MHz clock source for the internal clock of the PHY and a 50MHz clock source for the RMII interface clock. Each clock source requires a crystal oscillator, and there is currently no working solution for implementing the RMII interface using only one clock source. Summary of the invention
[0004] In order to solve the above technical problems, the present invention provides a media independent interface.
[0005] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:
[0006] A media independent interface, comprising a first clock interface for providing an input working clock to a physical layer chip, a second clock interface for providing a reference clock to the physical layer chip, and a third clock interface for providing the reference clock to a media access control chip, comprising:
[0007] A first selector, under the action of a clock detection signal, selects one of the external input clock from the first clock interface and the frequency division signal of the external input clock, and outputs a first selection result;
[0008] A second selector, connected to the first selector, selects one of the external input clock from the second clock interface and the first selection result under the action of a configuration signal, and outputs a second selection result;
[0009] A clock selection module, connected to the first clock interface and the second clock interface respectively, and selecting the external input clock received by a clock interface as the working clock of the media independent interface under the action of a clock detection signal and / or a clock configuration signal;
[0010] Among them, one of the first clock interface and the second clock interface receives the external input clock, and the other clock interface is left floating.
[0011] Preferably, the clock detection signal is generated by a clock detection module, and the clock detection module is used to detect the clock frequency received by the first clock interface under the action of a crystal oscillator clock when the first clock interface receives the external input clock, and output the clock detection signal according to the detected clock frequency.
[0012] Preferably, the clock detection module includes:
[0013] A counting unit, used for counting the number of rising edges of the crystal oscillator clock to obtain a first count, and for counting the number of rising edges of the external input clock to obtain a second count;
[0014] A comparison and judgment unit is connected to the statistical unit and is used to compare the ratio of the first count to the second count with a preset threshold value, and obtain the clock frequency according to the comparison result.
[0015] Preferably, when the detected clock frequency is 50 MHz, the clock detection signal is at a high level; and
[0016] When the detected clock frequency is 25 MHz, the clock detection signal is at a low level.
[0017] Preferably, the clock configuration signal is generated by a clock configuration module, and the clock configuration module is used for a user to configure the first clock interface or the second clock interface as a receiving end of the external input clock.
[0018] Preferably, when the first clock interface is configured to receive the external input clock, the clock configuration signal is at a low level; and
[0019] When the second clock interface is configured to receive the external input clock, the clock configuration signal is at a high level.
[0020] Preferably, the clock selection module selects the external input clock received by the first clock interface as the working clock of the media independent interface when the clock configuration signal is at a low level and the clock detection signal is at a high level; otherwise, the clock selection module selects the external input clock received by the second clock interface as the working clock of the media independent interface.
[0021] Preferably, the external input clock is 50 MHz.
[0022] The advantages or beneficial effects of the technical solution of the present invention are:
[0023] The present invention receives an external input clock through one of the first clock interface and the second clock interface, and the other interface is suspended, and only a 50MHz external input clock is needed as a clock source, thereby saving a crystal oscillator and simplifying the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a connection diagram of the RMII interface in the prior art;
[0025] Figure 2 A connection diagram of the RMII interface in a preferred embodiment of the present invention;
[0026] Figure 3 A connection diagram of the RMII interface in another preferred embodiment of the present invention;
[0027] Figure 4 FIG. 4 is a schematic diagram of a RMII interface clock circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0030] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.
[0031] See also Figure 2-Figure 4 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a media independent interface is provided, including a first clock interface XI for providing an input working clock to a physical layer chip (PHY), a second clock interface TXC for providing a reference clock to the physical layer chip, and a third clock interface REF_CLK for providing a reference clock to a media access control chip (MAC), including:
[0032] A first selector 1 selects one of the external input clock from the first clock interface XI and the frequency division signal of the external input clock under the action of a clock detection signal, and outputs a first selection result;
[0033] The second selector 2 is connected to the first selector 1, selects one of the external input clock from the second clock interface TXC and the first selection result under the action of a configuration signal, and outputs the second selection result;
[0034] The clock selection module 3 is connected to the first clock interface XI and the second clock interface TXC respectively, and selects an external input clock received by a clock interface as a working clock of the media independent interface under the action of a clock detection signal and / or a clock configuration signal;
[0035] Among them, one of the first clock interface XI and the second clock interface TXC receives an external input clock, and the other clock interface is set to be suspended.
[0036] As a preferred embodiment, the clock detection signal is generated by a clock detection module 4, and the clock detection module 4 is used to detect the clock frequency received by the first clock interface XI under the action of a crystal oscillator clock when the first clock interface XI receives an external input clock, and output the clock detection signal according to the detected clock frequency.
[0037] As a preferred implementation, the clock detection module 4 includes:
[0038] A counting unit, used for counting the number of rising edges of the crystal oscillator clock to obtain a first count, and for counting the number of rising edges of the external input clock to obtain a second count;
[0039] The comparison and judgment unit is connected to the statistical unit and is used to compare the ratio of the first count and the second count with a preset threshold value, and obtain the clock frequency according to the comparison result.
[0040] As a preferred implementation, when the detected clock frequency is 50 MHz, the clock detection signal is at a high level; and
[0041] When the detected clock frequency is 25 MHz, the clock detection signal is at a low level.
[0042] As a preferred implementation, the clock configuration signal is generated by a clock configuration module 5, and the clock configuration module 5 is used for the user to configure the first clock interface XI or the second clock interface TXC as a receiving end of the external input clock.
[0043] As a preferred implementation, when the first clock interface X1 is configured to receive an external input clock, the clock configuration signal is at a low level; and
[0044] When the second clock interface TXC is configured to receive an external input clock, the clock configuration signal is at a high level.
[0045] As a preferred implementation, the clock selection module selects the external input clock received by the first clock interface XI as the working clock of the media independent interface when the clock configuration signal is at a low level and the clock detection signal is at a high level, otherwise it selects the external input clock received by the second clock interface TXC as the working clock of the media independent interface.
[0046] As a preferred implementation, the external input clock is 50 MHz.
[0047] like Figure 2 As shown, it is a preferred embodiment of the present invention, wherein the first clock interface XI is suspended, and the second clock interface TXC and the third clock interface REF_CLK simultaneously receive external input clocks to provide working clocks for the RMII interface.
[0048] like Figure 3 As shown, it is another preferred embodiment of the present invention, wherein the second clock interface TXC is set to be suspended, and the first clock interface XI and the third clock interface REF_CLK simultaneously receive external input clocks to provide working clocks for the RMII interface.
[0049] like Figure 4 As shown in FIG. 1 , a schematic diagram of clock implementation of the above two connection modes in a preferred embodiment of the present invention is shown. The meaning of the signals in the figure is explained as follows:
[0050] Clk_xtl: The clock input from the first clock interface XI, which can be connected to a 50MHz clock source or not;
[0051] Clk_txc: The clock input from the second clock interface TXC, which can be connected to a 50MHz clock source or not;
[0052] Clk_ref: indicates the reference clock of the chip, which is generally 25MHz. The reference clock is used to generate the working clocks of different frequencies inside the chip.
[0053] Clk_osc: The crystal clock generated by the internal oscillator of the chip is generally 2.2MHz, which is used by the clock detection module 4 to detect whether the first clock interface XI receives a 25MHz clock source or a 50MHz clock source. If the received clock source is 25MHz, the RMII interface is connected in a conventional way. If the received clock source is 50MHz, only one clock source is received.
[0054] Clk_rmii: The working clock in RMII mode, its frequency is fixed at 50MHz.
[0055] Furthermore, the clock configuration module 5 controls the use of the clock clk_txc input from the first clock interface XI or the clock clk_xtl input from the second clock interface TXC as the clock source through a register or an external pin of the chip.
[0056] Specifically, the clock detection module detects whether clk_xtl is a 25MHz clock source or a 50MHz clock source. The implementation method is: within a period of time, such as 550us, the number of rising edges of clk_osc and clk_xtl are counted respectively. If clk_xtl is 25MHz, the ratio of its rising edge number to the number of rising edges of clk_osc is 11.36:1; if clk_xtl is 50MHz, the ratio of its rising edge number to the number of rising edges of clk_osc is 22.72:1. By setting a threshold as a preset threshold, for example, the preset threshold is 17, when it is greater than the preset threshold, it is judged that clk_xtl is 50MHz, otherwise it is 25MHz.
[0057] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.
Claims
1. A media independent interface, comprising a first clock interface for providing an input working clock to a physical layer chip, a second clock interface for providing a reference clock to the physical layer chip, and a third clock interface for providing the reference clock to a media access control chip, characterized in that: include: A first selector, under the action of a clock detection signal, selects one of the external input clock from the first clock interface and the frequency division signal of the external input clock, and outputs a first selection result; A second selector, connected to the first selector, selects one of the external input clock from the second clock interface and the first selection result under the action of a clock configuration signal, and outputs a second selection result; A clock selection module, connected to the first clock interface and the second clock interface respectively, and selecting the external input clock received by a clock interface as the working clock of the media independent interface under the action of the clock detection signal and / or the clock configuration signal; Among them, one of the first clock interface and the second clock interface receives the external input clock, and the other clock interface is left floating.
2. The media independent interface according to claim 1, characterized in that: The clock detection signal is generated by a clock detection module, and the clock detection module is used to detect the clock frequency received by the first clock interface under the action of a crystal oscillator clock when the first clock interface receives the external input clock, and output the clock detection signal according to the detected clock frequency.
3. The media independent interface according to claim 2, characterized in that: The clock detection module comprises: A counting unit, used for counting the number of rising edges of the crystal oscillator clock to obtain a first count, and for counting the number of rising edges of the external input clock to obtain a second count; A comparison and judgment unit is connected to the statistical unit and is used to compare the ratio of the first count to the second count with a preset threshold value, and obtain the clock frequency according to the comparison result.
4. The media independent interface according to claim 2, characterized in that: When the detected clock frequency is 50 MHz, the clock detection signal is at a high level; and When the detected clock frequency is 25 MHz, the clock detection signal is at a low level.
5. The media independent interface according to claim 1, characterized in that: The clock configuration signal is generated by a clock configuration module, and the clock configuration module is used for a user to configure the first clock interface or the second clock interface as a receiving end of the external input clock.
6. The media independent interface according to claim 5, characterized in that: When the first clock interface is configured to receive the external input clock, the clock configuration signal is at a low level; and When the second clock interface is configured to receive the external input clock, the clock configuration signal is at a high level.
7. The media independent interface according to claim 1, characterized in that: The clock selection module selects the external input clock received by the first clock interface as the working clock of the media independent interface when the clock configuration signal is at a low level and the clock detection signal is at a high level; otherwise, the clock selection module selects the external input clock received by the second clock interface as the working clock of the media independent interface.
8. The media independent interface according to claim 1, characterized in that: The external input clock is 50 MHz.