Pixel circuit, control method, and image sensor

Abstract

The application belongs to the technical field of semiconductor devices, and relates to a pixel circuit, a control method and an image sensor, which comprise: at least two pixel units arranged in an array, each pixel unit comprising at least two pixels; the transfer transistors of the at least two pixels in at least one pixel unit are connected with a corresponding first group of transfer control lines, and the transfer transistors in other pixel units are connected with a corresponding second group of transfer control lines. The pixel circuit, the control method and the image sensor provided by the application can control the phase focusing density of the image sensor by controlling the time sequence of the first group of transfer control lines and the second group of transfer control lines, without changing the structure of the pixels, and the structure is simple and the optical performance is good.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a pixel circuit, control method and image sensor. Background Technology

[0002] With the development of image sensor technology, the application fields of image sensors are becoming more and more extensive. For example, image sensors can be used in medical radiation imaging, industrial flaw detection, security inspection and other fields.

[0003] Current image sensors do not allow adjustment of phase detection autofocus density, therefore, it is impossible to switch the phase detection autofocus density according to the specific scene.

[0004] Those skilled in the art have been seeking solutions to the above problems.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] The technical problem to be solved by this application is to provide a pixel circuit, a control method and an image sensor to address the deficiencies of the prior art, so as to achieve switching of phase focusing density while ensuring optical performance.

[0007] This application is implemented as follows:

[0008] This application provides a pixel circuit, including at least two pixel units, wherein the at least two pixel units are arranged in an array.

[0009] Each pixel unit comprises at least two pixels. Each pixel includes a photoelectric conversion element and a transfer transistor. The photoelectric conversion element is used to generate charge in response to incident light. The transfer transistor is coupled between the photoelectric conversion element and a floating diffusion node, and is used to transfer the charge accumulated in the photoelectric conversion element during exposure to the floating diffusion node according to a transfer control signal. At least one pixel in at least one pixel unit has its transfer transistor connected to a corresponding first set of transfer control lines, which includes at least one transfer control line, with one pixel corresponding to one transfer control line. The transfer transistors in other pixels are connected to a corresponding second set of transfer control lines.

[0010] Optionally, at least two pixels in the same pixel unit share a single on-chip lens.

[0011] Optionally, the number of transmission control lines in the first group of transmission control lines is less than or equal to the number of pixels in the corresponding pixel unit.

[0012] Optionally, the number of transmission control lines in the first group of transmission control lines is greater than the number of pixels in the corresponding pixel unit.

[0013] Optionally, each row of pixel units is provided with a corresponding first set of transmission control lines and a corresponding second set of transmission control lines.

[0014] Optionally, when the phase focus density is 100%, the timing of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is the same; when the phase focus density is not 100%, the timing of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is different.

[0015] Optionally, each pixel unit includes four pixels, and the four pixels in the same pixel unit share a single on-chip lens. The first group of transmission control lines corresponding to each row of pixel units includes four transmission control lines. The transmission transistors of the four pixels in the pixel unit connected to the first group of transmission control lines are respectively connected to the four transmission control lines in the corresponding first group of transmission control lines.

[0016] Optionally, when the phase focus density is not 100%, the timing of the first sub-transmission control line and the second sub-transmission control line receiving the effective level transmission control signal in the first group of transmission control lines is staggered to obtain left and right phase information and / or up and down phase information. The four transmission control lines in the second group of transmission control lines receive the effective level transmission control signal to obtain image information. The first sub-transmission control line is the two transmission control lines connecting the first pair of adjacent pixels among the four pixels, and the second sub-transmission control line is the two transmission control lines connecting the second pair of pixels among the four pixels excluding the first pair of pixels.

[0017] Optionally, in the same row of pixel units, two pixel units connected to the first set of transmission control lines are separated by at least one pixel unit.

[0018] Optionally, the pixel units in the nth row of the pixel circuit are arranged cyclically according to the first green and blue color filters, and the pixel units in the (n+1)th row are arranged cyclically according to the red and second green color filters; or, each pixel unit group includes four pixel units arranged in an array, and the four pixel units in each pixel unit group correspond to the first green, blue, second green and red color filters respectively in a clockwise direction; wherein, the pixel unit connected to the first group of transmission control lines is set at the position corresponding to the first green.

[0019] Optionally, in the same row of pixel units, two pixel units connected to the first set of transmission control lines are separated by at least one pixel unit.

[0020] Optionally, the pixel circuit further includes:

[0021] A reset transistor is coupled between a first voltage source and the floating diffusion node; and / or,

[0022] An amplification output unit, coupled to the floating diffusion node, is used to amplify and output the voltage signal of the floating diffusion node; and / or,

[0023] A dual-conversion gain control unit, coupled between the reset transistor and the floating diffuse node, is used to implement gain control; and / or,

[0024] A row selection transistor is coupled between the output terminal of the amplification output unit and the column output line. The gate of the row selection transistor receives a row selection control signal and is used to output the voltage signal of the floating diffusion node.

[0025] This application also provides an image sensor, including the pixel circuit described above.

[0026] This application also provides a control method for the above-mentioned pixel circuit, the control method comprising: acquiring image information based on the first set of transmission control lines and the second set of transmission control lines; or, acquiring phase focus information based on the first set of transmission control lines and the second set of transmission control lines; or, acquiring phase focus information based on the first set of transmission control lines and acquiring image information based on the second set of transmission control lines.

[0027] Optionally, the control method includes single-row reading or parallel reading, wherein: during the reading process, phase focus information is obtained based on different pixels in the same pixel unit connected to the first group of transmission control lines; or, phase focus information is obtained based on pixel units in different rows of pixel units connected to the first group of transmission control lines.

[0028] Optionally, the method of obtaining phase focus information based on different pixel unit rows includes: the pixel array having a first focus pixel row with first pixel units connected to a first group of transmission control lines, and a second focus pixel row with second pixel units connected to a first group of transmission control lines, wherein first focus information is obtained based on the first focus pixel row, and second focus information is obtained based on the second focus pixel row to obtain phase focus information.

[0029] This application provides a pixel circuit, a control method, and an image sensor, wherein at least two pixels in at least one pixel unit have their transmission transistors connected to a corresponding first set of transmission control lines, and the transmission transistors in other pixels are connected to a corresponding second set of transmission control lines. Therefore, the pixel circuit, control method, and image sensor provided in this application can control the phase focusing density of the image sensor by controlling the first and second sets of transmission control lines without changing the pixel structure, resulting in a simple structure and good optical performance.

[0030] To make the above and other objects, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of the structure of a pixel unit in a pixel circuit provided in an embodiment of this application;

[0033] Figure 3 This is a circuit diagram of a pixel unit in a pixel circuit provided in an embodiment of this application;

[0034] Figure 4 This is a timing diagram of a pixel unit in a pixel circuit provided in an embodiment of this application;

[0035] Figure 5 This is a timing diagram of another pixel unit in a pixel circuit provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram illustrating the effect of an image sensor according to an embodiment of the present application in achieving a phase-detection autofocus mode with 100% upper and lower phase information density.

[0037] Figure 7 This is a schematic diagram illustrating the effect of an image sensor according to an embodiment of this application in achieving a phase-detection autofocus mode with 100% phase information density in the top, bottom, left, and right directions.

[0038] Figure 8a This is a timing diagram of the image sensor of the first embodiment of this application when achieving an upper and lower phase information density of 6%;

[0039] Figure 8b This is a timing diagram of the image sensor according to the second embodiment of this application when achieving an upper and lower phase information density of 6%;

[0040] Figure 8c This is a timing diagram of the image sensor according to the third embodiment of this application when achieving an upper and lower phase information density of 6%;

[0041] Figure 9 This is a timing diagram of an image sensor according to an embodiment of the present application when achieving a left and right phase information density of 6%;

[0042] Figure 10 This is an image sensor according to an embodiment of this application. Specific Implementation

[0043] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0044] This application provides a pixel circuit, which includes at least two pixel units arranged in an array, each pixel unit including:

[0045] At least two pixels, each pixel including a photoelectric conversion element and a transfer transistor, the photoelectric conversion element being used to accumulate charge generated by the photoelectric effect in response to incident light, the photoelectric conversion element including but not limited to a photodiode PD; the transfer transistor being coupled between the photoelectric conversion element and a floating diffusion node, being used to transfer the charge accumulated by the photoelectric conversion element during exposure to the floating diffusion node according to a transfer control signal;

[0046] A reset transistor, coupled between a first voltage source and a floating diffusion node, is used to reset the voltage of the floating diffusion node according to a reset control signal.

[0047] An amplification output unit, coupled to a floating diffusion node, is used to amplify and output the voltage signal of the floating diffusion node;

[0048] In one embodiment, at least one pixel in at least one pixel unit has its transmission transistor connected to a corresponding first set of transmission control lines to obtain the focusing information required for phase-detection autofocus. In another embodiment, at least two pixels in at least one pixel unit have their transmission transistors connected to a corresponding first set of transmission control lines. The first set of transmission control lines includes at least one transmission control line, with one pixel corresponding to one transmission control line; the transmission transistors in the other pixel units are connected to a corresponding second set of transmission control lines, which are different from the first set of transmission control lines.

[0049] According to one embodiment of this application, the amplified output unit includes a source follower transistor, the gate of which is coupled to the floating diffusion node, the drain of which is coupled to a second voltage source, and the source of which is coupled to the row select transistor as an output terminal.

[0050] The first voltage source and the second voltage source can be the same voltage source, so that the reset transistor and the source follower transistor are simultaneously connected to the same voltage source. Of course, the first voltage source and the second voltage source can also be different voltage sources, and the reset transistor and the source follower transistor are connected separately.

[0051] In one embodiment, the pixel circuit further includes a dual-conversion gain control unit coupled between the reset transistor and the floating diffusion node for gain control.

[0052] As a specific embodiment, the dual-conversion gain control unit includes a dual-conversion gain control transistor and a dual-conversion gain capacitor. The dual-conversion gain control transistor is coupled between a reset transistor and a floating diffusion node. The first terminal of the dual-conversion gain capacitor is coupled to the node between the dual-conversion gain transistor and the reset transistor, and the second terminal of the dual-conversion gain capacitor is connected to a specified level or ground.

[0053] In one embodiment, the pixel circuit further includes a row selection transistor coupled between the output terminal of the amplification output unit and the column output line. The gate of the row selection transistor receives a row selection control signal for outputting a voltage signal of the floating diffusion node.

[0054] In one embodiment, at least two pixels in the same pixel unit share a single on-chip lens. For example, four pixels may share a single on-chip lens. In a further embodiment, a pixel unit may include four pixels, and the four pixels in the same pixel unit share the same on-chip lens. In other embodiments, a pixel unit may include two pixels, and the two pixels in the same pixel unit share the same on-chip lens. In one embodiment, all pixels in the same pixel unit share a single on-chip lens.

[0055] In one embodiment, the number of transmission control lines in the first group of transmission control lines corresponding to each row of pixel units is equal to the number of pixels in each pixel unit, and there is a one-to-one correspondence between pixels and transmission control lines. Of course, in other embodiments, the number of transmission control lines in the first group of transmission control lines may be less than the number of pixels in the corresponding pixel unit. For example, a pixel unit may include four pixels, where two pixels are connected to the first group of transmission control lines and the other two are connected to the second group of transmission control lines.

[0056] In one embodiment, when the phase focus density is 100%, the timing of the transmission control signals received by the first set of transmission control lines and the second set of transmission control lines is the same; when the phase focus density is not 100%, the timing of the transmission control signals received by the first set of transmission control lines and the second set of transmission control lines is different.

[0057] In one embodiment, each pixel unit includes four pixels, and the four pixels in the same pixel unit share a single on-chip lens. The first group of transmission control lines corresponding to each row of pixel units includes four transmission control lines. In this embodiment, the transmission transistors of the four pixels in at least one pixel unit are respectively connected to the four transmission control lines in the corresponding first group of transmission control lines.

[0058] In one embodiment, when the phase focus density is not 100%, the timing of the first sub-transmission control line and the second sub-transmission control line receiving the effective level transmission control signal in the first group of transmission control lines is staggered to obtain left-right phase information and / or top-bottom phase information. The four transmission control lines in the second group of transmission control lines simultaneously receive the effective level transmission control signal to obtain image information. The first sub-transmission control line includes two transmission control lines connecting adjacent first pairs of pixels among the four pixels, and the second sub-transmission control line includes two transmission control lines connecting second pairs of pixels among the four pixels, excluding the first pair.

[0059] The pixel circuit provided in this application includes at least two pixel units. All pixels in each pixel unit share a reset transistor, an amplification output unit, and a row selection transistor, thereby saving chip area and facilitating device miniaturization. Furthermore, the transmission transistors of at least two pixels in at least one pixel unit are connected to a first set of transmission control lines, while the transmission transistors in other pixels are connected to corresponding second sets of transmission control lines. This allows the phase focusing density of the image sensor to be controlled by controlling the first and second sets of transmission control lines without altering the pixel structure, resulting in a simple structure and good optical performance. In addition, at least two pixels in the same pixel unit share a single on-chip lens, avoiding mutual interference between pixels. The number of transmission control lines in the first set corresponding to each row of pixel units can be set to be equal to the number of pixels in each pixel unit, enabling the acquisition of left-right phase information and / or top-bottom phase information while switching between different phase focusing densities, further improving flexibility.

[0060] The following detailed description of the solution in this application is based on several specific embodiments.

[0061] Example 1

[0062] Please see Figure 1 , Figure 2 and Figure 3 ,like Figure 1 As shown, the pixel circuit provided in this embodiment includes N pixel units ( Figure 1 The diagram shows 8×4 pixel units (but this application is not limited to this), and N pixel units are arranged in an array, where N is a positive integer and N≥2.

[0063] like Figure 2 As shown, in one embodiment, each pixel unit includes four pixels ①, ②, ③, and ④, but this application is not limited to this. In one embodiment, the four pixels ①, ②, ③, and ④ correspond to one on-chip lens; in other embodiments, two pixels may share one on-chip lens, etc.

[0064] In this configuration, at least two pixels in at least one pixel unit have their transmission transistors connected to a first set of transmission control lines, while the transmission transistors of the other pixels are connected to a second set of transmission control lines. The first set of transmission control lines includes at least one transmission control line, with one pixel corresponding to one transmission control line. It is permissible for one pixel to be connected to only one transmission control line, and one transmission control line may connect to pixels in different pixel units.

[0065] In one embodiment, each row of pixel units is provided with a corresponding first set of transmission control lines and a corresponding second set of transmission control lines. In an optional example, for a pixel unit connected to the first set of transmission control lines, some pixels are connected to the first set of transmission control lines, and the remaining pixels are connected to the second set of transmission control lines.

[0066] In this embodiment, each pixel unit includes four pixels, and each row of pixel units corresponds to eight transmission control lines. Taking the pixel unit in the nth row as an example, it corresponds to four transmission control lines txap<n>, txbp<n>, txcp<n>, and txdp<n> (forming the first group of transmission control lines), and four transmission control lines txa<n>, txb<n>, txc<n>, and txd<n> (forming the second group of transmission control lines).

[0067] The first pixel ① of all pixel units in the nth row is connected to the first transmission control line txa<n> in the second group of transmission control lines, the second pixel ② is connected to the second transmission control line txb<n> in the second group of transmission control lines, the third pixel ③ is connected to the third transmission control line txc<n> in the second group of transmission control lines, and the fourth pixel ④ is connected to the fourth transmission control line txd<n> in the second group of transmission lines.

[0068] like Figure 1 As shown, in this embodiment, the transmission transistors of the four pixels in the second and sixth columns of the n+2th row are connected to the first set of transmission control lines txap, txbp, txcp, and txdp, respectively. The transmission transistors of the remaining pixel units are connected to the second set of transmission control lines txa, txb, txc, and txd. In other embodiments, the number and position of the pixel units connected to the first set of transmission control lines can be adjusted as needed, and this application is not limited thereto.

[0069] In one embodiment, the number of transmission control lines in the first group of transmission control lines is less than or equal to the number of pixels in the corresponding pixel unit. In other embodiments, the number of transmission control lines in the first group of transmission control lines is greater than the number of pixels in the corresponding pixel unit. In this case, the number of transmission control lines in the same row of pixel units may be greater than the number of pixels in the pixel unit. In this case, the pixels in the pixel unit can be connected to the corresponding transmission control lines according to the actual design.

[0070] As an example, for pixel units connected to the first group of transmission control lines in the same row, the first group of transmission control lines can be divided into several parts, wherein the control lines in different parts can be completely different or can overlap between each other; a pixel unit selects one of the several parts to connect.

[0071] For example, the four pixels in the first pixel unit can be connected to four of the six transmission control lines, while the four pixels in the second pixel unit in the same row can be selected to connect to the remaining two control lines. Alternatively, the four pixels in another second pixel unit can be connected to the remaining two control lines, and two of the four control lines connected to the first pixel unit can be selected to connect to the pixel. Based on the above method, a flexible design for relative focusing pixels can be achieved.

[0072] Each pixel includes a photoelectric conversion element and a transmission transistor, such as Figure 3 As shown, each pixel unit comprises four pixels, including photoelectric conversion elements PD1, PD2, PD3, PD4, and transfer transistors TXA, TXB, TXC, and TXD. The photoelectric conversion elements PD1, PD2, PD3, and PD4 are used to accumulate charge generated by the photoelectric effect in response to incident light. The transfer transistors TXA, TXB, TXC, and TXD are coupled between the corresponding photoelectric conversion elements PD1, PD2, PD3, and PD4 and the floating diffusion node FD, respectively, and are used to transfer the charge accumulated by the corresponding photoelectric conversion elements PD1, PD2, PD3, and PD4 during exposure to the floating diffusion node FD according to the transfer control signals txa, txb, txc, tcd or txap, txbp, txcp, txdp. The four pixels in a single pixel unit can share one floating diffusion node FD, or two adjacent pixels can share one floating diffusion node. The resulting nodes FD1 and FD2 are simultaneously electrically connected to the gate of the source follower transistor SF, and the output circuit simultaneously outputs the signals corresponding to the two nodes FD1 and FD2. Specifically, the anodes of photoelectric conversion elements PD1, PD2, PD3, and PD4 are connected to ground, and their cathodes are coupled to the floating diffusion node FD through the corresponding transmission transistors TXA, TXB, TXC, and TXD.

[0073] The reset transistor RST is coupled between the first voltage source Vrab and the floating diffusion node FD, and is used to reset the voltage of the floating diffusion node FD according to the reset control signal rst.

[0074] The amplification output unit is coupled to the floating diffusion node FD and is used to amplify and output the voltage signal of the floating diffusion node FD. Specifically, in this embodiment, the amplification output unit includes a first source follower transistor SF. The gate of the first source follower transistor SF is coupled to the floating diffusion node FD, its drain is coupled to a second voltage source Vrsf, and its source is coupled to the row select transistor as the output terminal. Of course, this embodiment only illustrates one implementation of the amplification output unit. Those skilled in the art should realize that the amplification output unit can also use other amplification devices with different gains to replace the source follower transistor SF. For example, two-stage or multi-stage amplifiers can be used to replace the source follower transistor SF in this embodiment. These variations are also within the protection scope of this application.

[0075] In one embodiment, the pixel circuit further includes a dual-conversion gain control unit coupled between a reset transistor RST and a floating diffusion node FD, for gain control. In a specific embodiment, the dual-conversion gain control unit includes a dual-conversion gain control transistor DCG and a dual-conversion gain capacitor Cdcg. The dual-conversion gain control transistor DCG is coupled between the reset transistor RST and the floating diffusion node FD. A first terminal of the dual-conversion gain capacitor Cdcg is coupled to the node between the dual-conversion gain transistor DCG and the reset transistor RST, and a second terminal of the dual-conversion gain capacitor Cdcg is connected to a specified voltage level.

[0076] In a preferred embodiment, the pixel circuit provided in this embodiment further includes a row selection transistor RS, which is coupled between the output terminal of the amplification output unit (e.g., the source of the first source follower transistor SF) and the column output line. Its gate receives a control signal rs, used to output the voltage signal of the floating diffusion node FD in the rolling exposure mode. It should be noted that the row selection transistor RS is included as a preferred embodiment, and implementation of this application does not necessarily require the inclusion of a row selection transistor RS.

[0077] The reset transistor RST, transfer transistor TX, first source follower transistor SF, row selection transistor RS, and dual conversion gain control transistor DCG are all NMOS, N = 8 × 4. The transfer transistors of the four pixels ①②③④ in the second and sixth columns of the n+2th row are connected to the first transfer control line txap, the second transfer control line txbp, the third transfer control line txcp, and the fourth transfer control line txdp in the first group of transfer control lines, respectively. The transfer transistors of the remaining pixel units in the n+2th row are connected to the first transfer control line txa, the second transfer control line txb, the third transfer control line txc, and the fourth transfer control line txd in the second group of transfer control lines. Their control timing is as follows: Figure 4 The image sensor in this embodiment is illustrated using the example shown below. Its specific working process is as follows:

[0078] 1. At time t0, the row selection signal rs is set to high level, and the quantization circuit is ready to quantize the data of the corresponding row;

[0079] 2. At time t1, the reset signal rst and the dual-conversion gain selection signal dcg are set to low level to obtain the corresponding image reset signal; of course, in other embodiments, the dual-conversion gain selection signal dcg can also be set to high level.

[0080] 3. At time t2, the first transmission control lines txap and txa in the first group of transmission control lines and the second transmission control lines txbp and txb in the first group of transmission control lines and the second group of transmission control lines are all set to high level. The transmission transistors TXA and TXB in the first pixel ① and the second pixel ② in all pixel units in the n+2th row are turned on, and all pixel units in the n+2th row begin to transmit the upper phase information.

[0081] 4. At time t3, the first transmission control lines txap and txa in the first group of transmission control lines and the second transmission control lines txbp and txb in the first group of transmission control lines and the second group of transmission control lines are all set to low level. All pixel units in the (n+2)th row end the transmission of upper phase information. The quantized upper phase information VTPD can be obtained by quantization through the quantization circuit.

[0082] 5. At time t4, the third transmission control lines txcp and txc in the first group of transmission control lines and the fourth transmission control lines txdp and txd in the first group of transmission control lines and the second group of transmission control lines are all set to high level. The transmission transistors TXC and TXD in the third pixel ③ and the fourth pixel ④ in all pixel units in the n+2th row are turned on, and all pixel units in the n+2th row begin to transmit the next phase information.

[0083] 6. At time t5, the first group of transmission control lines and the third transmission control lines txcp and txc in the second group of transmission control lines, as well as the fourth transmission control lines txdp and txd in the first group of transmission control lines and the second group of transmission control lines, are all set to low level. All pixel units in the (n+2)th row end the transmission of the next phase information. If the two phase information are summed at the floating diffusion node fd, and then quantized again through the quantization circuit, the image information Vsum is obtained.

[0084] 7. At time t6, the reset signal rst and the double conversion gain selection signal dcg are set to high level to reset the floating diffusion node fd;

[0085] 8. At time t7, the row selection signal rs is set to low level, ending the current row quantization.

[0086] Through digital calculation, the lower phase information VLPD = Vsum - VTPD can be obtained. Thus, the n+2th row of pixel units in the image sensor of this embodiment can realize the upper and lower phase focusing mode.

[0087] In other embodiments, a reset operation, where the reset signal rst or the dual-conversion gain selection signal dcg is set high and then low, can be added between time t3 and time t4. This ensures that the quantization circuit quantizes the individual lower phase information again at time t5, rather than the summed Vsum. Furthermore, it should be noted that based on the above control principle, other focusing data for phase-detection autofocus can also be obtained based on txap, txbp, txcp, and txdp. Additionally, the timing correspondence between txap, txbp, txcp, txdp and txa, txb, txc, and tcd can be designed according to actual requirements.

[0088] Figure 5 This is a timing diagram of another pixel unit in a pixel circuit provided in one embodiment of this application. Please also refer to... Figure 5 , Figure 2 and Figure 3At time t2, by setting the first transmission control lines txap and txa, and the third transmission control lines txcp and txc of the first and second sets of transmission control lines corresponding to a certain pixel unit to a high level, the transmission transistors TXA and TXC in the first pixel ① and the third pixel ③ of this pixel unit are turned on, causing this pixel unit to start transmitting right phase information. Then, at time t3, by setting the first transmission control lines txap and txa, and the third transmission control lines txcp and txc of the first and second sets of transmission control lines corresponding to this pixel unit to a low level, the right phase information transmission of this pixel unit ends. The quantized right phase information can be obtained through quantization. The principle for obtaining the quantized left phase information is similar to that for obtaining the right phase information, and will not be repeated here.

[0089] Figure 6 This is a schematic diagram illustrating the effect of an image sensor according to an embodiment of this application in achieving a phase-detection autofocus mode with 100% upper and lower phase information density. If each pixel unit in the pixel array is achieved through... Figure 4 The timing control quantization shown yields upper phase information 10a and lower phase information 10b, thus enabling a phase-detection autofocus mode with 100% upper and lower phase information density. Figure 6 Only a 4×4 array is shown, but this application is not limited to this. The upper phase information 10a and lower phase information 10b are used for phase focusing. In one embodiment, Figure 6 The effect shown can be based on Figure 4 The readout timing implementation.

[0090] Figure 7 This is a schematic diagram illustrating the effect of an image sensor according to an embodiment of this application in achieving a phase-detection autofocus mode with 100% phase information density in all directions. Figure 7 As shown, the 4x2 pixel array in the 4x4 pixel array is obtained through... Figure 4 Timing-controlled quantization yields the corresponding image information 10, right phase information 10a, and left phase information 10b. The 4x2 pixel array is processed by... Figure 6 Timing control quantization yields corresponding image information 20, right phase information 20a, and left phase information 20b. The image information is used for imaging, while the left and right phase information, and the top and bottom phase information, are used for phase focusing. For example... Figure 7As shown, in one embodiment, in a phase-detection autofocus mode with 100% density, the pixel units used to acquire left-right phase information and up-down phase information each account for 50%. In other embodiments, the proportion and acquisition position of the pixel units used to acquire left-right and up-down phase information in the entire pixel array can be configured according to phase-detection autofocus requirements. In one implementation, Figure 7 The effect shown can be based on Figure 4 and Figure 5 It is achieved by combining the readout timing.

[0091] Figure 8a This is a timing diagram illustrating the image sensor of the first embodiment of this application when achieving a 6% upper and lower phase information density. Please also refer to... Figure 1 and Figure 8a ,like Figure 1 As shown, in this 4×8 pixel array, the transmission transistors of the four pixels in the second and sixth columns of the n+2th row are connected to the first set of transmission control lines txap, txbp, txcp, and txdp, respectively, while the transmission transistors of the remaining pixel units are connected to the second set of transmission control lines txa, txb, txc, and txd.

[0092] Therefore, in such Figure 8a Under the control of the timing signal shown, the pixel units in the 2nd and 6th columns of the (n+2)th row are used to acquire top and bottom phase information, while the remaining pixel units are used to acquire normal image information. For the specific implementation principle, please refer to the description above; it will not be repeated here. Therefore, in... Figure 8a Under the control of the timing signal shown, this application can achieve a density of 2 / 4×8, which is approximately equal to 6% phase focus mode.

[0093] In other embodiments, the timing of the first transmission control line txap and the third transmission control line txcp in the first group of transmission control lines txap, txbp, txcp, and txdp can be set to be the same, and the timing of the second transmission control line txbp and the fourth transmission control line txdp can be set to be the same, so as to achieve a phase focusing mode with a left and right phase information density of 6%.

[0094] Figure 8b This is a timing diagram illustrating the image sensor of the second embodiment of this application when achieving a 6% upper and lower phase information density. Please also refer to... Figure 1 and Figure 8b ,like Figure 1As shown, in this 4×8 pixel array, the transmission transistors of the four pixels in the second and sixth columns of the n+2th row are connected to the first set of transmission control lines txap, txbp, txcp, and txdp, respectively, while the transmission transistors of the remaining pixel units are connected to the second set of transmission control lines txa, txb, txc, and txd.

[0095] Therefore, in such Figure 8b Under the control of the timing signal shown, the two pixel units in the 2nd and 6th columns of the (n+2)th row can be used to obtain the up and down phase information. The remaining pixel units, although... Figure 8b The timing signals shown can also be used to acquire upper and lower phase information under control, but the readout circuit (not shown in the figure) may not use the remaining pixel units for phase focusing. Therefore, in situations such as Figure 8b Under the control of the timing signal shown, this application can also achieve a density of 2 / 4×8, which is approximately equal to 6% phase focus mode.

[0096] Figure 8c This is a timing diagram of the image sensor according to the third embodiment of this application when achieving an upper and lower phase information density of 6%. Figure 8c and Figure 8a The timing signals shown are basically the same, the only difference being that the high-level times of the first group of transmission control lines txap, txbp and the second group of transmission control lines txa, txb, txc, txd coincide. (The rest of the text appears to be unrelated and possibly machine-generated.) Figure 8c Under the control of the timing signal shown, this application can also achieve a phase-detection autofocus mode with a density of 2 / 4 × 8, which is approximately equal to 6%. For the specific principle, please refer to [link / reference needed]. Figure 8a The corresponding descriptions will not be repeated here.

[0097] It should be noted that other phase-detection autofocus ratios can also be achieved through the 8a-8c readout method. For example, 3% phase-detection autofocus can be achieved based on the design of the first set of transmission control lines and corresponding pixel units.

[0098] Figure 9 This is a timing diagram illustrating an image sensor according to an embodiment of this application when achieving a left and right phase information density of 6%. Please also refer to... Figure 1 and Figure 9 ,like Figure 1 As shown, in this 4×8 pixel array, the transmission transistors of the four pixels in the second and sixth columns of the n+2th row are connected to the first set of transmission control lines txap, txbp, txcp, and txdp, respectively, while the transmission transistors of the remaining pixel units are connected to the second set of transmission control lines txa, txb, txc, and txd.

[0099] Therefore, in such Figure 9Under the control of the timing signal shown, the pixel units in the 2nd and 6th columns of the (n+2)th row are used to acquire left and right phase information at different times. The remaining pixel units are used to acquire normal image information. For example, Figure 9 The left side of the vertical dividing line indicates reading data from rows 0-7 of the pixel array. Pixel units in these eight rows connected to the first set of transmission control lines acquire half of the phase information. Simultaneously, the right side of the vertical dividing line indicates reading data from rows 8-15 of the pixel array. Pixel units in these eight rows connected to the first set of transmission control lines acquire the other half of the phase information. Therefore, complete phase information can be obtained based on the pixel units in rows 0-15 connected to the first set of transmission control lines. Thus, in... Figure 9 Under the control of the timing signals shown, this application can achieve a phase focusing mode with a left and right phase information density of 6%. It should be noted that, in this mode, it can be understood that a pixel unit connected to the first set of transmission control lines is only used to acquire half of the phase information. Therefore, for the total number of pixel units used to acquire phase focusing information, the density of the acquired focusing information data is reduced by half. Of course, other density transformations can be designed by those skilled in the art according to actual needs.

[0100] In other embodiments, the timing of the first transmission control line txap and the second transmission control line txbp in the first group of transmission control lines txap, txbp, txcp, and txdp can be set to be the same, and the timing of the third transmission control line txcp and the fourth transmission control line txdp can be set to be the same, so as to achieve a phase focusing mode with an upper and lower phase information density of 6%.

[0101] Example 2

[0102] Please see Figure 10 ,like Figure 10 As shown, this embodiment provides an image sensor 100, including a pixel array 110. The pixel array 110 is arranged in rows and columns, and the structure of each pixel in the pixel array 110 can be as follows: Figure 2 and Figure 3 The pixel structure shown above is for reference only; please refer to the description above for details. It will not be repeated here.

[0103] In addition, as an illustrative embodiment, the image sensor also includes a logic control unit 120, a driving unit, a column A / D conversion unit 150, and an image processing unit 160; wherein:

[0104] The logic control unit 120 is used to control the working timing logic of the entire system;

[0105] One end of the driving unit is connected to the logic control unit 120, and the other end is coupled to the pixel array 110, for driving and controlling each control signal line in the pixel array 110; specifically, the driving unit includes a row driving unit 130 and a column driving unit 140. One end of the row driving unit 130 is connected to the logic control unit 120, and the other end is coupled to the pixel array 110, for providing corresponding row control signals to the pixel array 110; one end of the column driving unit 140 is connected to the logic control unit 120, and the other end is coupled to the pixel array 110, for providing corresponding column control signals to the pixel array 110;

[0106] The column A / D conversion unit 150 corresponds to each column of pixels in the pixel array 110 and is used to realize the analog-to-digital conversion of column signals under the control of the logic control unit 120;

[0107] The image processing unit 160 is used to perform image processing on the image digital signal output by the column A / D conversion unit 150 under the control of the logic control unit 120.

[0108] Example 3

[0109] This embodiment provides a control method for the above-mentioned pixel circuit. The control method includes: acquiring image information based on a first set of transmission control lines and a second set of transmission control lines. In this method, the first set of transmission control lines can be used as the function of the second set of transmission control lines. In an optional method, the control timing of the first set of transmission control lines and the second set of transmission control lines are the same, and the correspondence between the first set of transmission control lines and the pixel unit and the correspondence between the second set of transmission control lines and the pixel unit are consistent. The two can achieve the acquisition of traditional image information through corresponding timing control.

[0110] In addition, phase focus information is obtained based on the first set of transmission control lines and the second set of transmission control lines. That is, both are used to obtain focus information to achieve 100% phase focus. For the description of obtaining all phase focus information based on the first set of transmission control lines and the second set of transmission control lines, please refer to the above description, which will not be repeated here.

[0111] In addition, the solution of the present invention can also obtain phase focus information based on the first set of transmission control lines and obtain image information based on the second set of transmission control lines to achieve partial phase focus. For the partial phase focus information obtained based on the first set of transmission control lines and the second set of transmission control lines, please refer to the description above, which will not be repeated here.

[0112] In this embodiment, the control method includes single-row reading or parallel reading, wherein: during the reading process, by controlling the timing of the first set of transmission control lines and the second set of transmission control lines, phase focus information can be obtained based on different pixels in the same pixel unit connected to the first transmission control line; or, phase focus information can be obtained based on pixel units in different pixel unit rows connected to the first transmission control line.

[0113] Specifically, for the method of obtaining phase focus information based on different pixels in the same pixel unit connected to the first transmission control line, that is, in this method, each pixel unit in the pixel array connected to the first set of transmission control lines can independently obtain complete phase focus data. It can be considered that the density of phase focus data is the density of pixel units connected to the first set of transmission control lines.

[0114] Furthermore, regarding the method of obtaining phase focus information based on pixel units connected to the first transmission control line in different pixel unit rows, it can be understood that in the pixel array, each pixel unit connected to the first group of transmission control lines is used to obtain partial phase focus data, and at least two different pixel units are needed to obtain complete phase focus data. In this case, it can be considered that the density of phase focus data is less than the density of pixel units connected to the first group of transmission control lines.

[0115] In this embodiment, the method of obtaining phase focus information based on different pixel unit rows includes: the pixel array includes a first focus pixel row having a first pixel unit connected to a first transmission control line, and a second focus pixel row having a second pixel unit connected to a first transmission control line, wherein first focus information is obtained based on the first focus pixel row, and second focus information is obtained based on the second focus pixel row to obtain phase focus information.

[0116] Specifically, for example, the first focus information obtained from the first focus pixel row can be left and right phase information, and the second focus information obtained from the second focus pixel row can be up and down phase information.

[0117] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of this application. Therefore, if these modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; however, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0118] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0119] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element. Depending on the context, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0120] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes a plurality of pixel units arranged in an array, each pixel unit including: At least two pixels, each pixel including a photoelectric conversion element and a transfer transistor, the photoelectric conversion element being used to generate charge in response to incident light; the transfer transistor being coupled between the photoelectric conversion element and a floating diffusion node, being used to transfer the charge accumulated in the photoelectric conversion element during exposure to the floating diffusion node according to a transfer control signal; In this embodiment, at least one of the pixel transistors in at least one pixel unit is connected to the corresponding first group of transmission control lines, and the transmission transistors in the other pixel units are connected to the corresponding second group of transmission control lines. When the phase focus density is 100%, the timing of the transmission control signals received by the first set of transmission control lines is the same as that of the transmission control signals received by the second set of transmission control lines; when the phase focus density is not 100%, the timing of the transmission control signals received by the first set of transmission control lines is different from that of the second set of transmission control lines.

2. The pixel circuit as described in claim 1, characterized in that, At least two pixels in the same pixel unit share a single on-chip lens, and the at least two pixels sharing a single on-chip lens are connected to the corresponding first set of transmission control lines.

3. The pixel circuit as described in claim 1, characterized in that, All pixels in the same pixel unit share a single on-chip lens.

4. The pixel circuit as described in claim 1, characterized in that, The number of transmission control lines in the first group of transmission control lines is less than or equal to the number of pixels in the corresponding pixel unit.

5. The pixel circuit as described in claim 1, characterized in that, The number of transmission control lines in the first group of transmission control lines is greater than the number of pixels in the corresponding pixel unit.

6. The pixel circuit as described in claim 1, characterized in that, Each row of pixel units is provided with a corresponding first group of transmission control lines and a corresponding second group of transmission control lines.

7. The pixel circuit as described in claim 1, characterized in that, The pixel units in the nth row of the pixel circuit are arranged cyclically according to the first green and blue color filters, and the pixel units in the (n+1)th row are arranged cyclically according to the red and second green color filters; or, each pixel unit group includes four pixel units arranged in an array, and the four pixel units in each pixel unit group correspond to the first green, blue, second green and red color filters respectively in a clockwise direction; wherein, the pixel unit connected to the first group of transmission control lines is set at the position corresponding to the first green.

8. The pixel circuit as described in claim 1, characterized in that, In the same row of pixel units, there must be at least one pixel unit between two pixel units connected to the first set of transmission control lines.

9. The pixel circuit as described in claim 1, characterized in that, The pixel circuit also includes: A reset transistor is coupled between a first voltage source and the floating diffusion node; and / or, An amplification output unit, coupled to the floating diffusion node, is used to amplify and output the voltage signal of the floating diffusion node; and / or, A dual-conversion gain control unit, coupled between the reset transistor and the floating diffuse node, is used to implement gain control; and / or, A row selection transistor is coupled between the output terminal of the amplification output unit and the column output line. The gate of the row selection transistor receives a row selection control signal and is used to output the voltage signal of the floating diffusion node.

10. The pixel circuit according to any one of claims 1-9, characterized in that, Each pixel unit includes four pixels, and the four pixels in the same pixel unit share a single on-chip lens. The first group of transmission control lines each includes four transmission control lines. In this configuration, the transmission transistors of the four pixels in the pixel unit connected to the first group of transmission control lines are respectively connected to the four transmission control lines in the first group of transmission control lines.

11. The pixel circuit as described in claim 10, characterized in that, When the phase focus density is not 100%, the first sub-transmission control line and the second sub-transmission control line in the first group of transmission control lines receive the effective level transmission control signal at different times to obtain left and right phase information and / or up and down phase information. The four transmission control lines in the second group of transmission control lines receive the effective level transmission control signal to obtain image information. The first sub-transmission control line includes two transmission control lines connecting adjacent first pairs of pixels among the four pixels, and the second sub-transmission control line includes two transmission control lines connecting second pairs of pixels among the four pixels, excluding the first pair of pixels.

12. An image sensor, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 11.

13. A control method for a pixel circuit as described in any one of claims 1-11, characterized in that, The control method includes: Image information is acquired based on the first set of transmission control lines and the second set of transmission control lines; or, phase focus information is acquired based on the first set of transmission control lines and the second set of transmission control lines; or, phase focus information is acquired based on the first set of transmission control lines and image information is acquired based on the second set of transmission control lines.

14. The pixel circuit control method as described in claim 13, characterized in that, The control method includes single-line reading or parallel reading, wherein: During the reading process, phase focus information is obtained based on different pixels in the same pixel unit connected to the first group of transmission control lines; or, phase focus information is obtained based on pixel units in different rows of pixel units connected to the first group of transmission control lines.

15. The pixel circuit control method as described in claim 14, characterized in that, Methods for obtaining phase-detection autofocus information based on different pixel unit rows include: The pixel array has a first focusing pixel row with a first pixel unit connected to a first set of transmission control lines, and a second focusing pixel row with a second pixel unit connected to the first set of transmission control lines. First focusing information is obtained based on the first focusing pixel row, and second focusing information is obtained based on the second focusing pixel row to obtain phase focusing information.

Images