Dynamic random access memory structure and method of manufacturing the same

Abstract

A dynamic random access memory structure includes a substrate, a buried word line structure, a bit line structure, a contact window, a plurality of spacers, and a contact pad. The buried word line structure is located in the substrate. The bit line structure is located on the substrate at one side of the buried word line structure. The contact window is located on the substrate at another side of the buried word line structure. The spacers are located at two sides of the contact window. The contact pad is located on the contact window and between two adjacent spacers.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its manufacturing method, and more particularly to a dynamic random access memory (DRAM) structure and its manufacturing method. Background Technology

[0002] A dynamic random access memory (DRAM) has been developed, comprising transistors and capacitors coupled to each other. In this DRAM, capacitors are used as storage nodes. Furthermore, to increase storage density, the electrically connected capacitors and storage node contacts are often misaligned. However, misaligning the capacitors and storage node contacts results in higher contact resistance, and the etching process used to form the capacitors may cause punch-through issues, thus degrading the electrical performance of the memory element.

[0003] The common solution to the above problem is to add a pad between the storage node contact window and the capacitor. However, this pad usually requires two photomasks to fabricate, making the manufacturing process complex and costly. Summary of the Invention

[0004] This invention provides a dynamic random access memory structure and its manufacturing method, which can reduce the complexity of the manufacturing process and the manufacturing cost.

[0005] This invention proposes a dynamic random access memory (DRAM) structure, including a substrate, an embedded word line structure, a bit line structure, a contact window, multiple spacers, and pads. The embedded word line structure is located within the substrate. The bit line structure is located on the substrate on one side of the embedded word line structure. The contact window is located on the substrate on the other side of the embedded word line structure. The spacers are located on both sides of the contact window. The pads are located on the contact window and between adjacent spacers.

[0006] According to one embodiment of the present invention, in the above-described dynamic random access memory structure, the substrate located below the contact window may have a recess, and part of the contact window may be located in the recess.

[0007] According to one embodiment of the present invention, the above-described dynamic random access memory structure may further include a barrier layer. The barrier layer is located between the contact window and the substrate.

[0008] This invention proposes a method for manufacturing a dynamic random access memory (DRAM) structure, comprising the following steps: Providing a substrate. Forming an embedded word line structure in the substrate. Forming a bit line structure on the substrate on one side of the embedded word line structure. Forming a contact window on the substrate on the other side of the embedded word line structure. Forming a plurality of first gap walls on both sides of the contact window. Forming a pad on the contact window. The pad is located between two adjacent first gap walls.

[0009] According to an embodiment of the present invention, in the manufacturing method of the above-described dynamic random access memory structure, the bit line structure may include a bit line contact window, a bit line, and a hard mask layer. The bit line contact window is located on the substrate. The bit line is located on the bit line contact window. The hard mask layer is located on the bit line.

[0010] According to an embodiment of the present invention, in the manufacturing method of the above-described dynamic random access memory structure, the method for forming a contact window may include the following steps: A sacrificial layer is formed on a substrate. A plurality of first openings are formed in the sacrificial layer. A plurality of second spacer walls are formed in the plurality of first openings. The sacrificial layer is removed to form second openings, exposing the substrate. A contact window is formed in the second openings. The height of the top surface of the contact window may be lower than the height of the top surface of the second spacer wall, thus forming a first recess.

[0011] According to an embodiment of the present invention, in the manufacturing method of the above-described dynamic random access memory structure, the method for forming the pad and the first gap wall may include the following steps: Lowering the height of the hard mask layer so that a first recess extends above the hard mask layer. Forming a pad layer in the first recess. After forming the pad layer, removing the second gap wall to form a third opening. Forming the first gap wall in the third opening. The material of the first gap wall is different from the material of the second gap wall. Patterning the pad layer to form a pad.

[0012] According to an embodiment of the present invention, the manufacturing method of the above-described dynamic random access memory structure may further include the following step: After removing the sacrificial layer, a portion of the substrate may be removed, thereby forming a second recess in the substrate.

[0013] According to an embodiment of the present invention, in the manufacturing method of the above-described dynamic random access memory structure, the method for forming a contact window may include the following steps: forming a contact window layer on a substrate; patterning the contact window layer to form a contact window and a plurality of first openings.

[0014] According to an embodiment of the present invention, in the manufacturing method of the above-described dynamic random access memory structure, the method for forming the pads and the first gap walls may include the following steps: A plurality of second gap walls are formed in a plurality of first openings. The height of the hard mask layer and the height of the contact window are reduced, and a first recess is formed above the hard mask layer and the contact window. A pad layer is formed in the first recess. The pad layer is patterned to form a pad. After forming the pad, the second gap walls are removed to form a second opening. A first gap wall is formed in the second opening. The material of the first gap wall is different from the material of the second gap wall.

[0015] Based on the above, in the dynamic random access memory structure and manufacturing method proposed in this invention, the pad is located between two adjacent gap walls. Therefore, the pad only requires one photomask for fabrication, thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figures 1A to 1M This is a cross-sectional view of the manufacturing process of a dynamic random access memory structure according to an embodiment of the present invention.

[0018] Figures 2A to 2G They are respectively Figure 1A , Figure 1C , Figure 1G , Figure 1H , Figure 1J , Figure 1K and Figure 1L The top view.

[0019] Figures 3A to 3J This is a cross-sectional view of the manufacturing process of a dynamic random access memory structure according to another embodiment of the present invention.

[0020] Figures 4A to 4E They are respectively Figure 3A , Figure 3D , Figure 3E , Figure 3F and Figure 3G The top view.

[0021] [Symbol Explanation]

[0022] 10,20: Dynamic Random Access Memory Architecture

[0023] 100, 200: Base

[0024] 102,202: Isolation Structure

[0025] 104,204: Embedded character line structure

[0026] 106,206: Embedded letter lines

[0027] 108, 138, 208, 238: Dielectric layer

[0028] 110, 210: Top cover layer

[0029] 112,212: Bitline structure

[0030] 114,214: Bitline contact window

[0031] 116,216: Bit lines

[0032] 118, 218: Hard mask layer

[0033] 120,122,124,220,222,224: Lining

[0034] 126: Sacrificial Layer

[0035] 128,134,230,236a: Spacer wall

[0036] 130,226a: Contact window

[0037] 132,232: Substrate layer

[0038] 132a, 232a: Gaskets

[0039] 136,234: Patterned hard mask layer

[0040] 140, 240: Capacitor Structure

[0041] 226: Contact window layer

[0042] 228, 228a: Barrier layer

[0043] 236: Spacer wall material layer

[0044] AA1, AA2: Active (Active) Region

[0045] OP1~OP5: Opening

[0046] R1~R3: Depression

[0047] TS1~TS10: Top surface Detailed Implementation

[0048] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, the features in the top view and the features in the sectional view are not drawn to scale. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0049] Figures 1A to 1M This is a cross-sectional view of the manufacturing process of a dynamic random access memory structure according to an embodiment of the present invention. Figures 2A to 2G They are respectively Figure 1A , Figure 1C , Figure 1G , Figure 1H , Figure 1J , Figure 1K and Figure 1L The top view. Figures 1A to 1M It is along Figure 2A The manufacturing process cross-sectional view of section line I-I' in this embodiment is shown. In the top view of this embodiment, some components are omitted from the cross-sectional view in order to clearly illustrate the positional relationship between the components in the top view.

[0050] Please refer to Figure 1A and Figure 2A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 may define an active region AA1 in the substrate 100. Figure 2A The isolation structure 102 can be a single-layer or multi-layer structure. For example, the isolation structure 102 is a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide, silicon nitride, or a combination thereof. Furthermore, desired doped regions (not shown) can be formed in the substrate 100 according to product requirements.

[0051] Next, an embedded word line structure 104 is formed in the substrate 100. Partially, the embedded word line structure 104 may be located within the isolation structure 102. The embedded word line structure 104 may include embedded word lines 106 and a dielectric layer 108. The embedded word lines 106 are located in the substrate 100. The material of the embedded word lines 106 is, for example, tungsten. The dielectric layer 108 is located between the embedded word lines 106 and the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. Furthermore, the embedded word line structure 104 may further include a capping layer 110. The capping layer 110 is located on the embedded word lines 106. The material of the capping layer 110 is, for example, silicon nitride. Additionally, the dielectric layer 108 may be located between the capping layer 110 and the substrate 100.

[0052] Then, a bit line structure 112 is formed on a substrate 100 on one side of the embedded word line structure 104. The bit line structure 112 may include a bit line contact window 114, a bit line 116, and a hard mask layer 118. The bit line contact window 114 is located on the substrate 100. The material of the bit line contact window 114 is, for example, doped polysilicon. The bit line 116 is located on the bit line contact window 114. The material of the bit line 116 is, for example, tungsten. The hard mask layer 118 is located on the bit line 116. The material of the hard mask layer 118 is, for example, silicon nitride. Furthermore, a liner 120 may be formed on the sidewall of the bit line structure 112. The liner 120 may be a single-layer structure or a multi-layer structure. In this embodiment, the liner 120 may be a multi-layer structure. For example, the liner 120 may include a liner 122 and a liner 124. The liner 122 is located on the sidewall of the bit line structure 112. The material of the liner 122 is, for example, silicon oxide. Substrate 124 is located on substrate 122. The material of substrate 122 is, for example, silicon nitride.

[0053] Next, a sacrificial layer 126 may be formed on the substrate 100. The material of the sacrificial layer 126 may be, for example, germanium. In some embodiments, the method of forming the sacrificial layer 126 may include the following steps. First, a sacrificial material layer (not shown) covering the bit line structure 112 may be formed on the substrate 100. Then, using a hard mask layer 118 as a terminating layer, the sacrificial material layer may be subjected to a chemical mechanical polishing process and / or an etch-back process to form the sacrificial layer 126.

[0054] Please refer to Figure 1B Multiple openings OP1 can be formed in the sacrificial layer 126. The openings OP1 can be located above the embedded word line structure 104. The openings OP1 can be formed, for example, by patterning the sacrificial layer 126. In some embodiments, the sacrificial layer 126 can be patterned using a photolithography process and an etching process. In other embodiments, patterning the sacrificial layer 126 may include the following steps: First, a patterned mask layer (not shown) can be formed using a self-alignment double patterning (SADP) process. Then, the patterned mask layer can be used as a mask to perform a dry etching process on the sacrificial layer 126.

[0055] Please refer to Figure 1C and Figure 2B Multiple spacer walls 128 can be formed in multiple openings OP1. The material of the spacer walls 128 is, for example, silicon oxide. The method of forming the spacer walls 128 may include the following steps. First, a spacer wall material layer (not shown) filling the openings OP1 can be formed. Next, the spacer wall material layer located outside the openings OP1 can be removed to form the spacer walls 128. The method for removing the spacer wall material layer located outside the openings OP1 is, for example, chemical mechanical polishing, etch-back, or a combination thereof.

[0056] Please refer to Figure 1D The sacrificial layer 126 can be removed to form an opening OP2 and expose the substrate 100. The method for removing the sacrificial layer 126 is, for example, wet etching.

[0057] Please refer to Figure 1E After removing the sacrificial layer 126, a portion of the substrate 100 can be removed, forming a recess R1 in the substrate 100. The method for removing the portion of the substrate 100 is, for example, dry etching.

[0058] Please refer to Figure 1F A contact window 130 can be formed in the opening OP2. Thus, the contact window 130 can be formed on the substrate 100 on the other side of the embedded word line structure 104. The contact window 130 can be used as a storage node contact window. A portion of the contact window 130 can be located in a recess R1, thereby increasing the contact area between the contact window 130 and the substrate 100. The height of the top surface TS1 of the contact window 130 can be lower than the height of the top surface TS2 of the spacer wall 128, forming a recess R2. The material of the contact window 130 is, for example, doped polysilicon. In some embodiments, the method of forming the contact window 130 may include the following steps: First, a contact window material layer (not shown) filling the opening OP2 can be formed. Next, a portion of the spacer wall material layer can be removed to form the contact window 130. The method for removing a portion of the spacer wall material layer is, for example, to first perform a chemical mechanical polishing process on the spacer wall material layer, and then perform an etching process (e.g., a dry etching process) on the spacer wall material layer.

[0059] Please refer to Figure 1G and Figure 2C This allows the height of the hard mask layer 118 to be reduced, causing the recess R2 to extend above the hard mask layer 118. Consequently, the height of the top surface TS3 of the hard mask layer 118 can be lower than the height of the top surface TS2 of the spacer wall 128. In some embodiments, the height of the hard mask layer 118 can be reduced using a dry etching process. Furthermore, the height of the substrate 120 can be reduced, causing the recess R2 to extend above the substrate 120. Additionally, the height of the substrate 120 can be reduced using a dry etching process.

[0060] Please refer to Figure 1H and Figure 2D A pad layer 132 can be formed in the recess R2. Furthermore, the top view shape of the pad layer 132 can be strip-shaped. Figure 2DThe material of the pad layer 132 is, for example, tungsten. In some embodiments, the method of forming the pad layer 132 may include the following steps. First, a pad material layer (not shown) filling the recess R2 may be formed. Next, the pad material layer located outside the recess R2 may be removed to form the pad layer 132. The method for removing the pad material layer located outside the recess R2 is, for example, chemical mechanical polishing, etch-back, or a combination thereof. In this embodiment, the height of the pad layer 132 may be equal to the height of the spacer wall 128, but the invention is not limited thereto. In other embodiments, the height of the pad layer 132 may be reduced by etch-back, such that the height of the pad layer 132 is lower than the height of the spacer wall 128.

[0061] Please refer to Figure 1I After the pad layer 132 is formed, the spacer wall 128 can be removed to form the opening OP3. The spacer wall 128 can be removed, for example, by wet etching.

[0062] Please refer to Figure 1J and Figure 2E A gap wall 134 can be formed in the opening OP3. Thus, multiple gap walls 134 can be formed on both sides of the contact window 130. The material of the gap wall 134 is different from the material of the gap wall 128. For example, the material of the gap wall 134 can be silicon nitride, and the material of the gap wall 128 can be silicon oxide. In some embodiments, the method of forming the gap wall 134 may include the following steps: First, a gap wall material layer (not shown) filling the opening OP3 can be formed. Then, the gap wall material layer located outside the opening OP3 can be removed to form the gap wall 134. The method for removing the gap wall material layer located outside the opening OP3 is, for example, chemical mechanical polishing, etch-back, or a combination thereof. In this embodiment, the height of the gap wall 134 may be equal to the height of the pad layer 132, but the invention is not limited thereto. In other embodiments, the height of the gap wall 134 can be reduced by etch-back, so that the height of the gap wall 134 is lower than the height of the pad layer 132.

[0063] Please refer to Figure 1K and Figure 2F A patterned hard mask layer 136 can be formed on the pad layer 132 and the spacer wall 134. The patterned hard mask layer 136 exposes a portion of the pad layer 132. In some embodiments, the patterned hard mask layer 136 may also expose a portion of the spacer wall 134. The material of the patterned hard mask layer 136 is, for example, silicon nitride. In some embodiments, the patterned hard mask layer 136 can be formed by a deposition process, a photolithography process, and an etching process. In some embodiments, the patterned hard mask layer 136 can be formed by a self-aligned double patterning (SADP) process.

[0064] Please refer to Figure 1L and Figure 2G The pad layer 132 exposed by the patterned hard mask layer 136 is removed. This allows the pad layer 132 to be patterned to form a pad 132a. In this way, a pad 132a can be formed on the contact window 130. In some embodiments, the pad 132a can be used as a landing pad for the electrodes of a capacitor. The pad 132a is located between two adjacent gap walls 134. The height of the top surface TS4 of the pad 132a may be equal to the height of the top surface TS5 of the gap wall 134. Part of the pad 132a may be located above the bit line structure 120. Furthermore, the top view shape of the pad 132a may be blocky. Figure 2G The method for removing the pad layer 132 exposed by the patterned hard mask layer 136 is, for example, dry etching.

[0065] In this embodiment, the height of the top surface TS4 of the pad 132a is taken as an example, equal to the height of the top surface TS5 of the spacer wall 134, but the present invention is not limited thereto. In other embodiments, the height can be reduced by etching back. Figure 1J The height of the gap wall 134 is adjusted so that the height of the top surface TS4 of the pad 132a is higher than the height of the top surface TS5 of the gap wall 134.

[0066] Please refer to Figure 1M A dielectric layer 138 and a capacitor structure 140 located within the dielectric layer 138 can be formed. The capacitor structure 140 is electrically connected to a pad 132a. Furthermore, a portion of the capacitor structure 140 may be located within a patterned hard mask layer 136. The dielectric layer 138 can be a single-layer or multi-layer structure. The capacitor structure 140 can serve as a storage node in the dynamic random access memory structure 10. Furthermore, the capacitor structure 140 can be various capacitors suitable for dynamic random access memory (e.g., cylinder capacitors). Figure 1M In this drawing, the capacitor structure 140 is schematically illustrated to simplify the illustration. Furthermore, the fabrication processes of the dielectric layer 138 and the capacitor structure 140 are well known to those skilled in the art, and therefore their description is omitted here.

[0067] The following is through Figure 1M The dynamic random access memory structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the dynamic random access memory structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0068] Please refer to Figure 1MThe dynamic random access memory (DRAM) structure 10 includes a substrate 100, an embedded word line structure 104, a bit line structure 112, a contact window 130, a plurality of spacer walls 134, and pads 132a. The embedded word line structure 104 is located within the substrate 100. The bit line structure 112 is located on the substrate 100 on one side of the embedded word line structure 104. The contact window 130 is located on the substrate 100 on the other side of the embedded word line structure 104. In some embodiments, the substrate 100 below the contact window 130 may have a recess R1, and a portion of the contact window 130 is located within the recess R1. The spacer walls 134 are located on both sides of the contact window 130. The pads 132a are located on the contact window 130 and between two adjacent spacer walls 134. In this embodiment, the height of the top surface TS4 of the pad 132a may be equal to the height of the top surface TS5 of the spacer wall 134, but the invention is not limited thereto. In other embodiments, the height of the top surface TS4 of the pad 132a may be higher than the height of the top surface TS5 of the spacer wall 134.

[0069] Furthermore, the remaining components in the dynamic random access memory structure 10 can be described with reference to the above embodiments. Additionally, the materials, arrangement, formation methods, and functions of each component in the dynamic random access memory structure 10 have been described in detail in the above embodiments and will not be repeated here.

[0070] As can be seen from the above embodiments, in the dynamic random access memory structure 10 and its manufacturing method, the pad 132a is located between two adjacent gap walls 134. Therefore, the pad 132a only requires one photomask to be manufactured, thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0071] Figures 3A to 3J This is a cross-sectional view of the manufacturing process of a dynamic random access memory structure according to another embodiment of the present invention. Figures 4A to 4E They are respectively Figure 3A , Figure 3D , Figure 3E , Figure 3F and Figure 3G Top view Figures 3A to 3J It is along Figure 4A The manufacturing process cross-sectional view of section line II-II' is shown in the diagram. In the top view of this embodiment, some components are omitted from the cross-sectional view in order to clearly illustrate the positional relationship between the components in the top view.

[0072] Please refer to Figure 3A and Figure 4A A substrate 200 is provided. The substrate 200 may be a semiconductor substrate, such as a silicon substrate. Furthermore, an isolation structure 202 may be formed in the substrate 200. The isolation structure 202 may define an active region AA2 in the substrate 200. Figure 4AThe isolation structure 202 can be a single-layer or multi-layer structure. The isolation structure 202 is, for example, a shallow trench isolation structure. The material of the isolation structure 202 is, for example, silicon oxide, silicon nitride, or a combination thereof. Furthermore, desired doped regions (not shown) can be formed in the substrate 200 according to product requirements.

[0073] Next, a buried word line structure 204 is formed in the substrate 200. Partially, the buried word line structure 204 may be located within the isolation structure 202. The buried word line structure 204 may include buried word lines 206 and a dielectric layer 208. The buried word lines 206 are located in the substrate 200. The material of the buried word lines 206 is, for example, tungsten. The dielectric layer 208 is located between the buried word lines 206 and the substrate 200. The material of the dielectric layer 208 is, for example, silicon oxide. Furthermore, the buried word line structure 204 may further include a capping layer 210. The capping layer 210 is located on the buried word lines 206. The material of the capping layer 210 is, for example, silicon nitride. Additionally, the dielectric layer 208 may be located between the capping layer 210 and the substrate 200.

[0074] Then, a bit line structure 212 is formed on a substrate 200 on one side of the embedded word line structure 204. The bit line structure 212 may include a bit line contact window 214, a bit line 216, and a hard mask layer 218. The bit line contact window 214 is located on the substrate 200. The material of the bit line contact window 214 is, for example, doped polysilicon. The bit line 216 is located on the bit line contact window 214. The material of the bit line 216 is, for example, tungsten. The hard mask layer 218 is located on the bit line 216. The material of the hard mask layer 218 is, for example, silicon nitride. Furthermore, a liner 220 may be formed on the sidewall of the bit line structure 212. The liner 220 may be a single-layer structure or a multi-layer structure. In this embodiment, the liner 220 may be a multi-layer structure. For example, the liner 220 may include a liner 222 and a liner 224. The liner 222 is located on the sidewall of the bit line structure 212. The material of the liner 222 is, for example, silicon oxide. Substrate 224 is located on substrate 222. The material of substrate 222 is, for example, silicon nitride.

[0075] Next, a contact window layer 226 may be formed on the substrate 200. The material of the contact window layer 226 may be, for example, doped polysilicon. In some embodiments, a barrier layer 228 may be formed between the contact window layer 226 and the substrate 200, between the contact window layer 226 and the embedded word line structure 204, and between the contact window layer 226 and the substrate 220. The material of the barrier layer 228 may be, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the method of forming the contact window layer 226 and the barrier layer 228 may include the following steps. First, a barrier material layer (not shown) covering the bit line structure 212 may be conformally formed on the substrate 200. Next, a contact window material layer (not shown) may be formed on the barrier material layer. Next, using a hard mask layer 218 as a terminating layer, the contact window material layer and the barrier material layer may be formed by a chemical mechanical polishing process and / or an etch-back process.

[0076] Please refer to Figure 3B The contact window layer 226 is patterned to form a contact window 226a and a plurality of openings OP4. Thus, the contact window 226a can be formed on the substrate 200 on the other side of the embedded word line structure 204. The contact window 226a can be used as a memory node contact window. In some embodiments, the contact window layer 226 can be patterned using photolithography and etching processes. In other embodiments, the method of patterning the contact window layer 226 may include the following steps: First, a patterned mask layer (not shown) can be formed using a self-aligned double patterning (SADP) process. Then, using the patterned mask layer as a mask, a dry etching process is performed on the contact window layer 226. During the above patterning process, the barrier layer 228 can be used as an etching stop layer. Furthermore, the barrier layer 228 exposed by the openings OP4 can be removed to form a barrier layer 228a. The method for removing the barrier layer 228 exposed by the openings OP4 is, for example, a wet etching process.

[0077] Please refer to Figure 3C Multiple spacer walls 230 are formed in multiple openings OP4. The material of the spacer walls 230 is, for example, silicon oxide. The method for forming the spacer walls 230 may include the following steps. First, a spacer wall material layer (not shown) filling the openings OP4 may be formed. Next, the spacer wall material layer located outside the openings OP4 may be removed to form the spacer walls 230. The method for removing the spacer wall material layer located outside the openings OP4 is, for example, chemical mechanical polishing, etch-back, or a combination thereof.

[0078] Please refer to Figure 3D and Figure 4BThe height of the hard mask layer 218 and the contact window 226a are reduced, and a recess R3 is formed above the hard mask layer 218 and the contact window 226a. Here, the height of the top surface TS6 of the hard mask layer 218 can be lower than the height of the top surface TS7 of the spacer wall 230, and the height of the top surface TS8 of the contact window 226a can be lower than the height of the top surface TS7 of the spacer wall 230. In some embodiments, the height of the hard mask layer 218 can be reduced first, and then the height of the contact window 226a can be reduced. In other embodiments, the height of the contact window 226a can be reduced first, and then the height of the hard mask layer 218 can be reduced. In some embodiments, the height of the hard mask layer 218 and the height of the contact window 226a can be reduced separately using a dry etching process. Furthermore, the height of the substrate 220 can be reduced so that the recess R3 extends above the substrate 220. Alternatively, the height of the substrate 220 can be reduced using a dry etching process.

[0079] Please refer to Figure 3E and Figure 4C A pad layer 232 can be formed in the recess R3. Furthermore, the top view shape of the pad layer 232 can be strip-shaped. Figure 4C The material of the pad layer 232 is, for example, tungsten. In some embodiments, the method of forming the pad layer 232 may include the following steps. First, a pad material layer (not shown) filling the recess R3 may be formed. Next, the pad material layer located outside the recess R3 may be removed to form the pad layer 232. The method for removing the pad material layer located outside the recess R3 is, for example, chemical mechanical polishing, etch-back, or a combination thereof. In this embodiment, the height of the pad layer 232 may be equal to the height of the spacer wall 230, but the invention is not limited thereto. In other embodiments, the height of the pad layer 232 may be reduced by etch-back, such that the height of the pad layer 232 is lower than the height of the spacer wall 230.

[0080] Please refer to Figure 3F and Figure 4D A patterned hard mask layer 234 can be formed on the pad layer 232 and the spacer wall 230. The patterned hard mask layer 234 exposes a portion of the pad layer 232. In some embodiments, the patterned hard mask layer 234 may also expose a portion of the spacer wall 230. The material of the patterned hard mask layer 234 is, for example, silicon oxide. In some embodiments, the patterned hard mask layer 234 can be formed by a deposition process, a photolithography process, and an etching process. In some embodiments, the patterned hard mask layer 234 can be formed by a self-aligned double patterning (SADP) process.

[0081] Please refer to Figure 3G and Figure 4EThe pad layer 232 exposed by the patterned hard mask layer 234 is removed. This allows the pad layer 232 to be patterned to form a pad 232a. In this way, a pad 232a can be formed on the contact window 226a. In some embodiments, the pad 226a can be used as a landing pad for the electrode of a capacitor. The pad 232a is located between two adjacent gap walls 230. A portion of the pad 232a may be located above the bit line structure 220. Furthermore, the top view shape of the pad 232a may be blocky (…). Figure 4E The method for removing the pad layer 232 exposed by the patterned hard mask layer 234 is, for example, dry etching.

[0082] Please refer to Figure 3H After forming the pad 232a, the patterned hard mask layer 234 and the spacer wall 230 can be removed to form the opening OP5. In some embodiments, when the patterned hard mask layer 234 and the spacer wall 230 are made of the same material, the patterned hard mask layer 234 and the spacer wall 230 can be removed simultaneously in the same etching process. The method for removing the patterned hard mask layer 234 and the spacer wall 230 is, for example, wet etching.

[0083] Please refer to Figure 3I A spacer wall material layer 236 can be formed in the opening OP5. The material of the spacer wall material layer 236 is, for example, silicon nitride. The method for forming the spacer wall material layer 236 is, for example, chemical vapor deposition.

[0084] Please refer to Figure 3J A dielectric layer 238 and a capacitor structure 240 located within the dielectric layer 238 can be formed. The capacitor structure 240 is electrically connected to a pad 232a. The dielectric layer 238 can be a single-layer or multi-layer structure. The capacitor structure 240 can serve as a storage node of the dynamic random access memory structure 20. Furthermore, the capacitor structure 240 can be various capacitors suitable for dynamic random access memory (e.g., cylindrical capacitors). Figure 3J In this drawing, the capacitor structure 240 is schematically illustrated to simplify the illustration. Furthermore, the fabrication processes of the dielectric layer 238 and the capacitor structure 240 are well known to those skilled in the art, and therefore their description is omitted here.

[0085] Furthermore, during the formation of capacitor structure 240, a portion of the spacer wall material layer 236 is removed, resulting in spacer walls 236a formed in opening OP5. This allows multiple spacer walls 236a to be formed on both sides of contact window 226a. A pad 232a is located between two adjacent spacer walls 236a, and the height of the top surface TS9 of pad 232a may be lower than the height of the top surface TS10 of spacer wall 236a. The material of spacer wall 236a differs from that of spacer wall 230. For example, spacer wall 236a may be made of silicon nitride, while spacer wall 230 may be made of silicon oxide.

[0086] In this embodiment, the height of the top surface TS9 of the pad 232a is taken as an example, being lower than the height of the top surface TS10 of the gap wall 236a, but the present invention is not limited thereto. In other embodiments, this can be achieved by adjusting... Figure 3I The spacer wall material layer 236 is formed by a back etching process to form the spacer wall 236a, and the height of the top surface TS9 of the pad 232a can be equal to or higher than the height of the top surface TS10 of the spacer wall 236a.

[0087] The following is through Figure 3J The dynamic random access memory structure 20 of the above embodiment will be explained here. Furthermore, although the method for forming the dynamic random access memory structure 20 is described using the above method as an example, the present invention is not limited thereto.

[0088] Please refer to Figure 3J The dynamic random access memory (DRAM) structure 20 includes a substrate 200, an embedded word line structure 204, a bit line structure 212, a contact window 226a, multiple spacer walls 236a, and pads 232a. The embedded word line structure 204 is located within the substrate 200. The bit line structure 212 is located on the substrate 200 on one side of the embedded word line structure 204. The contact window 226a is located on the substrate 200 on the other side of the embedded word line structure 204. The spacer walls 236a are located on both sides of the contact window 226a. The pads 232a are located on the contact window 226a and between adjacent spacer walls 236a. In this embodiment, the height of the top surface TS9 of the pad 232a is lower than the height of the top surface TS10 of the spacer wall 236a, but this is not a limitation of the invention. In other embodiments, the height of the top surface TS9 of the pad 232a may be equal to or higher than the height of the top surface TS10 of the spacer wall 236a. Furthermore, the dynamic random access memory structure 20 may also include a barrier layer 228a. The barrier layer 228a is located between the contact window 226a and the substrate 200.

[0089] Furthermore, the remaining components in the dynamic random access memory structure 20 can be described with reference to the above embodiments. Additionally, the materials, arrangement, formation methods, and functions of each component in the dynamic random access memory structure 20 have been described in detail in the above embodiments and will not be repeated here.

[0090] As can be seen from the above embodiments, in the dynamic random access memory structure 20 and its manufacturing method, the pad 232a is located between two adjacent gap walls 236a. Therefore, the pad 232a only requires one photomask to be manufactured, thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0091] In summary, in the dynamic random access memory structure and manufacturing method of the above embodiments, since the pads are located between two adjacent gap walls, the manufacturing process of the pads can be simplified. Furthermore, the pads only require one photomask for fabrication, thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0092] Although the present invention is disclosed in conjunction with the embodiments, it is not intended to limit the invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for manufacturing a dynamic random access memory (DRAM) structure, comprising: Provide a base; An embedded character line structure is formed in the substrate; A bit line structure is formed on the substrate on one side of the embedded word line structure; A contact window is formed on the substrate on the other side of the embedded letter line structure; Multiple first gap walls are formed on both sides of the contact window; as well as A pad is formed on the contact window, wherein the pad is located between two adjacent first gap walls; The method for forming the contact window includes: A sacrificial layer is formed on the substrate; Multiple first openings are formed in the sacrificial layer; Multiple second gap walls are formed in the multiple first openings; The sacrificial layer is removed to form a second opening, exposing the substrate; and The contact window is formed in the second opening, wherein the height of the top surface of the contact window is lower than the height of the top surface of the second gap wall, thus forming a first recess.

2. The method for manufacturing a dynamic random access memory structure as described in claim 1, wherein the bit line structure comprises: Bit line contact window, located on the substrate; Bit lines are located on the bit line contact window; as well as A hard mask layer is located on the bit line.

3. The method for manufacturing a dynamic random access memory structure as described in claim 2, wherein the method for forming the pad and the first gap wall includes: The height of the hard mask layer is reduced so that the first recess extends above the hard mask layer; A padding layer is formed in the first depression; After the pad layer is formed, the second gap wall is removed to form the third opening; The first gap wall is formed in the third opening, wherein the material of the first gap wall is different from the material of the second gap wall; as well as The pad layer is patterned to form the pad.

4. The method for manufacturing a dynamic random access memory structure as described in claim 1, further comprising: After the sacrificial layer is removed, a portion of the substrate is removed, forming a second depression in the substrate.

5. A method for manufacturing a dynamic random access memory (DRAM) structure, comprising: Provide a base; An embedded character line structure is formed in the substrate; A bit line structure is formed on the substrate on one side of the embedded word line structure; A contact window is formed on the substrate on the other side of the embedded letter line structure; Multiple first gap walls are formed on both sides of the contact window; as well as A pad is formed on the contact window, wherein the pad is located between two adjacent first gap walls; The method for forming the contact window includes: A contact window layer is formed on the substrate; as well as The contact window layer is patterned to form the contact window and a plurality of first openings.

6. The method for manufacturing a dynamic random access memory structure as described in claim 5, wherein the bit line structure comprises: Bit line contact window, located on the substrate; Bit lines are located on the bit line contact window; as well as A hard mask layer is located on the bit line.

7. The method for manufacturing a dynamic random access memory structure as described in claim 6, wherein the method for forming the pad and the first gap wall includes: Multiple second gap walls are formed in the multiple first openings; The height of the hard mask layer and the height of the contact window are reduced, and a first recess is formed above the hard mask layer and the contact window; A padding layer is formed in the first depression; The pad layer is patterned to form the pad; After the pad is formed, the second gap wall is removed to form the second opening; as well as The first gap wall is formed in the second opening, wherein the material of the first gap wall is different from the material of the second gap wall.

8. A dynamic random access memory structure manufactured by the method according to any one of claims 1 to 7, comprising: Base; An embedded character line structure is located in the substrate; The bit line structure is located on the substrate on one side of the embedded word line structure; A contact window is located on the substrate on the other side of the embedded letter line structure; Multiple gap walls are located on both sides of the contact window; as well as A contact pad is located on the contact window and between two adjacent gap walls.

9. The dynamic random access memory structure of claim 8, wherein the substrate located below the contact window has a recess, and a portion of the contact window is located in the recess.

10. The dynamic random access memory structure as described in claim 8, further comprising: A barrier layer is located between the contact window and the substrate.

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